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Diffstat (limited to 'plugins/arm/v7/arm.c')
| -rw-r--r-- | plugins/arm/v7/arm.c | 2271 |
1 files changed, 2271 insertions, 0 deletions
diff --git a/plugins/arm/v7/arm.c b/plugins/arm/v7/arm.c new file mode 100644 index 0000000..89a17b6 --- /dev/null +++ b/plugins/arm/v7/arm.c @@ -0,0 +1,2271 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * arm.c - désassemblage des instructions ARMv7 + * + * Copyright (C) 2014-2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "arm.h" + + +#include <stdint.h> + + +#include <arch/undefined.h> +#include <common/bconst.h> + + +#include "simd.h" +#include "opcodes/arm_opcodes.h" +#include "opcodes/opcodes_tmp_arm.h" + + + +/* Désassemble une instruction ARMv7 de données ou autre. */ +static GArchInstruction *process_armv7_arm_data_processing_and_miscellaneous_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.1. */ +static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.2. */ +static GArchInstruction *process_armv7_arm_data_processing_register_shifted_register(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.3. */ +static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.5. */ +static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.6. */ +static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.7. */ +static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumulate(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.8. */ +static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.9. */ +static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivileged(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.10. */ +static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.11. */ +static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.2.12. */ +static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.3. */ +static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.4. */ +static GArchInstruction *process_armv7_arm_media_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.4.1. */ +static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_signed(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.4.2. */ +static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_unsigned(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.4.3. */ +static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.4.4. */ +static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_divide(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.5. */ +static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_data_transfer(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.6. */ +static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervisor_call(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.7. */ +static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A5.7.1. */ +static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t); + + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.1. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArchInstruction *process_armv7_arm_instruction_set_encoding(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t cond; /* Champ 'cond' à retrouver */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.1 ARM instruction set encoding + */ + + result = NULL; + + cond = (raw >> 28) & 0xf; + op1 = (raw >> 25) & 0x7; + op = (raw >> 4) & 0x1; + + if (cond != b1111) + { + if ((op1 & b110) == b000) + result = process_armv7_arm_data_processing_and_miscellaneous_instructions(raw); + + else if (op1 == b010) + result = process_armv7_arm_load_store_word_and_unsigned_byte(raw); + + else if (op1 == b011) + { + if (op == b0) + result = process_armv7_arm_load_store_word_and_unsigned_byte(raw); + + else/* if (op == b1)*/ + result = process_armv7_arm_media_instructions(raw); + + } + + else if ((op1 & b110) == b100) + result = process_armv7_arm_branch_branch_with_link_and_block_data_transfer(raw); + + else if ((op1 & b110) == b110) + result = process_armv7_arm_coprocessor_instructions_and_supervisor_call(raw); + + } + + else /* if (cond == b1111) */ + result = process_armv7_arm_unconditional_instructions(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 de données ou autre. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_data_processing_and_miscellaneous_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2 Data-processing and miscellaneous instructions + */ + + result = NULL; + + op = (raw >> 25) & 0x1; + op1 = (raw >> 20) & 0x1f; + op2 = (raw >> 4) & 0xf; + + if (op == b0) + { + if ((op1 & b11001) != b10000) + { + if ((op2 & b0001) == b0000) + result = process_armv7_arm_data_processing_register(raw); + + else if ((op2 & b1001) == b0001) + result = process_armv7_arm_data_processing_register_shifted_register(raw); + + if (result != NULL) goto padpami_found; + + } + + else /* if ((op1 & b11001) == b10000) */ + { + if ((op2 & b1000) == b0000) + result = process_armv7_arm_miscellaneous_instructions(raw); + + else if ((op2 & b1001) == b1000) + result = process_armv7_arm_halfword_multiply_and_multiply_accumulate(raw); + + if (result != NULL) goto padpami_found; + + } + + if ((op1 & b10000) == b00000) + { + if (op2 == b1001) + result = process_armv7_arm_multiply_and_multiply_accumulate(raw); + + if (result != NULL) goto padpami_found; + + } + + if ((op1 & b10000) == b10000) + { + if (op2 == b1001) + result = process_armv7_arm_synchronization_primitives(raw); + + if (result != NULL) goto padpami_found; + + } + + if ((op1 & b10010) != b00010) + { + if (op2 == b1011) + result = process_armv7_arm_extra_load_store_instructions(raw); + + else if ((op2 & b1101) == b1101) + result = process_armv7_arm_extra_load_store_instructions(raw); + + if (result != NULL) goto padpami_found; + + } + + else /* if ((op1 & b10010) != b00010) */ + { + if (op2 == b1011) + result = process_armv7_arm_extra_load_store_instructions_unprivileged(raw); + + else if ((op2 & b1101) == b1101) + result = process_armv7_arm_extra_load_store_instructions(raw); + + if (result != NULL) goto padpami_found; + + } + + } + + else + { + if ((op1 & b11001) != b10000) + result = process_armv7_arm_data_processing_immediate(raw); + + else if (op1 == b10000) + result = armv7_read_arm_instr_mov_immediate(raw); + + else if (op1 == b10100) + result = armv7_read_arm_instr_movt(raw); + + else if ((op1 & b11011) == b10010) + result = process_armv7_arm_msr_immediate_and_hints(raw); + + } + + padpami_found: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.1. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t imm5; /* Champ 'imm5' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.1 Data-processing (register) + */ + + if ((raw & 0x0e000010) != 0x00000000) return NULL; + + result = NULL; + + op = (raw >> 20) & 0x1f; + imm5 = (raw >> 7) & 0x1f; + op2 = (raw >> 5) & 0x3; + + if ((op & b11110) == b00000) + result = armv7_read_arm_instr_and_register(raw); + + else if ((op & b11110) == b00010) + result = armv7_read_arm_instr_eor_register(raw); + + else if ((op & b11110) == b00100) + result = armv7_read_arm_instr_sub_register(raw); + + else if ((op & b11110) == b00110) + result = armv7_read_arm_instr_rsb_register(raw); + + else if ((op & b11110) == b01000) + result = armv7_read_arm_instr_add_register_arm(raw); + + else if ((op & b11110) == b01010) + result = armv7_read_arm_instr_adc_register(raw); + + else if ((op & b11110) == b01100) + result = armv7_read_arm_instr_sbc_register(raw); + + else if ((op & b11110) == b01110) + result = armv7_read_arm_instr_rsc_register(raw); + + /* + else if ((op & b11001) == b10000) + result = process_armv7_arm_data_processing_and_miscellaneous_instructions(raw); + */ + + else if (op == b10001) + result = armv7_read_arm_instr_tst_register(raw); + + else if (op == b10011) + result = armv7_read_arm_instr_teq_register(raw); + + else if (op == b10101) + result = armv7_read_arm_instr_cmp_register(raw); + + else if (op == b10111) + result = armv7_read_arm_instr_cmn_register(raw); + + else if ((op & b11110) == b11000) + result = armv7_read_arm_instr_orr_register(raw); + + else if ((op & b11110) == b11010) + { + if (op2 == b00) + { + if (imm5 == b00000) + result = armv7_read_arm_instr_mov_register_arm(raw); + + else + result = armv7_read_arm_instr_lsl_immediate(raw); + + } + + else if (op2 == b01) + result = armv7_read_arm_instr_lsr_immediate(raw); + + else if (op2 == b10) + result = armv7_read_arm_instr_asr_immediate(raw); + + else if (op2 == b11) + { + if (imm5 == b00000) + result = armv7_read_arm_instr_rrx(raw); + + else + result = armv7_read_arm_instr_ror_immediate(raw); + + } + + } + + else if ((op & b11110) == b11100) + result = armv7_read_arm_instr_bic_register(raw); + + else if ((op & b11110) == b11110) + result = armv7_read_arm_instr_mvn_register(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.2. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_data_processing_register_shifted_register(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.2 Data-processing (register-shifted register) + */ + + if ((raw & 0x0e000090) != 0x00000010) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x1f; + op2 = (raw >> 5) & 0x3; + + if ((op1 & b11110) == b00000) + result = armv7_read_arm_instr_and_register_shifted_register(raw); + + else if ((op1 & b11110) == b00010) + result = armv7_read_arm_instr_eor_register_shifted_register(raw); + + else if ((op1 & b11110) == b00100) + result = armv7_read_arm_instr_sub_register_shifted_register(raw); + + else if ((op1 & b11110) == b00110) + result = armv7_read_arm_instr_rsb_register_shifted_register(raw); + + else if ((op1 & b11110) == b01000) + result = armv7_read_arm_instr_add_register_shifted_register(raw); + + else if ((op1 & b11110) == b01010) + result = armv7_read_arm_instr_adc_register_shifted_register(raw); + + else if ((op1 & b11110) == b01100) + result = armv7_read_arm_instr_sbc_register_shifted_register(raw); + + else if ((op1 & b11110) == b01110) + result = armv7_read_arm_instr_rsc_register_shifted_register(raw); + +#if 0 + else if ((op1 & b11001) == b10000) + /* See Data-processing and miscellaneous instructions on page A5-196 */ +#endif + + else if (op1 == b10001) + result = armv7_read_arm_instr_tst_register_shifted_register(raw); + + else if (op1 == b10011) + result = armv7_read_arm_instr_teq_register_shifted_register(raw); + + else if (op1 == b10101) + result = armv7_read_arm_instr_cmp_register_shifted_register(raw); + + else if (op1 == b10111) + result = armv7_read_arm_instr_cmn_register_shifted_register(raw); + + else if ((op1 & b11110) == b11000) + result = armv7_read_arm_instr_orr_register_shifted_register(raw); + + else if ((op1 & b11110) == b11010) + { + if (op2 == b00) + result = armv7_read_arm_instr_lsl_register(raw); + + else if (op2 == b01) + result = armv7_read_arm_instr_lsr_register(raw); + + else if (op2 == b10) + result = armv7_read_arm_instr_asr_register(raw); + + else if (op2 == b11) + result = armv7_read_arm_instr_ror_register(raw); + + } + + else if ((op1 & b11110) == b11100) + result = armv7_read_arm_instr_bic_register_shifted_register(raw); + + else if ((op1 & b11110) == b11110) + result = armv7_read_arm_instr_mvn_register_shifted_register(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.3. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.3 Data-processing (immediate) + */ + + if ((raw & 0x0e000000) != 0x02000000) return NULL; + + result = NULL; + + op = (raw >> 20) & 0x1f; + rn = (raw >> 16) & 0xf; + + if ((op & b11110) == b00000) + result = armv7_read_arm_instr_and_immediate(raw); + + else if ((op & b11110) == b00010) + result = armv7_read_arm_instr_eor_immediate(raw); + + else if ((op & b11110) == b00100) + { + if (rn == b1111) + result = armv7_read_arm_instr_adr(raw); + + else + result = armv7_read_arm_instr_sub_immediate_arm(raw); + + } + + else if ((op & b11110) == b00110) + result = armv7_read_arm_instr_rsb_immediate(raw); + + else if ((op & b11110) == b01000) + { + if (rn == b1111) + result = armv7_read_arm_instr_adr(raw); + + else + result = armv7_read_arm_instr_add_immediate_arm(raw); + + } + + else if ((op & b11110) == b01010) + result = armv7_read_arm_instr_adc_immediate(raw); + + else if ((op & b11110) == b01100) + result = armv7_read_arm_instr_sbc_immediate(raw); + + else if ((op & b11110) == b01110) + result = armv7_read_arm_instr_rsc_immediate(raw); + + /* + else if ((op & b11110) == b10000) + result = process_armv7_arm_data_processing_and_miscellaneous_instructions(raw); + */ + + else if (op == b10001) + result = armv7_read_arm_instr_tst_immediate(raw); + + else if (op == b10011) + result = armv7_read_arm_instr_teq_immediate(raw); + + else if (op == b10101) + result = armv7_read_arm_instr_cmp_immediate(raw); + + else if (op == b10111) + result = armv7_read_arm_instr_cmn_immediate(raw); + + else if ((op & b11110) == b11000) + result = armv7_read_arm_instr_orr_immediate(raw); + + else if ((op & b11110) == b11010) + result = armv7_read_arm_instr_mov_immediate(raw); + + else if ((op & b11110) == b11100) + result = armv7_read_arm_instr_bic_immediate(raw); + + else if ((op & b11110) == b11110) + result = armv7_read_arm_instr_mvn_immediate(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.5. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.5 Multiply and multiply accumulate + */ + + if ((raw & 0x0f0000f0) != 0x00000090) return NULL; + + result = NULL; + + op = (raw >> 20) & 0xf; + + if ((op & b1110) == b0000) + result = armv7_read_arm_instr_mul(raw); + + else if ((op & b1110) == b0010) + result = armv7_read_arm_instr_mla(raw); + + else if (op == b0100) + result = armv7_read_arm_instr_umaal(raw); + + else if (op == b0101) + result = NULL; /* Non défini */ + + else if (op == b0110) + result = armv7_read_arm_instr_mls(raw); + + else if (op == b0111) + result = NULL; /* Non défini */ + + else if ((op & b1110) == b1000) + result = armv7_read_arm_instr_umull(raw); + + else if ((op & b1110) == b1010) + result = armv7_read_arm_instr_umlal(raw); + + else if ((op & b1110) == b1100) + result = armv7_read_arm_instr_smull(raw); + + else if ((op & b1110) == b1110) + result = armv7_read_arm_instr_smlal(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.6. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.6 Saturating addition and subtraction + */ + + if ((raw & 0x0f9000f0) != 0x01000050) return NULL; + + result = NULL; + + op = (raw >> 21) & 0x3; + + if (op == b00) + result = armv7_read_arm_instr_qadd(raw); + + else if (op == b01) + result = armv7_read_arm_instr_qsub(raw); + + else if (op == b10) + result = armv7_read_arm_instr_qdadd(raw); + + else if (op == b11) + result = armv7_read_arm_instr_qdsub(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.7. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumulate(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.7 Halfword multiply and multiply accumulate + */ + + if ((raw & 0x0f900090) != 0x01000080) return NULL; + + result = NULL; + + op1 = (raw >> 21) & 0x3; + op = (raw >> 5) & 0x1; + + if (op1 == b00) + result = armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(raw); + + else if (op1 == b01) + { + if (op == b0) + result = armv7_read_arm_instr_smlawb_smlawt(raw); + + else/* if (op == b1)*/ + result = armv7_read_arm_instr_smulwb_smulwt(raw); + + } + + else if (op1 == b10) + result = armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(raw); + + else if (op1 == b11) + result = armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.8. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.8 Extra load/store instructions + */ + + if ((raw & 0x0e000090) != 0x00000090) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x1f; + rn = (raw >> 16) & 0xf; + op2 = (raw >> 5) & 0x3; + + if (op2 == b01) + { + if ((op1 & b00101) == b00000) + result = armv7_read_arm_instr_strh_register(raw); + + else if ((op1 & b00101) == b00001) + result = armv7_read_arm_instr_ldrh_register(raw); + + else if ((op1 & b00101) == b00100) + result = armv7_read_arm_instr_strh_immediate_arm(raw); + + else/* if ((op1 & b00101) == b00101)*/ + { + if (rn == b1111) + result = armv7_read_arm_instr_ldrh_literal(raw); + + else + result = armv7_read_arm_instr_ldrh_immediate_arm(raw); + + } + + } + + else if (op2 == b10) + { + if ((op1 & b00101) == b00000) + result = armv7_read_arm_instr_ldrd_register(raw); + + else if ((op1 & b00101) == b00001) + result = armv7_read_arm_instr_ldrsb_register(raw); + + else if ((op1 & b00101) == b00100) + { + if (rn == b1111) + result = armv7_read_arm_instr_ldrd_literal(raw); + + else + result = armv7_read_arm_instr_ldrd_immediate(raw); + + } + + else/* if ((op1 & b00101) == b00101)*/ + { + if (rn == b1111) + result = armv7_read_arm_instr_ldrsb_literal(raw); + + else + result = armv7_read_arm_instr_ldrsb_immediate(raw); + + } + + } + + else if (op2 == b11) + { + if ((op1 & b00101) == b00000) + result = armv7_read_arm_instr_strd_register(raw); + + else if ((op1 & b00101) == b00001) + result = armv7_read_arm_instr_ldrsh_register(raw); + + else if ((op1 & b00101) == b00100) + result = armv7_read_arm_instr_strd_immediate(raw); + + else/* if ((op1 & b00101) == b00101)*/ + { + if (rn == b1111) + result = armv7_read_arm_instr_ldrsh_literal(raw); + + else + result = armv7_read_arm_instr_ldrsh_immediate(raw); + + } + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.9. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivileged(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.9 Extra load/store instructions, unprivileged + */ + + if ((raw & 0x0f200090) != 0x00200090) return NULL; + + result = NULL; + + op = (raw >> 20) & 0x1; + op2 = (raw >> 5) & 0x3; + + if (op2 == b01) + { + if (op == b0) + result = armv7_read_arm_instr_strht(raw); + + else/* if (op == b1)*/ + result = armv7_read_arm_instr_ldrht(raw); + + } + + else if (op2 == b10) + { + if (op == b1) + result = armv7_read_arm_instr_ldrsbt(raw); + + } + + else if (op2 == b11) + { + if (op == b1) + result = armv7_read_arm_instr_ldrsht(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.10. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.10 Synchronization primitives + */ + + if ((raw & 0x0f0000f0) != 0x01000090) return NULL; + + result = NULL; + + op = (raw >> 20) & 0xf; + + if ((op & b1011) == b0000) + result = armv7_read_arm_instr_swp_swpb(raw); + + else if (op == b1000) + result = armv7_read_arm_instr_strex(raw); + + else if (op == b1001) + result = armv7_read_arm_instr_ldrex(raw); + + else if (op == b1010) + result = armv7_read_arm_instr_strexd(raw); + + else if (op == b1011) + result = armv7_read_arm_instr_ldrexd(raw); + + else if (op == b1100) + result = armv7_read_arm_instr_strexb(raw); + + else if (op == b1101) + result = armv7_read_arm_instr_ldrexb(raw); + + else if (op == b1110) + result = armv7_read_arm_instr_strexh(raw); + + else if (op == b1111) + result = armv7_read_arm_instr_ldrexh(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.11. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.11 MSR (immediate), and hints + */ + + if ((raw & 0x0fb00000) != 0x03200000) return NULL; + + result = NULL; + + op = (raw >> 22) & 0x1; + op1 = (raw >> 16) & 0xf; + op2 = (raw >> 0) & 0x1; + + if (op == b0) + { + if (op1 == b0000) + { + if (op2 == b00000000) + result = armv7_read_arm_instr_nop(raw); + + else if (op2 == b00000001) + result = armv7_read_arm_instr_yield(raw); + + else if (op2 == b00000010) + result = armv7_read_arm_instr_wfe(raw); + + else if (op2 == b00000011) + result = armv7_read_arm_instr_wfi(raw); + + else if (op2 == b00000100) + result = armv7_read_arm_instr_sev(raw); + + else if ((op2 & b11110000) == b11110000) + result = armv7_read_arm_instr_dbg(raw); + + } + + else if (op1 == b0100 || (op1 & b1011) == b1000) + result = armv7_read_arm_instr_msr_immediate_a8(raw); + + else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010) + result = armv7_read_arm_instr_msr_immediate_b9(raw); + + } + + else/* if (op == b1)*/ + result = armv7_read_arm_instr_msr_immediate_b9(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.2.12. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.2.12 Miscellaneous instructions + */ + + if ((raw & 0x0f900080) != 0x01000000) return NULL; + + result = NULL; + + op = (raw >> 21) & 0x3; + op1 = (raw >> 16) & 0xf; + b = (raw >> 9) & 0x1; + op2 = (raw >> 4) & 0x7; + + if (op2 == b000) + { + if (b == b1) + { + if ((op & b01) == b00) + result = armv7_read_arm_instr_mrs_banked_register(raw); + + else/* if ((op & b01) == b01)*/ + result = armv7_read_arm_instr_msr_banked_register(raw); + + } + else/* if (b == b0)*/ + { + if ((op & b01) == b00) + result = armv7_read_arm_instr_mrs(raw); + + else if (op == b01) + { + if ((op1 & b0011) == b0000) + result = armv7_read_arm_instr_msr_register_a8(raw); + + else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010) + result = armv7_read_arm_instr_msr_register_b9(raw); + + } + + else if (op == b11) + result = armv7_read_arm_instr_msr_register_b9(raw); + + } + + } + + else if (op2 == b001) + { + if (op == b01) + result = armv7_read_arm_instr_bx(raw); + + else if (op == b11) + result = armv7_read_arm_instr_clz(raw); + + } + + else if (op2 == b010) + { + if (op == b01) + result = armv7_read_arm_instr_bxj(raw); + + } + + else if (op2 == b011) + { + if (op == b01) + result = armv7_read_arm_instr_blx_register(raw); + + } + + else if (op2 == b101) + result = process_armv7_arm_saturating_addition_and_subtraction(raw); + + else if (op2 == b110) + { + if (op == b11) + result = armv7_read_arm_instr_eret(raw); + + } + + else if (op2 == b111) + { + if (op == b) + result = armv7_read_arm_instr_bkpt(raw); + + else if (op == b) + result = armv7_read_arm_instr_hvc(raw); + + else if (op == b) + result = armv7_read_arm_instr_smc_previously_smi(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.3. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t b; /* Champ 'b' à retrouver */ + + /** + * Suit les directives de : + * § A5.3 Load/store word and unsigned byte + */ + + if ((raw & 0x0c000000) != 0x04000000) return NULL; + + result = NULL; + + a = (raw >> 25) & 0x1; + op1 = (raw >> 20) & 0x1f; + rn = (raw >> 16) & 0xf; + b = (raw >> 4) & 0x1; + + if (a == b0) + { + if ((op1 & b00101) == b00000 && (op1 & b10111) != b00010) + result = armv7_read_arm_instr_str_immediate_arm(raw); + + else if ((op1 & b10111) == b00010) + result = armv7_read_arm_instr_strt(raw); + + else if ((op1 & b00101) == b00001 && (op1 & b10111) != b00011) + { + if (rn != b1111) + result = armv7_read_arm_instr_ldr_immediate_arm(raw); + else + result = armv7_read_arm_instr_ldr_literal(raw); + } + + else if ((op1 & b10111) == b00011) + result = armv7_read_arm_instr_ldrt(raw); + + else if ((op1 & b00101) == b00100 && (op1 & b10110) != b00110) + result = armv7_read_arm_instr_strb_immediate_arm(raw); + + else if ((op1 & b10110) == b00110) + result = armv7_read_arm_instr_strbt(raw); + + else if ((op1 & b00101) == b00101 && (op1 & b10111) != b00111) + { + if (rn != b1111) + result = armv7_read_arm_instr_ldrb_immediate_arm(raw); + else + result = armv7_read_arm_instr_ldrb_literal(raw); + } + + else if ((op1 & b10111) == b00111) + result = armv7_read_arm_instr_ldrbt(raw); + + } + else /*if (a == b1)*/ + { + if ((op1 & b00101) == b00000 && (op1 & b10111) != b00010 && b == b0) + result = armv7_read_arm_instr_str_register(raw); + + else if ((op1 & b10111) == b00010 && b == b0) + result = armv7_read_arm_instr_strt(raw); + + else if ((op1 & b00101) == b00001 && (op1 & b10111) != b00011 && b == b0) + result = armv7_read_arm_instr_ldr_register_arm(raw); + + else if ((op1 & b10111) == b00011 && b == b0) + result = armv7_read_arm_instr_ldrt(raw); + + else if ((op1 & b00101) == b00100 && (op1 & b10110) != b00110 && b == b0) + result = armv7_read_arm_instr_strb_register(raw); + + else if ((op1 & b10110) == b00110 && b == b0) + result = armv7_read_arm_instr_strbt(raw); + + else if ((op1 & b00101) == b00101 && (op1 & b10111) != b00111 && b == b0) + result = armv7_read_arm_instr_ldrb_register(raw); + + else if ((op1 & b10111) == b00111 && b == b0) + result = armv7_read_arm_instr_ldrbt(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t cond; /* Champ 'cond' à retrouver */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rd; /* Champ 'rd' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + + /** + * Suit les directives de : + * § A5.4 Media instructions + */ + + if ((raw & 0x0e000010) != 0x06000010) return NULL; + + result = NULL; + + cond = (raw >> 28) & 0xf; + op1 = (raw >> 20) & 0x1f; + rd = (raw >> 12) & 0xf; + op2 = (raw >> 5) & 0x7; + rn = (raw >> 0) & 0xf; + + if ((op1 & b11100) == b00000) + result = process_armv7_arm_parallel_addition_and_subtraction_signed(raw); + + else if ((op1 & b11100) == b00100) + result = process_armv7_arm_parallel_addition_and_subtraction_unsigned(raw); + + else if ((op1 & b11000) == b01000) + result = process_armv7_arm_packing_unpacking_saturation_and_reversal(raw); + + else if ((op1 & b11000) == b10000) + result = process_armv7_arm_signed_multiply_signed_and_unsigned_divide(raw); + + else if (op1 == b11000) + { + if (op2 == b000) + { + if (rd == b1111) + result = armv7_read_arm_instr_usad8(raw); + else + result = armv7_read_arm_instr_usada8(raw); + } + + goto a54_done; + + } + + else if ((op1 & b11110) == b11010) + { + if ((op2 & b011) == b010) + result = armv7_read_arm_instr_sbfx(raw); + + goto a54_done; + + } + + else if ((op1 & b11110) == b11100) + { + if ((op2 & b011) == b000) + { + if (rn == b1111) + result = armv7_read_arm_instr_bfc(raw); + else + result = armv7_read_arm_instr_bfi(raw); + } + + goto a54_done; + + } + + else if ((op1 & b11110) == b11110) + { + if ((op2 & b011) == b010) + result = armv7_read_arm_instr_ubfx(raw); + + goto a54_done; + + } + + else if (op1 == b11111 && op2 == b111 && cond == b1110) + result = armv7_read_arm_instr_ubfx(raw); + + a54_done: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.1. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_signed(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.4.1 Parallel addition and subtraction, signed + */ + + if ((raw & 0x0fc00010) != 0x06000010) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x3; + op2 = (raw >> 5) & 0x7; + + if (op1 == b01) + { + if (op2 == b000) + result = armv7_read_arm_instr_sadd16(raw); + + else if (op2 == b001) + result = armv7_read_arm_instr_sasx(raw); + + else if (op2 == b010) + result = armv7_read_arm_instr_ssax(raw); + + else if (op2 == b011) + result = armv7_read_arm_instr_ssub16(raw); + + else if (op2 == b100) + result = armv7_read_arm_instr_sadd8(raw); + + else if (op2 == b111) + result = armv7_read_arm_instr_ssub8(raw); + + } + + else if (op1 == b10) + { + if (op2 == b000) + result = armv7_read_arm_instr_qadd16(raw); + + else if (op2 == b001) + result = armv7_read_arm_instr_qasx(raw); + + else if (op2 == b010) + result = armv7_read_arm_instr_qsax(raw); + + else if (op2 == b011) + result = armv7_read_arm_instr_qsub16(raw); + + else if (op2 == b100) + result = armv7_read_arm_instr_qadd8(raw); + + else if (op2 == b111) + result = armv7_read_arm_instr_qsub8(raw); + + } + + else if (op1 == b11) + { + if (op2 == b000) + result = armv7_read_arm_instr_shadd16(raw); + + else if (op2 == b001) + result = armv7_read_arm_instr_shasx(raw); + + else if (op2 == b010) + result = armv7_read_arm_instr_shsax(raw); + + else if (op2 == b011) + result = armv7_read_arm_instr_shsub16(raw); + + else if (op2 == b100) + result = armv7_read_arm_instr_shadd8(raw); + + else if (op2 == b111) + result = armv7_read_arm_instr_shsub8(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.2. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_unsigned(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.4.2 Parallel addition and subtraction, unsigned + */ + + if ((raw & 0x0fc00010) != 0x06400010) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x3; + op2 = (raw >> 5) & 0x7; + + if (op1 == b01) + { + if (op2 == b000) + result = armv7_read_arm_instr_uadd16(raw); + + else if (op2 == b001) + result = armv7_read_arm_instr_uasx(raw); + + else if (op2 == b010) + result = armv7_read_arm_instr_usax(raw); + + else if (op2 == b011) + result = armv7_read_arm_instr_usub16(raw); + + else if (op2 == b100) + result = armv7_read_arm_instr_uadd8(raw); + + else if (op2 == b111) + result = armv7_read_arm_instr_usub8(raw); + + } + + else if (op1 == b10) + { + if (op2 == b000) + result = armv7_read_arm_instr_uqadd16(raw); + + else if (op2 == b001) + result = armv7_read_arm_instr_uqasx(raw); + + else if (op2 == b010) + result = armv7_read_arm_instr_uqsax(raw); + + else if (op2 == b011) + result = armv7_read_arm_instr_uqsub16(raw); + + else if (op2 == b100) + result = armv7_read_arm_instr_uqadd8(raw); + + else if (op2 == b111) + result = armv7_read_arm_instr_uqsub8(raw); + + } + + else if (op1 == b11) + { + if (op2 == b000) + result = armv7_read_arm_instr_uhadd16(raw); + + else if (op2 == b001) + result = armv7_read_arm_instr_uhasx(raw); + + else if (op2 == b010) + result = armv7_read_arm_instr_uhsax(raw); + + else if (op2 == b011) + result = armv7_read_arm_instr_uhsub16(raw); + + else if (op2 == b100) + result = armv7_read_arm_instr_uhadd8(raw); + + else if (op2 == b111) + result = armv7_read_arm_instr_uhsub8(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.3. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.4.3 Packing, unpacking, saturation, and reversal + */ + + if ((raw & 0x0f800010) != 0x06800010) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x7; + a = (raw >> 16) & 0xf; + op2 = (raw >> 5) & 0x7; + + if ((op1 & b111) == b000) + { + if ((op2 & b001) == b000) + { + result = armv7_read_arm_instr_pkh(raw); + goto a543_done; + } + else if (op2 == b011) + { + if (a == b1111) + { + result = armv7_read_arm_instr_sxtb16(raw); + goto a543_done; + } + else + { + result = armv7_read_arm_instr_sxtab16(raw); + goto a543_done; + } + } + else if (op2 == b101) + { + result = armv7_read_arm_instr_sel(raw); + goto a543_done; + } + } + + else if ((op1 & b110) == b010 && (op2 & b001) == b000) + { + result = armv7_read_arm_instr_ssat(raw); + goto a543_done; + } + + else if (op1 == b010) + { + if (op2 == b001) + { + result = armv7_read_arm_instr_ssat16(raw); + goto a543_done; + } + else if (op2 == b011) + { + if (a == b1111) + { + result = armv7_read_arm_instr_sxtb(raw); + goto a543_done; + } + else + { + result = armv7_read_arm_instr_sxtab(raw); + goto a543_done; + } + } + } + + else if (op1 == b011) + { + if (op2 == b001) + { + result = armv7_read_arm_instr_rev(raw); + goto a543_done; + } + else if (op2 == b011) + { + if (a == b1111) + { + result = armv7_read_arm_instr_sxth(raw); + goto a543_done; + } + else + { + result = armv7_read_arm_instr_sxtah(raw); + goto a543_done; + } + } + else if (op2 == b101) + { + result = armv7_read_arm_instr_rev16(raw); + goto a543_done; + } + } + + else if (op1 == b100 && op2 == b011) + { + if (a == b1111) + { + result = armv7_read_arm_instr_uxtb16(raw); + goto a543_done; + } + else + { + result = armv7_read_arm_instr_uxtab16(raw); + goto a543_done; + } + } + + else if ((op1 & b110) == b110 && (op2 & b001) == b000) + { + result = armv7_read_arm_instr_usat(raw); + goto a543_done; + } + + else if (op1 == b110) + { + if (op2 == b001) + { + result = armv7_read_arm_instr_usat16(raw); + goto a543_done; + } + else if (op2 == b011) + { + if (a == b1111) + { + result = armv7_read_arm_instr_uxtb(raw); + goto a543_done; + } + else + { + result = armv7_read_arm_instr_uxtab(raw); + goto a543_done; + } + } + } + + else if (op1 == b111) + { + if (op2 == b001) + { + result = armv7_read_arm_instr_rbit(raw); + goto a543_done; + } + else if (op2 == b011) + { + if (a == b1111) + { + result = armv7_read_arm_instr_uxth(raw); + goto a543_done; + } + else + { + result = armv7_read_arm_instr_uxtah(raw); + goto a543_done; + } + } + else if (op2 == b101) + { + result = armv7_read_arm_instr_revsh(raw); + goto a543_done; + } + } + + a543_done: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.4.4. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_divide(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t a; /* Champ 'a' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.4.4 Signed multiply, signed and unsigned divide + */ + + if ((raw & 0x0f800010) != 0x07000010) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x7; + a = (raw >> 12) & 0xf; + op2 = (raw >> 5) & 0x7; + + if (op1 == b000) + { + if ((op2 & b110) == b000) + { + if (a != b1111) + result = armv7_read_arm_instr_smlad(raw); + else/* if (a == b1111)*/ + result = armv7_read_arm_instr_smuad(raw); + + } + + else if ((op2 & b110) == b010) + { + if (a != b1111) + result = armv7_read_arm_instr_smlsd(raw); + else/* if (a == b1111)*/ + result = armv7_read_arm_instr_smusd(raw); + + } + + } + + else if (op1 == b001) + { + if (op2 == b000) + result = armv7_read_arm_instr_sdiv(raw); + + } + + else if (op1 == b011) + { + if (op2 == b000) + result = armv7_read_arm_instr_udiv(raw); + + } + + else if (op1 == b100) + { + if ((op2 & b110) == b000) + result = armv7_read_arm_instr_smlald(raw); + + else if ((op2 & b110) == b010) + result = armv7_read_arm_instr_smlsld(raw); + + } + + else if (op1 == b101) + { + if ((op2 & b110) == b000) + { + if (a != b1111) + result = armv7_read_arm_instr_smmla(raw); + else/* if (a == b1111)*/ + result = armv7_read_arm_instr_smmul(raw); + + } + + else if ((op2 & b110) == b110) + result = armv7_read_arm_instr_smmls(raw); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.5. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_data_transfer(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op; /* Champ 'op' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t r; /* Champ 'r' à retrouver */ + + /** + * Suit les directives de : + * § A5.5 Branch, branch with link, and block data transferr + */ + + if ((raw & 0x0c000000) != 0x08000000) return NULL; + + result = NULL; + + op = (raw >> 20) & 0x3f; + rn = (raw >> 16) & 0xf; + r = (raw >> 15) & 0x1; + + if ((op & b111101) == b000000) + result = armv7_read_arm_instr_stmda_stmed(raw); + + else if ((op & b111101) == b000001) + result = armv7_read_arm_instr_ldmda_ldmfa(raw); + + else if ((op & b111101) == b001000) + result = armv7_read_arm_instr_stm_stmia_stmea(raw); + + else if (op == b001001) + result = armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(raw); + + else if (op == b001011) + { + if (rn != b1101) + result = armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(raw); + else /* if (rn == b1101) */ + result = armv7_read_arm_instr_pop_arm(raw); + } + + else if (op == b010000) + result = armv7_read_arm_instr_stmdb_stmfd(raw); + + else if (op == b010010) + { + if (rn != b1101) + result = armv7_read_arm_instr_stmdb_stmfd(raw); + else /* if (rn == b1101) */ + result = armv7_read_arm_instr_push(raw); + } + + else if ((op & b111101) == b010001) + result = armv7_read_arm_instr_ldmdb_ldmea(raw); + + else if ((op & b111101) == b011000) + result = armv7_read_arm_instr_stmib_stmfa(raw); + + else if ((op & b111101) == b011001) + result = armv7_read_arm_instr_ldmib_ldmed(raw); + + else if ((op & b100101) == b000100) + result = armv7_read_arm_instr_stm_user_registers(raw); + + else if ((op & b100101) == b000101) + { + if (r == b0) + result = armv7_read_arm_instr_ldm_user_registers(raw); + else /* if (r == b1) */ + result = armv7_read_arm_instr_ldm_exception_return(raw); + } + + else if ((op & b110000) == b100000) + result = armv7_read_arm_instr_b(raw); + + else if ((op & b110000) == b110000) + result = armv7_read_arm_instr_bl_blx_immediate(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.6. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervisor_call(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t coproc; /* Champ 'coproc' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.6 Coprocessor instructions, and Supervisor Call + */ + + if ((raw & 0x0c000000) != 0x0c000000) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x3f; + rn = (raw >> 16) & 0xf; + coproc = (raw >> 8) & 0xf; + op = (raw >> 4) & 0x1; + + if ((op1 & b111110) == b000000) + result = g_undef_instruction_new(IBS_UNDEFINED); + + else if ((op1 & b110000) == b110000) + result = armv7_read_arm_instr_svc_previously_swi(raw); + + else if ((coproc & b1110) != b1010) + { + if ((op1 & b100001) == b000000 && (op1 & b111011) != b000000) + result = armv7_read_arm_instr_stc_stc2(raw); + + else if ((op1 & b100001) == b000001 && (op1 & b111011) != b000001) + { + if (rn != b1111) + result = armv7_read_arm_instr_ldc_ldc2_immediate(raw); + else + result = armv7_read_arm_instr_ldc_ldc2_literal(raw); + + } + + else if (op1 == b000100) + result = armv7_read_arm_instr_mcrr_mcrr2(raw); + + else if (op1 == b000101) + result = armv7_read_arm_instr_mrrc_mrrc2(raw); + + + else if ((op1 & b110000) == b100000 && op == b0) + result = armv7_read_arm_instr_cdp_cdp2(raw); + + else if ((op1 & b110001) == b100000 && op == b1) + result = armv7_read_arm_instr_mcr_mcr2(raw); + + else if ((op1 & b110001) == b100001 && op == b1) + result = armv7_read_arm_instr_mrc_mrc2(raw); + + } + + else if ((coproc & b1110) == b1010) + { + /* TODO */ + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.7. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A5.7 Unconditional instructions + */ + + if ((raw & 0xf0000000) != 0xf0000000) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0xff; + rn = (raw >> 16) & 0xf; + op = (raw >> 4) & 0x1; + + if ((op1 & b10000000) == b00000000) + result = process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(raw); + + else if ((op1 & b11100101) == b10000100) + result = armv7_read_arm_instr_srs_arm(raw); + + else if ((op1 & b11100101) == b10000001) + result = armv7_read_arm_instr_rfe(raw); + + else if ((op1 & b11100000) == b10100000) + result = armv7_read_arm_instr_bl_blx_immediate(raw); + + else if ((op1 & b11100001) == b11000000 && (op1 & b11111011) != b11000000) + result = armv7_read_arm_instr_stc_stc2(raw); + + else if ((op1 & b11100001) == b11000001 && (op1 & b11111011) != b11000001) + { + if (rn != b1111) + result = armv7_read_arm_instr_ldc_ldc2_immediate(raw); + else/* if (rn == b1111)*/ + result = armv7_read_arm_instr_ldc_ldc2_literal(raw); + } + + else if (op1 == b11000100) + result = armv7_read_arm_instr_mcrr_mcrr2(raw); + + else if (op1 == b11000101) + result = armv7_read_arm_instr_mrrc_mrrc2(raw); + + else if ((op1 & b11110000) == b11100000 && op == b0) + result = armv7_read_arm_instr_cdp_cdp2(raw); + + else if ((op1 & b11110001) == b11100000 && op == b1) + result = armv7_read_arm_instr_mcr_mcr2(raw); + + else if ((op1 & b11110001) == b11100001 && op == b1) + result = armv7_read_arm_instr_mrc_mrc2(raw); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A5.7.1. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à retourner */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A5.7.1 Memory hints, Advanced SIMD instructions, and miscellaneous instructions + */ + + if ((raw & 0xf8000000) != 0xf0000000) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x7f; + rn = (raw >> 16) & 0xf; + op2 = (raw >> 4) & 0xf; + + if (op1 == b0010000) + { + if ((op2 & b0010) == b0000 && (rn & b0001) == b0000) + result = armv7_read_arm_instr_cps_arm(raw); + + else if (op2 == b0000 && (rn & b0001) == b0001) + result = armv7_read_arm_instr_cps_arm(raw); + + } + + else if ((op1 & b1100000) == b0100000) + result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, true); + + else if ((op1 & b1110001) == b1000000) + result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, true); + + else if ((op1 & b1110111) == b1000001) + result = g_undef_instruction_new(IBS_NOP); + + else if ((op1 & b1110111) == b1000101) + result = armv7_read_arm_instr_pli_immediate_literal(raw); + + else if ((op1 & b1110011) == b1000011) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + else if ((op1 & b1110111) == b1010101) + { + if (rn != b1111) + result = armv7_read_arm_instr_pld_pldw_immediate(raw); + else + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + } + + else if ((op1 & b1110111) == b1010101) + { + if (rn != b1111) + result = armv7_read_arm_instr_pld_pldw_immediate(raw); + else + result = armv7_read_arm_instr_pld_literal(raw); + + } + + else if (op1 == b1010011) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + else if (op1 == b1010111) + { + if (op2 == b0000) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + else if (op2 == b0001) + result = armv7_read_arm_instr_clrex(raw); + + else if ((op2 & b1110) == b0010) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + else if (op2 == b0100) + result = armv7_read_arm_instr_dsb(raw); + + else if (op2 == b0101) + result = armv7_read_arm_instr_dmb(raw); + + else if (op2 == b0110) + result = armv7_read_arm_instr_isb(raw); + + else if (op2 == b0111) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + else if ((op2 & b1000) == b1000) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + } + + else if ((op1 & b1111011) == b1011011) + result = g_undef_instruction_new(IBS_UNPREDICTABLE); + + else if ((op1 & b1110111) == b1100001 && (op2 & b0001) == b0000) + result = g_undef_instruction_new(IBS_NOP); + + else if ((op1 & b1110111) == b1100101 && (op2 & b0001) == b0000) + result = armv7_read_arm_instr_pli_register(raw); + + else if ((op1 & b1110111) == b1110001 && (op2 & b0001) == b0000) + result = armv7_read_arm_instr_pld_pldw_register(raw); + + return result; + +} |