summaryrefslogtreecommitdiff
path: root/src/arch/arm/v7/opdefs/str_A88203.d
diff options
context:
space:
mode:
Diffstat (limited to 'src/arch/arm/v7/opdefs/str_A88203.d')
-rw-r--r--src/arch/arm/v7/opdefs/str_A88203.d135
1 files changed, 135 insertions, 0 deletions
diff --git a/src/arch/arm/v7/opdefs/str_A88203.d b/src/arch/arm/v7/opdefs/str_A88203.d
new file mode 100644
index 0000000..2952e1a
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/str_A88203.d
@@ -0,0 +1,135 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Foobar. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title STR (immediate, Thumb)
+
+@encoding(t1) {
+
+ @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3)
+
+ @syntax <Rgt> <access>
+
+ @conv {
+
+ Rgt = Register(Rt)
+ Rgn = Register(Rn)
+ imm32 = ZeroExtend(imm5:'00', 7, 32);
+ access = MakeMemoryAccess(Rgn, imm32, 1, 0)
+
+ }
+
+}
+
+@encoding(t2) {
+
+ @half 1 0 0 1 0 Rt(3) imm8(8)
+
+ @syntax <Rgt> <access>
+
+ @conv {
+
+ Rgt = Register(Rt)
+ Sp = Register(13)
+ imm32 = ZeroExtend(imm8:'00', 10, 32);
+ access = MakeMemoryAccess(Sp, imm32, 1, 0)
+
+ }
+
+}
+
+@encoding(T3) {
+
+ @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12)
+
+ @syntax "str.W" <Rgt> <access>
+
+ @conv {
+
+ Rgt = Register(Rt)
+ Rgn = Register(Rn)
+ imm32 = ZeroExtend(imm12, 12, 32);
+ access = MakeMemoryAccess(Rgn, imm32, 1, 0)
+
+ }
+
+ @rules {
+
+ //if Rn == '1111' then UNDEFINED;
+ //if t == 15 then UNPREDICTABLE;
+
+ }
+
+}
+
+@encoding(T41) {
+
+ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 U(1) W(1) imm8(8)
+
+ @syntax <Rgt> <access>
+
+ @conv {
+
+ Rgt = Register(Rt)
+ Rgn = Register(Rn)
+ imm32 = ZeroExtend(imm8, 8, 32);
+ access = MakeMemoryAccess(Rgn, imm32, U, W)
+
+ }
+
+ @rules {
+
+ //if P == '1' && U == '1' && W == '0' then SEE STRT;
+ //if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH;
+ //if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
+ //if t == 15 || (wback && n == t) then UNPREDICTABLE;
+
+ }
+
+}
+
+@encoding(T42) {
+
+ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 0 U(1) W(1) imm8(8)
+
+ @syntax <Rgt> <base> <offset>
+
+ @conv {
+
+ Rgt = Register(Rt)
+ Rgn = Register(Rn)
+ imm32 = ZeroExtend(imm8, 8, 32);
+ base = MakeMemoryNotIndexed(Rgn, W)
+ offset = MakeAccessOffset(U, imm32)
+
+ }
+
+ @rules {
+
+ //if P == '1' && U == '1' && W == '0' then SEE STRT;
+ //if Rn == '1101' && P == '1' && U == '0' && W == '1' && imm8 == '00000100' then SEE PUSH;
+ //if Rn == '1111' || (P == '0' && W == '0') then UNDEFINED;
+ //if t == 15 || (wback && n == t) then UNPREDICTABLE;
+
+ }
+
+}