From 7577eadd4e871d467f747c4927a1b1984d6a7606 Mon Sep 17 00:00:00 2001 From: Cyrille Bagard Date: Sun, 22 May 2016 17:43:43 +0200 Subject: Extended the compiler to transform all the new ARMv7 encoding definitions. --- ChangeLog | 290 ++++++++++++++++++++++ src/arch/arm/v7/Makefile.am | 1 + src/arch/arm/v7/cregister.c | 212 ++++++++++++++++ src/arch/arm/v7/cregister.h | 56 +++++ src/arch/arm/v7/fetch.c | 12 +- src/arch/arm/v7/helpers.h | 236 +++++++++++++++--- src/arch/arm/v7/opcodes/opcodes_tmp_arm.h | 122 --------- src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h | 18 -- src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h | 102 -------- src/arch/arm/v7/opdefs/Makefile.am | 154 +++++++++++- src/arch/arm/v7/opdefs/adc_A881.d | 55 +++-- src/arch/arm/v7/opdefs/adc_A882.d | 74 +++--- src/arch/arm/v7/opdefs/adc_A883.d | 52 ++++ src/arch/arm/v7/opdefs/add_A8810.d | 83 +++++++ src/arch/arm/v7/opdefs/add_A8811.d | 52 ++++ src/arch/arm/v7/opdefs/add_A884.d | 97 +++----- src/arch/arm/v7/opdefs/add_A885.d | 33 +-- src/arch/arm/v7/opdefs/add_A886.d | 73 +++--- src/arch/arm/v7/opdefs/add_A887.d | 34 +-- src/arch/arm/v7/opdefs/add_A888.d | 52 ++++ src/arch/arm/v7/opdefs/add_A889.d | 122 ++++----- src/arch/arm/v7/opdefs/adr_A8812.d | 98 ++++---- src/arch/arm/v7/opdefs/and_A8813.d | 56 +++-- src/arch/arm/v7/opdefs/and_A8814.d | 75 +++--- src/arch/arm/v7/opdefs/and_A8815.d | 52 ++++ src/arch/arm/v7/opdefs/asr_A8816.d | 76 +++--- src/arch/arm/v7/opdefs/asr_A8817.d | 90 +++++++ src/arch/arm/v7/opdefs/b_A8818.d | 158 ++++++------ src/arch/arm/v7/opdefs/bfc_A8819.d | 67 +++++ src/arch/arm/v7/opdefs/bfi_A8820.d | 69 ++++++ src/arch/arm/v7/opdefs/bic_A8821.d | 55 +++-- src/arch/arm/v7/opdefs/bic_A8822.d | 74 +++--- src/arch/arm/v7/opdefs/bic_A8823.d | 52 ++++ src/arch/arm/v7/opdefs/bkpt_A8824.d | 55 +++++ src/arch/arm/v7/opdefs/bl_A8825.d | 123 ++++----- src/arch/arm/v7/opdefs/blx_A8826.d | 43 ++-- src/arch/arm/v7/opdefs/bx_A8827.d | 53 ++-- src/arch/arm/v7/opdefs/bxj_A8828.d | 61 +++++ src/arch/arm/v7/opdefs/cb_A8829.d | 58 +++++ src/arch/arm/v7/opdefs/cbnz_A8829.d | 70 ------ src/arch/arm/v7/opdefs/cdp_A8830.d | 109 ++++++++ src/arch/arm/v7/opdefs/clrex_A8832.d | 39 +++ src/arch/arm/v7/opdefs/clz_A8833.d | 63 +++++ src/arch/arm/v7/opdefs/cmn_A8834.d | 42 ++-- src/arch/arm/v7/opdefs/cmn_A8835.d | 60 ++--- src/arch/arm/v7/opdefs/cmn_A8836.d | 49 ++++ src/arch/arm/v7/opdefs/cmp_A8837.d | 56 +++-- src/arch/arm/v7/opdefs/cmp_A8838.d | 81 +++--- src/arch/arm/v7/opdefs/cmp_A8839.d | 49 ++++ src/arch/arm/v7/opdefs/dbg_A8842.d | 61 +++++ src/arch/arm/v7/opdefs/dmb_A8843.d | 55 +++++ src/arch/arm/v7/opdefs/dsb_A8844.d | 55 +++++ src/arch/arm/v7/opdefs/eor_A8846.d | 56 +++-- src/arch/arm/v7/opdefs/eor_A8847.d | 75 +++--- src/arch/arm/v7/opdefs/eor_A8848.d | 52 ++++ src/arch/arm/v7/opdefs/ldr_A8862.d | 126 ++++------ src/arch/arm/v7/opdefs/ldr_A8863.d | 66 ++--- src/arch/arm/v7/opdefs/ldr_A8864.d | 89 +++---- src/arch/arm/v7/opdefs/ldr_A8865.d | 56 ++--- src/arch/arm/v7/opdefs/ldr_A8866.d | 54 ++++ src/arch/arm/v7/opdefs/ldrb_A8867.d | 109 +++----- src/arch/arm/v7/opdefs/ldrb_A8868.d | 64 ++--- src/arch/arm/v7/opdefs/ldrb_A8869.d | 63 +++++ src/arch/arm/v7/opdefs/ldrb_A8870.d | 114 +++------ src/arch/arm/v7/opdefs/ldrbt_A8871.d | 93 +++++++ src/arch/arm/v7/opdefs/ldrd_A8872.d | 75 ++++++ src/arch/arm/v7/opdefs/ldrd_A8873.d | 65 +++++ src/arch/arm/v7/opdefs/ldrd_A8874.d | 54 ++++ src/arch/arm/v7/opdefs/ldrex_A8875.d | 66 +++++ src/arch/arm/v7/opdefs/ldrexb_A8876.d | 65 +++++ src/arch/arm/v7/opdefs/ldrexd_A8877.d | 67 +++++ src/arch/arm/v7/opdefs/ldrexh_A8878.d | 65 +++++ src/arch/arm/v7/opdefs/ldrh_A8879.d | 81 ++++++ src/arch/arm/v7/opdefs/ldrh_A8880.d | 53 ++++ src/arch/arm/v7/opdefs/ldrh_A8881.d | 63 +++++ src/arch/arm/v7/opdefs/ldrh_A8882.d | 88 +++++++ src/arch/arm/v7/opdefs/ldrht_A8883.d | 92 +++++++ src/arch/arm/v7/opdefs/ldrsb_A8884.d | 90 +++++++ src/arch/arm/v7/opdefs/ldrsb_A8885.d | 63 +++++ src/arch/arm/v7/opdefs/ldrsb_A8886.d | 88 +++++++ src/arch/arm/v7/opdefs/ldrsbt_A8887.d | 92 +++++++ src/arch/arm/v7/opdefs/ldrsh_A8888.d | 90 +++++++ src/arch/arm/v7/opdefs/ldrsh_A8889.d | 63 +++++ src/arch/arm/v7/opdefs/ldrsh_A8890.d | 88 +++++++ src/arch/arm/v7/opdefs/ldrsht_A8891.d | 92 +++++++ src/arch/arm/v7/opdefs/ldrt_A8892.d | 93 +++++++ src/arch/arm/v7/opdefs/lsl_A8894.d | 81 +++--- src/arch/arm/v7/opdefs/lsl_A8895.d | 90 +++++++ src/arch/arm/v7/opdefs/lsr_A8896.d | 79 +++--- src/arch/arm/v7/opdefs/lsr_A8897.d | 90 +++++++ src/arch/arm/v7/opdefs/mcr_A8898.d | 109 ++++++++ src/arch/arm/v7/opdefs/mcrr_A8899.d | 105 ++++++++ src/arch/arm/v7/opdefs/mla_A88100.d | 56 ++--- src/arch/arm/v7/opdefs/mls_A88101.d | 52 ++-- src/arch/arm/v7/opdefs/mov_A88102.d | 107 ++++---- src/arch/arm/v7/opdefs/mov_A88103.d | 68 +++-- src/arch/arm/v7/opdefs/mov_A88104.d | 29 ++- src/arch/arm/v7/opdefs/movt_A88106.d | 44 ++-- src/arch/arm/v7/opdefs/mrc_A88107.d | 109 ++++++++ src/arch/arm/v7/opdefs/mrrc_A88108.d | 105 ++++++++ src/arch/arm/v7/opdefs/mul_A88114.d | 68 +++-- src/arch/arm/v7/opdefs/mvn_A88115.d | 51 ++-- src/arch/arm/v7/opdefs/mvn_A88116.d | 70 +++--- src/arch/arm/v7/opdefs/mvn_A88117.d | 51 ++++ src/arch/arm/v7/opdefs/nop_A88119.d | 27 +- src/arch/arm/v7/opdefs/orn_A88120.d | 50 ++++ src/arch/arm/v7/opdefs/orn_A88121.d | 51 ++++ src/arch/arm/v7/opdefs/orr_A88122.d | 56 +++-- src/arch/arm/v7/opdefs/orr_A88123.d | 75 +++--- src/arch/arm/v7/opdefs/orr_A88124.d | 52 ++++ src/arch/arm/v7/opdefs/pop_A88131.d | 63 ++--- src/arch/arm/v7/opdefs/pop_A88132.d | 47 ++-- src/arch/arm/v7/opdefs/push_A88133.d | 107 +++----- src/arch/arm/v7/opdefs/qadd16_A88135.d | 65 +++++ src/arch/arm/v7/opdefs/qadd8_A88136.d | 65 +++++ src/arch/arm/v7/opdefs/qadd_A88134.d | 65 +++++ src/arch/arm/v7/opdefs/qasx_A88137.d | 65 +++++ src/arch/arm/v7/opdefs/qdadd_A88138.d | 65 +++++ src/arch/arm/v7/opdefs/qdsub_A88139.d | 65 +++++ src/arch/arm/v7/opdefs/qsax_A88140.d | 65 +++++ src/arch/arm/v7/opdefs/qsub16_A88142.d | 65 +++++ src/arch/arm/v7/opdefs/qsub8_A88143.d | 65 +++++ src/arch/arm/v7/opdefs/qsub_A88141.d | 65 +++++ src/arch/arm/v7/opdefs/rbit_A88144.d | 63 +++++ src/arch/arm/v7/opdefs/rev16_A88146.d | 78 ++++++ src/arch/arm/v7/opdefs/rev_A88145.d | 78 ++++++ src/arch/arm/v7/opdefs/revsh_A88147.d | 78 ++++++ src/arch/arm/v7/opdefs/ror_A88149.d | 74 ++++++ src/arch/arm/v7/opdefs/ror_A88150.d | 90 +++++++ src/arch/arm/v7/opdefs/rrx_A88151.d | 72 ++++++ src/arch/arm/v7/opdefs/rsb_A88152.d | 72 +++--- src/arch/arm/v7/opdefs/rsb_A88153.d | 59 ++--- src/arch/arm/v7/opdefs/rsb_A88154.d | 52 ++++ src/arch/arm/v7/opdefs/rsc_A88155.d | 31 +-- src/arch/arm/v7/opdefs/rsc_A88156.d | 33 +-- src/arch/arm/v7/opdefs/rsc_A88157.d | 52 ++++ src/arch/arm/v7/opdefs/sadd16_A88158.d | 65 +++++ src/arch/arm/v7/opdefs/sadd8_A88159.d | 65 +++++ src/arch/arm/v7/opdefs/sasx_A88160.d | 65 +++++ src/arch/arm/v7/opdefs/sbc_A88161.d | 55 +++-- src/arch/arm/v7/opdefs/sbc_A88162.d | 74 +++--- src/arch/arm/v7/opdefs/sbc_A88163.d | 52 ++++ src/arch/arm/v7/opdefs/sbfx_A88164.d | 67 +++++ src/arch/arm/v7/opdefs/sdiv_A88165.d | 65 +++++ src/arch/arm/v7/opdefs/sel_A88166.d | 65 +++++ src/arch/arm/v7/opdefs/setend_A88167.d | 55 +++++ src/arch/arm/v7/opdefs/sev_A88168.d | 53 ++++ src/arch/arm/v7/opdefs/shadd16_A88169.d | 65 +++++ src/arch/arm/v7/opdefs/shadd8_A88170.d | 65 +++++ src/arch/arm/v7/opdefs/shasx_A88171.d | 65 +++++ src/arch/arm/v7/opdefs/shsax_A88172.d | 65 +++++ src/arch/arm/v7/opdefs/shsub16_A88173.d | 65 +++++ src/arch/arm/v7/opdefs/shsub8_A88174.d | 65 +++++ src/arch/arm/v7/opdefs/smlad_A88177.d | 76 ++++++ src/arch/arm/v7/opdefs/smlal_A88178.d | 57 ++--- src/arch/arm/v7/opdefs/smlald_A88180.d | 76 ++++++ src/arch/arm/v7/opdefs/smlsd_A88182.d | 76 ++++++ src/arch/arm/v7/opdefs/smlsld_A88183.d | 76 ++++++ src/arch/arm/v7/opdefs/smmla_A88184.d | 76 ++++++ src/arch/arm/v7/opdefs/smmls_A88185.d | 76 ++++++ src/arch/arm/v7/opdefs/smmul_A88186.d | 74 ++++++ src/arch/arm/v7/opdefs/smuad_A88187.d | 74 ++++++ src/arch/arm/v7/opdefs/smull_A88189.d | 57 ++--- src/arch/arm/v7/opdefs/str_A88203.d | 121 ++++----- src/arch/arm/v7/opdefs/str_A88204.d | 60 ++--- src/arch/arm/v7/opdefs/str_A88205.d | 89 +++++++ src/arch/arm/v7/opdefs/strb_A88206.d | 101 +++----- src/arch/arm/v7/opdefs/strb_A88207.d | 64 ++--- src/arch/arm/v7/opdefs/strb_A88208.d | 112 +++------ src/arch/arm/v7/opdefs/sub_A88221.d | 96 +++---- src/arch/arm/v7/opdefs/sub_A88222.d | 32 +-- src/arch/arm/v7/opdefs/sub_A88223.d | 82 +++--- src/arch/arm/v7/opdefs/sub_A88224.d | 52 ++++ src/arch/arm/v7/opdefs/sub_A88225.d | 99 ++++---- src/arch/arm/v7/opdefs/sub_A88226.d | 76 ++++++ src/arch/arm/v7/opdefs/svc_A88228.d | 61 +++++ src/arch/arm/v7/opdefs/swp_A88229.d | 52 ++++ src/arch/arm/v7/opdefs/teq_A88237.d | 42 ++-- src/arch/arm/v7/opdefs/teq_A88238.d | 46 ++-- src/arch/arm/v7/opdefs/teq_A88239.d | 49 ++++ src/arch/arm/v7/opdefs/tst_A88240.d | 42 ++-- src/arch/arm/v7/opdefs/tst_A88241.d | 64 +++-- src/arch/arm/v7/opdefs/tst_A88242.d | 49 ++++ src/arch/arm/v7/opdefs/uadd16_A88243.d | 65 +++++ src/arch/arm/v7/opdefs/uadd8_A88244.d | 65 +++++ src/arch/arm/v7/opdefs/uasx_A88245.d | 65 +++++ src/arch/arm/v7/opdefs/ubfx_A88246.d | 67 +++++ src/arch/arm/v7/opdefs/udf_A88247.d | 69 ++++++ src/arch/arm/v7/opdefs/udiv_A88248.d | 65 +++++ src/arch/arm/v7/opdefs/uhadd16_A88249.d | 65 +++++ src/arch/arm/v7/opdefs/uhadd8_A88250.d | 65 +++++ src/arch/arm/v7/opdefs/uhasx_A88251.d | 65 +++++ src/arch/arm/v7/opdefs/uhsax_A88252.d | 65 +++++ src/arch/arm/v7/opdefs/uhsub16_A88253.d | 65 +++++ src/arch/arm/v7/opdefs/uhsub8_A88254.d | 65 +++++ src/arch/arm/v7/opdefs/umaal_A88255.d | 54 ++-- src/arch/arm/v7/opdefs/umlal_A88256.d | 57 ++--- src/arch/arm/v7/opdefs/umull_A88257.d | 57 ++--- src/arch/arm/v7/opdefs/uqadd16_A88258.d | 65 +++++ src/arch/arm/v7/opdefs/uqadd8_A88259.d | 65 +++++ src/arch/arm/v7/opdefs/uqasx_A88260.d | 65 +++++ src/arch/arm/v7/opdefs/uqsax_A88261.d | 65 +++++ src/arch/arm/v7/opdefs/uqsub16_A88262.d | 65 +++++ src/arch/arm/v7/opdefs/uqsub8_A88263.d | 65 +++++ src/arch/arm/v7/opdefs/usad8_A88264.d | 65 +++++ src/arch/arm/v7/opdefs/usada8_A88265.d | 67 +++++ src/arch/arm/v7/opdefs/usat16_A88267.d | 65 +++++ src/arch/arm/v7/opdefs/usat_A88266.d | 67 +++++ src/arch/arm/v7/opdefs/usax_A88268.d | 65 +++++ src/arch/arm/v7/opdefs/usub16_A88269.d | 65 +++++ src/arch/arm/v7/opdefs/usub8_A88270.d | 65 +++++ src/arch/arm/v7/opdefs/uxtab16_A88272.d | 67 +++++ src/arch/arm/v7/opdefs/uxtab_A88271.d | 67 +++++ src/arch/arm/v7/opdefs/uxtah_A88273.d | 67 +++++ src/arch/arm/v7/opdefs/uxtb16_A88275.d | 65 +++++ src/arch/arm/v7/opdefs/uxtb_A88274.d | 64 +++-- src/arch/arm/v7/opdefs/uxth_A88276.d | 80 ++++++ src/arch/arm/v7/opdefs/wfi_A88425.d | 53 ++++ src/arch/arm/v7/opdefs/yield_A88426.d | 27 +- src/arch/arm/v7/operands/Makefile.am | 3 + src/arch/arm/v7/operands/coproc.c | 221 +++++++++++++++++ src/arch/arm/v7/operands/coproc.h | 61 +++++ src/arch/arm/v7/operands/estate.c | 219 ++++++++++++++++ src/arch/arm/v7/operands/estate.h | 61 +++++ src/arch/arm/v7/operands/limitation.c | 258 +++++++++++++++++++ src/arch/arm/v7/operands/limitation.h | 77 ++++++ src/arch/arm/v7/operands/maccess.c | 46 +++- src/arch/arm/v7/operands/maccess.h | 5 +- src/arch/arm/v7/register.c | 2 +- src/arch/dalvik/pseudo/fill.c | 4 +- src/arch/dalvik/pseudo/switch.c | 4 +- src/arch/immediate.c | 18 ++ src/arch/immediate.h | 3 + src/arch/instruction-int.h | 2 +- src/arch/instruction.c | 25 +- src/arch/instruction.h | 4 +- src/arch/raw.c | 4 +- src/arch/undefined.c | 4 +- tools/d2c/args/grammar.y | 18 +- tools/d2c/args/manager.c | 201 +++++++++++++-- tools/d2c/args/manager.h | 17 +- tools/d2c/args/tokens.l | 7 + tools/d2c/bits/manager.c | 8 + tools/d2c/conv/manager.c | 154 +++++++++++- tools/d2c/conv/manager.h | 15 +- tools/d2c/d2c.mk | 3 +- tools/d2c/d2c_genmakefile.sh | 11 +- tools/d2c/grammar.y | 13 +- tools/d2c/pproc.c | 53 ++++ tools/d2c/pproc.h | 7 + tools/d2c/rules/grammar.y | 3 +- tools/d2c/rules/manager.c | 330 ++++++++++++++++++++----- tools/d2c/rules/manager.h | 8 +- tools/d2c/spec.c | 12 +- tools/d2c/syntax/manager.c | 63 +++-- tools/d2c/tokens.l | 4 +- 256 files changed, 14122 insertions(+), 3315 deletions(-) create mode 100644 src/arch/arm/v7/cregister.c create mode 100644 src/arch/arm/v7/cregister.h create mode 100644 src/arch/arm/v7/opdefs/adc_A883.d create mode 100644 src/arch/arm/v7/opdefs/add_A8810.d create mode 100644 src/arch/arm/v7/opdefs/add_A8811.d create mode 100644 src/arch/arm/v7/opdefs/add_A888.d create mode 100644 src/arch/arm/v7/opdefs/and_A8815.d create mode 100644 src/arch/arm/v7/opdefs/asr_A8817.d create mode 100644 src/arch/arm/v7/opdefs/bfc_A8819.d create mode 100644 src/arch/arm/v7/opdefs/bfi_A8820.d create mode 100644 src/arch/arm/v7/opdefs/bic_A8823.d create mode 100644 src/arch/arm/v7/opdefs/bkpt_A8824.d create mode 100644 src/arch/arm/v7/opdefs/bxj_A8828.d create mode 100644 src/arch/arm/v7/opdefs/cb_A8829.d delete mode 100644 src/arch/arm/v7/opdefs/cbnz_A8829.d create mode 100644 src/arch/arm/v7/opdefs/cdp_A8830.d create mode 100644 src/arch/arm/v7/opdefs/clrex_A8832.d create mode 100644 src/arch/arm/v7/opdefs/clz_A8833.d create mode 100644 src/arch/arm/v7/opdefs/cmn_A8836.d create mode 100644 src/arch/arm/v7/opdefs/cmp_A8839.d create mode 100644 src/arch/arm/v7/opdefs/dbg_A8842.d create mode 100644 src/arch/arm/v7/opdefs/dmb_A8843.d create mode 100644 src/arch/arm/v7/opdefs/dsb_A8844.d create mode 100644 src/arch/arm/v7/opdefs/eor_A8848.d create mode 100644 src/arch/arm/v7/opdefs/ldr_A8866.d create mode 100644 src/arch/arm/v7/opdefs/ldrb_A8869.d create mode 100644 src/arch/arm/v7/opdefs/ldrbt_A8871.d create mode 100644 src/arch/arm/v7/opdefs/ldrd_A8872.d create mode 100644 src/arch/arm/v7/opdefs/ldrd_A8873.d create mode 100644 src/arch/arm/v7/opdefs/ldrd_A8874.d create mode 100644 src/arch/arm/v7/opdefs/ldrex_A8875.d create mode 100644 src/arch/arm/v7/opdefs/ldrexb_A8876.d create mode 100644 src/arch/arm/v7/opdefs/ldrexd_A8877.d create mode 100644 src/arch/arm/v7/opdefs/ldrexh_A8878.d create mode 100644 src/arch/arm/v7/opdefs/ldrh_A8879.d create mode 100644 src/arch/arm/v7/opdefs/ldrh_A8880.d create mode 100644 src/arch/arm/v7/opdefs/ldrh_A8881.d create mode 100644 src/arch/arm/v7/opdefs/ldrh_A8882.d create mode 100644 src/arch/arm/v7/opdefs/ldrht_A8883.d create mode 100644 src/arch/arm/v7/opdefs/ldrsb_A8884.d create mode 100644 src/arch/arm/v7/opdefs/ldrsb_A8885.d create mode 100644 src/arch/arm/v7/opdefs/ldrsb_A8886.d create mode 100644 src/arch/arm/v7/opdefs/ldrsbt_A8887.d create mode 100644 src/arch/arm/v7/opdefs/ldrsh_A8888.d create mode 100644 src/arch/arm/v7/opdefs/ldrsh_A8889.d create mode 100644 src/arch/arm/v7/opdefs/ldrsh_A8890.d create mode 100644 src/arch/arm/v7/opdefs/ldrsht_A8891.d create mode 100644 src/arch/arm/v7/opdefs/ldrt_A8892.d create mode 100644 src/arch/arm/v7/opdefs/lsl_A8895.d create mode 100644 src/arch/arm/v7/opdefs/lsr_A8897.d create mode 100644 src/arch/arm/v7/opdefs/mcr_A8898.d create mode 100644 src/arch/arm/v7/opdefs/mcrr_A8899.d create mode 100644 src/arch/arm/v7/opdefs/mrc_A88107.d create mode 100644 src/arch/arm/v7/opdefs/mrrc_A88108.d create mode 100644 src/arch/arm/v7/opdefs/mvn_A88117.d create mode 100644 src/arch/arm/v7/opdefs/orn_A88120.d create mode 100644 src/arch/arm/v7/opdefs/orn_A88121.d create mode 100644 src/arch/arm/v7/opdefs/orr_A88124.d create mode 100644 src/arch/arm/v7/opdefs/qadd16_A88135.d create mode 100644 src/arch/arm/v7/opdefs/qadd8_A88136.d create mode 100644 src/arch/arm/v7/opdefs/qadd_A88134.d create mode 100644 src/arch/arm/v7/opdefs/qasx_A88137.d create mode 100644 src/arch/arm/v7/opdefs/qdadd_A88138.d create mode 100644 src/arch/arm/v7/opdefs/qdsub_A88139.d create mode 100644 src/arch/arm/v7/opdefs/qsax_A88140.d create mode 100644 src/arch/arm/v7/opdefs/qsub16_A88142.d create mode 100644 src/arch/arm/v7/opdefs/qsub8_A88143.d create mode 100644 src/arch/arm/v7/opdefs/qsub_A88141.d create mode 100644 src/arch/arm/v7/opdefs/rbit_A88144.d create mode 100644 src/arch/arm/v7/opdefs/rev16_A88146.d create mode 100644 src/arch/arm/v7/opdefs/rev_A88145.d create mode 100644 src/arch/arm/v7/opdefs/revsh_A88147.d create mode 100644 src/arch/arm/v7/opdefs/ror_A88149.d create mode 100644 src/arch/arm/v7/opdefs/ror_A88150.d create mode 100644 src/arch/arm/v7/opdefs/rrx_A88151.d create mode 100644 src/arch/arm/v7/opdefs/rsb_A88154.d create mode 100644 src/arch/arm/v7/opdefs/rsc_A88157.d create mode 100644 src/arch/arm/v7/opdefs/sadd16_A88158.d create mode 100644 src/arch/arm/v7/opdefs/sadd8_A88159.d create mode 100644 src/arch/arm/v7/opdefs/sasx_A88160.d create mode 100644 src/arch/arm/v7/opdefs/sbc_A88163.d create mode 100644 src/arch/arm/v7/opdefs/sbfx_A88164.d create mode 100644 src/arch/arm/v7/opdefs/sdiv_A88165.d create mode 100644 src/arch/arm/v7/opdefs/sel_A88166.d create mode 100644 src/arch/arm/v7/opdefs/setend_A88167.d create mode 100644 src/arch/arm/v7/opdefs/sev_A88168.d create mode 100644 src/arch/arm/v7/opdefs/shadd16_A88169.d create mode 100644 src/arch/arm/v7/opdefs/shadd8_A88170.d create mode 100644 src/arch/arm/v7/opdefs/shasx_A88171.d create mode 100644 src/arch/arm/v7/opdefs/shsax_A88172.d create mode 100644 src/arch/arm/v7/opdefs/shsub16_A88173.d create mode 100644 src/arch/arm/v7/opdefs/shsub8_A88174.d create mode 100644 src/arch/arm/v7/opdefs/smlad_A88177.d create mode 100644 src/arch/arm/v7/opdefs/smlald_A88180.d create mode 100644 src/arch/arm/v7/opdefs/smlsd_A88182.d create mode 100644 src/arch/arm/v7/opdefs/smlsld_A88183.d create mode 100644 src/arch/arm/v7/opdefs/smmla_A88184.d create mode 100644 src/arch/arm/v7/opdefs/smmls_A88185.d create mode 100644 src/arch/arm/v7/opdefs/smmul_A88186.d create mode 100644 src/arch/arm/v7/opdefs/smuad_A88187.d create mode 100644 src/arch/arm/v7/opdefs/str_A88205.d create mode 100644 src/arch/arm/v7/opdefs/sub_A88224.d create mode 100644 src/arch/arm/v7/opdefs/sub_A88226.d create mode 100644 src/arch/arm/v7/opdefs/svc_A88228.d create mode 100644 src/arch/arm/v7/opdefs/swp_A88229.d create mode 100644 src/arch/arm/v7/opdefs/teq_A88239.d create mode 100644 src/arch/arm/v7/opdefs/tst_A88242.d create mode 100644 src/arch/arm/v7/opdefs/uadd16_A88243.d create mode 100644 src/arch/arm/v7/opdefs/uadd8_A88244.d create mode 100644 src/arch/arm/v7/opdefs/uasx_A88245.d create mode 100644 src/arch/arm/v7/opdefs/ubfx_A88246.d create mode 100644 src/arch/arm/v7/opdefs/udf_A88247.d create mode 100644 src/arch/arm/v7/opdefs/udiv_A88248.d create mode 100644 src/arch/arm/v7/opdefs/uhadd16_A88249.d create mode 100644 src/arch/arm/v7/opdefs/uhadd8_A88250.d create mode 100644 src/arch/arm/v7/opdefs/uhasx_A88251.d create mode 100644 src/arch/arm/v7/opdefs/uhsax_A88252.d create mode 100644 src/arch/arm/v7/opdefs/uhsub16_A88253.d create mode 100644 src/arch/arm/v7/opdefs/uhsub8_A88254.d create mode 100644 src/arch/arm/v7/opdefs/uqadd16_A88258.d create mode 100644 src/arch/arm/v7/opdefs/uqadd8_A88259.d create mode 100644 src/arch/arm/v7/opdefs/uqasx_A88260.d create mode 100644 src/arch/arm/v7/opdefs/uqsax_A88261.d create mode 100644 src/arch/arm/v7/opdefs/uqsub16_A88262.d create mode 100644 src/arch/arm/v7/opdefs/uqsub8_A88263.d create mode 100644 src/arch/arm/v7/opdefs/usad8_A88264.d create mode 100644 src/arch/arm/v7/opdefs/usada8_A88265.d create mode 100644 src/arch/arm/v7/opdefs/usat16_A88267.d create mode 100644 src/arch/arm/v7/opdefs/usat_A88266.d create mode 100644 src/arch/arm/v7/opdefs/usax_A88268.d create mode 100644 src/arch/arm/v7/opdefs/usub16_A88269.d create mode 100644 src/arch/arm/v7/opdefs/usub8_A88270.d create mode 100644 src/arch/arm/v7/opdefs/uxtab16_A88272.d create mode 100644 src/arch/arm/v7/opdefs/uxtab_A88271.d create mode 100644 src/arch/arm/v7/opdefs/uxtah_A88273.d create mode 100644 src/arch/arm/v7/opdefs/uxtb16_A88275.d create mode 100644 src/arch/arm/v7/opdefs/uxth_A88276.d create mode 100644 src/arch/arm/v7/opdefs/wfi_A88425.d create mode 100644 src/arch/arm/v7/operands/coproc.c create mode 100644 src/arch/arm/v7/operands/coproc.h create mode 100644 src/arch/arm/v7/operands/estate.c create mode 100644 src/arch/arm/v7/operands/estate.h create mode 100644 src/arch/arm/v7/operands/limitation.c create mode 100644 src/arch/arm/v7/operands/limitation.h diff --git a/ChangeLog b/ChangeLog index 4e50933..0d24171 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,293 @@ +16-05-22 Cyrille Bagard + + * src/arch/arm/v7/Makefile.am: + Add the 'cregister.[ch]' files to libarcharmv7_la_SOURCES. + + * src/arch/arm/v7/cregister.c: + * src/arch/arm/v7/cregister.h: + New entries: handle co-processor registers. + + * src/arch/arm/v7/fetch.c: + Update code as the type of the used operands changed. + + * src/arch/arm/v7/helpers.h: + Provide new helpers for decoding ARMv7 operands. + + * src/arch/arm/v7/opcodes/opcodes_tmp_arm.h: + * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h: + * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h: + Refresh the list of all available ARMv7 instructions prototypes. + + * src/arch/arm/v7/opdefs/Makefile.am: + Update content. + + * src/arch/arm/v7/opdefs/adc_A881.d: + * src/arch/arm/v7/opdefs/adc_A882.d: + * src/arch/arm/v7/opdefs/adc_A883.d: + * src/arch/arm/v7/opdefs/add_A8810.d: + * src/arch/arm/v7/opdefs/add_A8811.d: + * src/arch/arm/v7/opdefs/add_A884.d: + * src/arch/arm/v7/opdefs/add_A885.d: + * src/arch/arm/v7/opdefs/add_A886.d: + * src/arch/arm/v7/opdefs/add_A887.d: + * src/arch/arm/v7/opdefs/add_A888.d: + * src/arch/arm/v7/opdefs/add_A889.d: + * src/arch/arm/v7/opdefs/adr_A8812.d: + * src/arch/arm/v7/opdefs/and_A8813.d: + * src/arch/arm/v7/opdefs/and_A8814.d: + * src/arch/arm/v7/opdefs/and_A8815.d: + * src/arch/arm/v7/opdefs/asr_A8816.d: + * src/arch/arm/v7/opdefs/asr_A8817.d: + * src/arch/arm/v7/opdefs/b_A8818.d: + * src/arch/arm/v7/opdefs/bfc_A8819.d: + * src/arch/arm/v7/opdefs/bfi_A8820.d: + * src/arch/arm/v7/opdefs/bic_A8821.d: + * src/arch/arm/v7/opdefs/bic_A8822.d: + * src/arch/arm/v7/opdefs/bic_A8823.d: + * src/arch/arm/v7/opdefs/bkpt_A8824.d: + * src/arch/arm/v7/opdefs/bl_A8825.d: + * src/arch/arm/v7/opdefs/blx_A8826.d: + * src/arch/arm/v7/opdefs/bx_A8827.d: + * src/arch/arm/v7/opdefs/bxj_A8828.d: + * src/arch/arm/v7/opdefs/cb_A8829.d: + * src/arch/arm/v7/opdefs/cbnz_A8829.d: + * src/arch/arm/v7/opdefs/cdp_A8830.d: + * src/arch/arm/v7/opdefs/clrex_A8832.d: + * src/arch/arm/v7/opdefs/clz_A8833.d: + * src/arch/arm/v7/opdefs/cmn_A8834.d: + * src/arch/arm/v7/opdefs/cmn_A8835.d: + * src/arch/arm/v7/opdefs/cmn_A8836.d: + * src/arch/arm/v7/opdefs/cmp_A8837.d: + * src/arch/arm/v7/opdefs/cmp_A8838.d: + * src/arch/arm/v7/opdefs/cmp_A8839.d: + * src/arch/arm/v7/opdefs/dbg_A8842.d: + * src/arch/arm/v7/opdefs/dmb_A8843.d: + * src/arch/arm/v7/opdefs/dsb_A8844.d: + * src/arch/arm/v7/opdefs/eor_A8846.d: + * src/arch/arm/v7/opdefs/eor_A8847.d: + * src/arch/arm/v7/opdefs/eor_A8848.d: + * src/arch/arm/v7/opdefs/ldr_A8862.d: + * src/arch/arm/v7/opdefs/ldr_A8863.d: + * src/arch/arm/v7/opdefs/ldr_A8864.d: + * src/arch/arm/v7/opdefs/ldr_A8865.d: + * src/arch/arm/v7/opdefs/ldr_A8866.d: + * src/arch/arm/v7/opdefs/ldrb_A8867.d: + * src/arch/arm/v7/opdefs/ldrb_A8868.d: + * src/arch/arm/v7/opdefs/ldrb_A8869.d: + * src/arch/arm/v7/opdefs/ldrb_A8870.d: + * src/arch/arm/v7/opdefs/ldrbt_A8871.d: + * src/arch/arm/v7/opdefs/ldrd_A8872.d: + * src/arch/arm/v7/opdefs/ldrd_A8873.d: + * src/arch/arm/v7/opdefs/ldrd_A8874.d: + * src/arch/arm/v7/opdefs/ldrex_A8875.d: + * src/arch/arm/v7/opdefs/ldrexb_A8876.d: + * src/arch/arm/v7/opdefs/ldrexd_A8877.d: + * src/arch/arm/v7/opdefs/ldrexh_A8878.d: + * src/arch/arm/v7/opdefs/ldrh_A8879.d: + * src/arch/arm/v7/opdefs/ldrh_A8880.d: + * src/arch/arm/v7/opdefs/ldrh_A8881.d: + * src/arch/arm/v7/opdefs/ldrh_A8882.d: + * src/arch/arm/v7/opdefs/ldrht_A8883.d: + * src/arch/arm/v7/opdefs/ldrsb_A8884.d: + * src/arch/arm/v7/opdefs/ldrsb_A8885.d: + * src/arch/arm/v7/opdefs/ldrsb_A8886.d: + * src/arch/arm/v7/opdefs/ldrsbt_A8887.d: + * src/arch/arm/v7/opdefs/ldrsh_A8888.d: + * src/arch/arm/v7/opdefs/ldrsh_A8889.d: + * src/arch/arm/v7/opdefs/ldrsh_A8890.d: + * src/arch/arm/v7/opdefs/ldrsht_A8891.d: + * src/arch/arm/v7/opdefs/ldrt_A8892.d: + * src/arch/arm/v7/opdefs/lsl_A8894.d: + * src/arch/arm/v7/opdefs/lsl_A8895.d: + * src/arch/arm/v7/opdefs/lsr_A8896.d: + * src/arch/arm/v7/opdefs/lsr_A8897.d: + * src/arch/arm/v7/opdefs/mcr_A8898.d: + * src/arch/arm/v7/opdefs/mcrr_A8899.d: + * src/arch/arm/v7/opdefs/mla_A88100.d: + * src/arch/arm/v7/opdefs/mls_A88101.d: + * src/arch/arm/v7/opdefs/mov_A88102.d: + * src/arch/arm/v7/opdefs/mov_A88103.d: + * src/arch/arm/v7/opdefs/mov_A88104.d: + * src/arch/arm/v7/opdefs/movt_A88106.d: + * src/arch/arm/v7/opdefs/mrc_A88107.d: + * src/arch/arm/v7/opdefs/mrrc_A88108.d: + * src/arch/arm/v7/opdefs/mul_A88114.d: + * src/arch/arm/v7/opdefs/mvn_A88115.d: + * src/arch/arm/v7/opdefs/mvn_A88116.d: + * src/arch/arm/v7/opdefs/mvn_A88117.d: + * src/arch/arm/v7/opdefs/nop_A88119.d: + * src/arch/arm/v7/opdefs/orn_A88120.d: + * src/arch/arm/v7/opdefs/orn_A88121.d: + * src/arch/arm/v7/opdefs/orr_A88122.d: + * src/arch/arm/v7/opdefs/orr_A88123.d: + * src/arch/arm/v7/opdefs/orr_A88124.d: + * src/arch/arm/v7/opdefs/pop_A88131.d: + * src/arch/arm/v7/opdefs/pop_A88132.d: + * src/arch/arm/v7/opdefs/push_A88133.d: + * src/arch/arm/v7/opdefs/qadd16_A88135.d: + * src/arch/arm/v7/opdefs/qadd8_A88136.d: + * src/arch/arm/v7/opdefs/qadd_A88134.d: + * src/arch/arm/v7/opdefs/qasx_A88137.d: + * src/arch/arm/v7/opdefs/qdadd_A88138.d: + * src/arch/arm/v7/opdefs/qdsub_A88139.d: + * src/arch/arm/v7/opdefs/qsax_A88140.d: + * src/arch/arm/v7/opdefs/qsub16_A88142.d: + * src/arch/arm/v7/opdefs/qsub8_A88143.d: + * src/arch/arm/v7/opdefs/qsub_A88141.d: + * src/arch/arm/v7/opdefs/rbit_A88144.d: + * src/arch/arm/v7/opdefs/rev16_A88146.d: + * src/arch/arm/v7/opdefs/rev_A88145.d: + * src/arch/arm/v7/opdefs/revsh_A88147.d: + * src/arch/arm/v7/opdefs/ror_A88149.d: + * src/arch/arm/v7/opdefs/ror_A88150.d: + * src/arch/arm/v7/opdefs/rrx_A88151.d: + * src/arch/arm/v7/opdefs/rsb_A88152.d: + * src/arch/arm/v7/opdefs/rsb_A88153.d: + * src/arch/arm/v7/opdefs/rsb_A88154.d: + * src/arch/arm/v7/opdefs/rsc_A88155.d: + * src/arch/arm/v7/opdefs/rsc_A88156.d: + * src/arch/arm/v7/opdefs/rsc_A88157.d: + * src/arch/arm/v7/opdefs/sadd16_A88158.d: + * src/arch/arm/v7/opdefs/sadd8_A88159.d: + * src/arch/arm/v7/opdefs/sasx_A88160.d: + * src/arch/arm/v7/opdefs/sbc_A88161.d: + * src/arch/arm/v7/opdefs/sbc_A88162.d: + * src/arch/arm/v7/opdefs/sbc_A88163.d: + * src/arch/arm/v7/opdefs/sbfx_A88164.d: + * src/arch/arm/v7/opdefs/sdiv_A88165.d: + * src/arch/arm/v7/opdefs/sel_A88166.d: + * src/arch/arm/v7/opdefs/setend_A88167.d: + * src/arch/arm/v7/opdefs/sev_A88168.d: + * src/arch/arm/v7/opdefs/shadd16_A88169.d: + * src/arch/arm/v7/opdefs/shadd8_A88170.d: + * src/arch/arm/v7/opdefs/shasx_A88171.d: + * src/arch/arm/v7/opdefs/shsax_A88172.d: + * src/arch/arm/v7/opdefs/shsub16_A88173.d: + * src/arch/arm/v7/opdefs/shsub8_A88174.d: + * src/arch/arm/v7/opdefs/smlad_A88177.d: + * src/arch/arm/v7/opdefs/smlal_A88178.d: + * src/arch/arm/v7/opdefs/smlald_A88180.d: + * src/arch/arm/v7/opdefs/smlsd_A88182.d: + * src/arch/arm/v7/opdefs/smlsld_A88183.d: + * src/arch/arm/v7/opdefs/smmla_A88184.d: + * src/arch/arm/v7/opdefs/smmls_A88185.d: + * src/arch/arm/v7/opdefs/smmul_A88186.d: + * src/arch/arm/v7/opdefs/smuad_A88187.d: + * src/arch/arm/v7/opdefs/smull_A88189.d: + * src/arch/arm/v7/opdefs/str_A88203.d: + * src/arch/arm/v7/opdefs/str_A88204.d: + * src/arch/arm/v7/opdefs/str_A88205.d: + * src/arch/arm/v7/opdefs/strb_A88206.d: + * src/arch/arm/v7/opdefs/strb_A88207.d: + * src/arch/arm/v7/opdefs/strb_A88208.d: + * src/arch/arm/v7/opdefs/sub_A88221.d: + * src/arch/arm/v7/opdefs/sub_A88222.d: + * src/arch/arm/v7/opdefs/sub_A88223.d: + * src/arch/arm/v7/opdefs/sub_A88224.d: + * src/arch/arm/v7/opdefs/sub_A88225.d: + * src/arch/arm/v7/opdefs/sub_A88226.d: + * src/arch/arm/v7/opdefs/svc_A88228.d: + * src/arch/arm/v7/opdefs/swp_A88229.d: + * src/arch/arm/v7/opdefs/teq_A88237.d: + * src/arch/arm/v7/opdefs/teq_A88238.d: + * src/arch/arm/v7/opdefs/teq_A88239.d: + * src/arch/arm/v7/opdefs/tst_A88240.d: + * src/arch/arm/v7/opdefs/tst_A88241.d: + * src/arch/arm/v7/opdefs/tst_A88242.d: + * src/arch/arm/v7/opdefs/uadd16_A88243.d: + * src/arch/arm/v7/opdefs/uadd8_A88244.d: + * src/arch/arm/v7/opdefs/uasx_A88245.d: + * src/arch/arm/v7/opdefs/ubfx_A88246.d: + * src/arch/arm/v7/opdefs/udf_A88247.d: + * src/arch/arm/v7/opdefs/udiv_A88248.d: + * src/arch/arm/v7/opdefs/uhadd16_A88249.d: + * src/arch/arm/v7/opdefs/uhadd8_A88250.d: + * src/arch/arm/v7/opdefs/uhasx_A88251.d: + * src/arch/arm/v7/opdefs/uhsax_A88252.d: + * src/arch/arm/v7/opdefs/uhsub16_A88253.d: + * src/arch/arm/v7/opdefs/uhsub8_A88254.d: + * src/arch/arm/v7/opdefs/umaal_A88255.d: + * src/arch/arm/v7/opdefs/umlal_A88256.d: + * src/arch/arm/v7/opdefs/umull_A88257.d: + * src/arch/arm/v7/opdefs/uqadd16_A88258.d: + * src/arch/arm/v7/opdefs/uqadd8_A88259.d: + * src/arch/arm/v7/opdefs/uqasx_A88260.d: + * src/arch/arm/v7/opdefs/uqsax_A88261.d: + * src/arch/arm/v7/opdefs/uqsub16_A88262.d: + * src/arch/arm/v7/opdefs/uqsub8_A88263.d: + * src/arch/arm/v7/opdefs/usad8_A88264.d: + * src/arch/arm/v7/opdefs/usada8_A88265.d: + * src/arch/arm/v7/opdefs/usat16_A88267.d: + * src/arch/arm/v7/opdefs/usat_A88266.d: + * src/arch/arm/v7/opdefs/usax_A88268.d: + * src/arch/arm/v7/opdefs/usub16_A88269.d: + * src/arch/arm/v7/opdefs/usub8_A88270.d: + * src/arch/arm/v7/opdefs/uxtab16_A88272.d: + * src/arch/arm/v7/opdefs/uxtab_A88271.d: + * src/arch/arm/v7/opdefs/uxtah_A88273.d: + * src/arch/arm/v7/opdefs/uxtb16_A88275.d: + * src/arch/arm/v7/opdefs/uxtb_A88274.d: + * src/arch/arm/v7/opdefs/uxth_A88276.d: + * src/arch/arm/v7/opdefs/wfi_A88425.d: + * src/arch/arm/v7/opdefs/yield_A88426.d: + New, updated and renamed entries. + + * src/arch/arm/v7/operands/Makefile.am: + Add the 'coproc.[ch]', 'estate.[ch]' and 'limitation.[ch]' files + to libarcharmv7operands_la_SOURCES. + + * src/arch/arm/v7/operands/coproc.c: + * src/arch/arm/v7/operands/coproc.h: + * src/arch/arm/v7/operands/estate.c: + * src/arch/arm/v7/operands/estate.h: + * src/arch/arm/v7/operands/limitation.c: + * src/arch/arm/v7/operands/limitation.h: + New entries: add support for new kind of ARMv7 operands. + + * src/arch/arm/v7/operands/maccess.c: + * src/arch/arm/v7/operands/maccess.h: + Extend the support of ARMv7 memory access operands. + + * src/arch/arm/v7/register.c: + Typo. + + * src/arch/dalvik/pseudo/fill.c: + * src/arch/dalvik/pseudo/switch.c: + Update code. + + * src/arch/immediate.c: + * src/arch/immediate.h: + Provide the raw value for internal usage. + + * src/arch/instruction-int.h: + * src/arch/instruction.c: + * src/arch/instruction.h: + Build and cache instruction keyword. + + * src/arch/raw.c: + * src/arch/undefined.c: + Update code. + + * tools/d2c/args/grammar.y: + * tools/d2c/args/manager.c: + * tools/d2c/args/manager.h: + * tools/d2c/args/tokens.l: + * tools/d2c/bits/manager.c: + * tools/d2c/conv/manager.c: + * tools/d2c/conv/manager.h: + * tools/d2c/d2c.mk: + * tools/d2c/d2c_genmakefile.sh: + * tools/d2c/grammar.y: + * tools/d2c/pproc.c: + * tools/d2c/pproc.h: + * tools/d2c/rules/grammar.y: + * tools/d2c/rules/manager.c: + * tools/d2c/rules/manager.h: + * tools/d2c/spec.c: + * tools/d2c/syntax/manager.c: + * tools/d2c/tokens.l: + Extend the compiler to transform all the new ARMv7 encoding definitions. + 16-05-20 Cyrille Bagard * src/glibext/gwidthtracker.c: diff --git a/src/arch/arm/v7/Makefile.am b/src/arch/arm/v7/Makefile.am index cea4dda..6f5362d 100644 --- a/src/arch/arm/v7/Makefile.am +++ b/src/arch/arm/v7/Makefile.am @@ -4,6 +4,7 @@ noinst_LTLIBRARIES = libarcharmv7.la libarcharmv7_la_SOURCES = \ arm.h arm.c \ context.h context.c \ + cregister.h cregister.c \ fetch.h fetch.c \ helpers.h helpers.c \ instruction.h instruction.c \ diff --git a/src/arch/arm/v7/cregister.c b/src/arch/arm/v7/cregister.c new file mode 100644 index 0000000..62f3833 --- /dev/null +++ b/src/arch/arm/v7/cregister.c @@ -0,0 +1,212 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * cregisters.c - aides auxiliaires relatives aux registres de co-processeur ARMv7 + * + * Copyright (C) 2016 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * OpenIDA is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * OpenIDA is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +#include "cregister.h" + + +#include + + +#include "../register-int.h" + + + +/* Représentation d'un registre de co-processeur ARMv7 (instance) */ +struct _GArmV7CRegister +{ + GArmRegister parent; /* Instance parente */ + +}; + + +/* Représentation d'un registre de co-processeur ARMv7 (classe) */ +struct _GArmV7CRegisterClass +{ + GArmRegisterClass parent; /* Classe parente */ + +}; + + + +/* Initialise la classe des registres de co-processeur ARMv7. */ +static void g_armv7_cregister_class_init(GArmV7CRegisterClass *); + +/* Initialise une instance de registre de co-processeur ARMv7. */ +static void g_armv7_cregister_init(GArmV7CRegister *); + +/* Supprime toutes les références externes. */ +static void g_armv7_cregister_dispose(GArmV7CRegister *); + +/* Procède à la libération totale de la mémoire. */ +static void g_armv7_cregister_finalize(GArmV7CRegister *); + +/* Traduit un registre en version humainement lisible. */ +static void g_armv7_cregister_print(const GArmV7CRegister *, GBufferLine *, AsmSyntax); + + + +/* Indique le type défini pour une représentation d'un registre de co-processeur ARMv7. */ +G_DEFINE_TYPE(GArmV7CRegister, g_armv7_cregister, G_TYPE_ARM_REGISTER); + + +/****************************************************************************** +* * +* Paramètres : klass = classe à initialiser. * +* * +* Description : Initialise la classe des registres de co-processeur ARMv7. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_cregister_class_init(GArmV7CRegisterClass *klass) +{ + GObjectClass *object_class; /* Autre version de la classe */ + GArchRegisterClass *reg_class; /* Classe de haut niveau */ + + object_class = G_OBJECT_CLASS(klass); + reg_class = G_ARCH_REGISTER_CLASS(klass); + + object_class->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_cregister_dispose; + object_class->finalize = (GObjectFinalizeFunc)g_armv7_cregister_finalize; + + reg_class->print = (reg_print_fc)g_armv7_cregister_print; + +} + + +/****************************************************************************** +* * +* Paramètres : reg = instance à initialiser. * +* * +* Description : Initialise une instance de registre de co-processeur ARMv7. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_cregister_init(GArmV7CRegister *reg) +{ + +} + + +/****************************************************************************** +* * +* Paramètres : reg = instance d'objet GLib à traiter. * +* * +* Description : Supprime toutes les références externes. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_cregister_dispose(GArmV7CRegister *reg) +{ + G_OBJECT_CLASS(g_armv7_cregister_parent_class)->dispose(G_OBJECT(reg)); + +} + + +/****************************************************************************** +* * +* Paramètres : reg = instance d'objet GLib à traiter. * +* * +* Description : Procède à la libération totale de la mémoire. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_cregister_finalize(GArmV7CRegister *reg) +{ + G_OBJECT_CLASS(g_armv7_cregister_parent_class)->finalize(G_OBJECT(reg)); + +} + + +/****************************************************************************** +* * +* Paramètres : index = indice du registre correspondant. * +* * +* Description : Crée une réprésentation de registre de co-processeur ARMv7. * +* * +* Retour : Adresse de la structure mise en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArmV7CRegister *g_armv7_cregister_new(uint8_t index) +{ + GArmV7CRegister *result; /* Structure à retourner */ + + result = g_object_new(G_TYPE_ARMV7_CREGISTER, NULL); + + G_ARM_REGISTER(result)->index = index; + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : reg = registre à transcrire. * +* line = ligne tampon où imprimer l'opérande donné. * +* syntax = type de représentation demandée. * +* * +* Description : Traduit un registre en version humainement lisible. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_cregister_print(const GArmV7CRegister *reg, GBufferLine *line, AsmSyntax syntax) +{ + char key[MAX_REGNAME_LEN]; /* Mot clef principal */ + size_t klen; /* Taille de ce mot clef */ + + switch (G_ARM_REGISTER(reg)->index) + { + case 0 ... 15: + klen = snprintf(key, MAX_REGNAME_LEN, "c%hhu", G_ARM_REGISTER(reg)->index); + break; + default: + klen = snprintf(key, MAX_REGNAME_LEN, "c??"); + break; + } + + g_buffer_line_insert_text(line, BLC_ASSEMBLY, key, klen, RTT_REGISTER); + +} diff --git a/src/arch/arm/v7/cregister.h b/src/arch/arm/v7/cregister.h new file mode 100644 index 0000000..c0dfa7b --- /dev/null +++ b/src/arch/arm/v7/cregister.h @@ -0,0 +1,56 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * cregisters.h - prototypes pour les aides auxiliaires relatives aux registres de co-processeur ARMv7 + * + * Copyright (C) 2016 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * OpenIDA is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * OpenIDA is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +#ifndef _ARCH_ARM_V7_CREGISTER_H +#define _ARCH_ARM_V7_CREGISTER_H + + +#include +#include + + + +#define G_TYPE_ARMV7_CREGISTER g_armv7_cregister_get_type() +#define G_ARMV7_CREGISTER(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_armv7_cregister_get_type(), GArmV7CRegister)) +#define G_IS_ARMV7_CREGISTER(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), g_armv7_cregister_get_type())) +#define G_ARMV7_CREGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_CREGISTER, GArmV7CRegisterClass)) +#define G_IS_ARMV7_CREGISTER_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_CREGISTER)) +#define G_ARMV7_CREGISTER_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_CREGISTER, GArmV7CRegisterClass)) + + +/* Représentation d'un registre de co-processeur ARMv7 (instance) */ +typedef struct _GArmV7CRegister GArmV7CRegister; + +/* Représentation d'un registre de co-processeur ARMv7 (classe) */ +typedef struct _GArmV7CRegisterClass GArmV7CRegisterClass; + + +/* Indique le type défini pour une représentation d'un registre de co-processeur ARMv7. */ +GType g_armv7_cregister_get_type(void); + +/* Crée une réprésentation de registre de co-processeur ARMv7. */ +GArmV7CRegister *g_armv7_cregister_new(uint8_t); + + + +#endif /* _ARCH_ARM_V7_CREGISTER_H */ diff --git a/src/arch/arm/v7/fetch.c b/src/arch/arm/v7/fetch.c index 6ca98ca..206e6e6 100644 --- a/src/arch/arm/v7/fetch.c +++ b/src/arch/arm/v7/fetch.c @@ -368,7 +368,6 @@ void help_fetching_with_instruction_ldr_literal_with_orig(GArchInstruction *inst const mrange_t *range; /* Emplacementt d'instruction */ phys_t phys_pc; /* Position dans l'exécution */ GArchOperand *op; /* Opérande de surcouche */ - GArchOperand *sub_op; /* Opérande numérique en place */ uint32_t offset; /* Décallage encodé en dur */ bool ret; /* Bilan d'une récupération */ off_t val_offset; /* Position de valeur à lire */ @@ -411,11 +410,9 @@ void help_fetching_with_instruction_ldr_literal_with_orig(GArchInstruction *inst } op = g_arch_instruction_get_operand(instr, 1); - assert(G_IS_ARMV7_OFFSET_OPERAND(op)); + assert(G_IS_IMM_OPERAND(op)); - sub_op = g_armv7_offset_operand_get_value(G_ARMV7_OFFSET_OPERAND(op)); - - ret = g_imm_operand_get_value(G_IMM_OPERAND(sub_op), MDS_32_BITS_UNSIGNED, &offset); + ret = g_imm_operand_get_value(G_IMM_OPERAND(op), MDS_32_BITS_UNSIGNED, &offset); if (!ret) { assert(0); @@ -424,10 +421,7 @@ void help_fetching_with_instruction_ldr_literal_with_orig(GArchInstruction *inst /* Transformations et conservation d'une position de symbole */ - if (g_armv7_offset_operand_is_positive(G_ARMV7_OFFSET_OPERAND(op))) - val_offset = phys_pc + offset; - else - val_offset = phys_pc - offset; + val_offset = phys_pc + offset; if (!g_exe_format_translate_offset_into_vmpa(G_EXE_FORMAT(format), val_offset, &sym_addr)) { diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h index 3b14837..c014682 100644 --- a/src/arch/arm/v7/helpers.h +++ b/src/arch/arm/v7/helpers.h @@ -25,18 +25,214 @@ #define _ARCH_ARM_V7_HELPERS_H +#include "cregister.h" #include "pseudo.h" +#include "operands/coproc.h" +#include "operands/estate.h" +#include "operands/limitation.h" #include "operands/maccess.h" #include "operands/offset.h" #include "operands/reglist.h" #include "operands/rotation.h" #include "operands/shift.h" +#include "../register.h" #include "../../operand.h" +#define BarrierLimitation(opt) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_limitation_operand_new(opt); \ + __result; \ + }) + + +#define BitDiff(msb, lsb) \ + ({ \ + GArchOperand *__result; \ + uint32_t __width; \ + __width = g_imm_operand_get_raw_value(G_IMM_OPERAND(msb)); \ + __width -= g_imm_operand_get_raw_value(G_IMM_OPERAND(lsb)); \ + __width += 1; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ + __result; \ + }) + + +#define BuildImm8(val) \ + ({ \ + GArchOperand *__result; \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ + __result; \ + }) + + +#define BuildImm16(val) \ + ({ \ + GArchOperand *__result; \ + __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)val); \ + __result; \ + }) + + +#define CoProcessor(idx) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_coproc_operand_new(idx); \ + __result; \ + }) + + +#define CRegister(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7CRegister *__reg; \ + __reg = g_armv7_cregister_new(idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ + }) + + +#define IncWidth(widthm1) \ + ({ \ + GArchOperand *__result; \ + uint32_t __width; \ + __width = widthm1 + 1; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ + __result; \ + }) + + +#define DecodeImmShift(type, imm5) \ + ({ \ + GArchOperand *__result; \ + SRType __shift_t; \ + uint32_t __shift_n; \ + GArchOperand *__op_n; \ + if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ + __result = NULL; \ + else \ + { \ + __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ + __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ + } \ + __result; \ + }) + + +#define EndianState(big) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_endian_operand_new(big); \ + __result; \ + }) + + +#define MakeMemoryAccess(base, off, shift, index, add, wback) \ + ({ \ + GArchOperand *__result; \ + GArchOperand *__offset; \ + if (off != NULL) \ + __offset = g_armv7_offset_operand_new(add, off); \ + else \ + __offset = NULL; \ + __result = g_armv7_maccess_operand_new(base, __offset, shift, index, wback); \ + __result; \ + }) + + +#define NextRegister(prev) \ + ({ \ + GRegisterOperand *__prev_op; \ + GArchRegister *__reg; \ + uint8_t __id; \ + __prev_op = G_REGISTER_OPERAND(prev); \ + __reg = g_register_operand_get_register(__prev_op); \ + __id = g_arm_register_get_index(G_ARM_REGISTER(__reg)); \ + Register(__id + 1); \ + }) + + +#define RawValue(val) \ + ({ \ + GArchOperand *__result; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, (uint32_t)val); \ + __result; \ + }) + + +#define Register(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__reg; \ + __reg = g_armv7_register_new(idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ + }) + + +#define RegisterShift(shift_t, rs) \ + ({ \ + GArchOperand *__result; \ + GArchOperand *__reg; \ + __reg = Register(rs); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_armv7_shift_operand_new(shift_t, __reg); \ + __result; \ + }) + + +#define Rotation(val5) \ + ({ \ + GArchOperand *__result; \ + uint8_t __rot; \ + GArchOperand *__rot_op; \ + __rot = val5; \ + __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ + __result = g_armv7_rotation_operand_new(__rot_op); \ + if (__result == NULL) \ + g_object_unref(G_OBJECT(__rot_op)); \ + __result; \ + }) + + +#define UInt(val) \ + ({ \ + GArchOperand *__result; \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ + __result; \ + }) + + + + +//#define DecodeImmShift(raw_type, raw_imm5); +//g_armv7_shift_operand_new(SRType type, GArchOperand *value) + + + +//#define MakeMemoryAccess(base, off, shift, index, add, wback) NULL + +//g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool writeb) + +//g_armv7_offset_operand_new(add, off) + + + + +//////////////////// + #define Imm16(imm16) \ ({ \ GArchOperand *__result; \ @@ -105,23 +301,6 @@ __result; \ }) -#define DecodeImmShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - SRType __shift_t; \ - uint32_t __shift_n; \ - GArchOperand *__op_n; \ - if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ - __result = NULL; \ - else \ - { \ - __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ - } \ - __result; \ - }) - - #if 0 // DecodeRegShift() @@ -137,12 +316,12 @@ return shift_t; -#define ZeroExtend(x, n, i) \ +#define ZeroExtend(x, i) \ ({ \ MemoryDataSize __mds; \ uint ## i ## _t __val; \ __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = armv7_zero_extend(x, n, i); \ + __val = armv7_zero_extend(x, 0/**/, i); \ g_imm_operand_new_from_value(__mds, __val); \ }) @@ -180,14 +359,14 @@ return shift_t; #define _MakeMemoryAccess(base, off, wr) \ MakeShiftedMemoryAccess(base, off, NULL, wr) - +/* #define MakeMemoryAccess(base, off, add, wr) \ ({ \ GArchOperand *__off; \ __off = MakeAccessOffset(add, off); \ _MakeMemoryAccess(base, __off, wr); \ }) - +*/ #define MakeMemoryNotIndexed(base, wr) \ _MakeMemoryAccess(base, NULL, wr) @@ -196,19 +375,6 @@ return shift_t; -#define BuildRotation(val5) \ - ({ \ - GArchOperand *__result; \ - uint8_t __rot; \ - GArchOperand *__rot_op; \ - __rot = val5; \ - __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ - __result = g_armv7_rotation_operand_new(__rot_op); \ - if (__result == NULL) \ - g_object_unref(G_OBJECT(__rot_op)); \ - __result; \ - }) - @@ -266,7 +432,7 @@ GArchOperand *sign_extend_armv7_imm(uint32_t, bool, unsigned int); GArchOperand *thumb_expand_armv7_imm(uint32_t); /* Crée un opérande représentant un registre ARMv7. */ -GArchOperand *translate_armv7_register(uint8_t); +//GArchOperand *translate_armv7_register(uint8_t); /* Réalise un simple transtypage de valeur entière. */ GArchOperand *zero_extend_armv7_imm(uint32_t, unsigned int); diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h index c4cf3b2..ec8372a 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h @@ -1,24 +1,7 @@ #ifndef arm_def_tmp_h #define arm_def_tmp_h -#define armv7_read_arm_instr_adc_register_shifted_register(r) NULL -#define armv7_read_arm_instr_add_register_shifted_register(r) NULL -#define armv7_read_arm_instr_and_register_shifted_register(r) NULL -#define armv7_read_arm_instr_asr_register(r) NULL -#define armv7_read_arm_instr_bfc(r) NULL -#define armv7_read_arm_instr_bfi(r) NULL -#define armv7_read_arm_instr_bic_register_shifted_register(r) NULL -#define armv7_read_arm_instr_bkpt(r) NULL -#define armv7_read_arm_instr_bxj(r) NULL -#define armv7_read_arm_instr_cdp_cdp2(r) NULL -#define armv7_read_arm_instr_clrex(r) NULL -#define armv7_read_arm_instr_clz(r) NULL -#define armv7_read_arm_instr_cmn_register_shifted_register(r) NULL -#define armv7_read_arm_instr_cmp_register_shifted_register(r) NULL #define armv7_read_arm_instr_cps_arm(r) NULL -#define armv7_read_arm_instr_dbg(r) NULL #define armv7_read_arm_instr_dmd(r) NULL -#define armv7_read_arm_instr_dsb(r) NULL -#define armv7_read_arm_instr_eor_register_shifted_register(r) NULL #define armv7_read_arm_instr_eret(r) NULL #define armv7_read_arm_instr_hvc(r) NULL #define armv7_read_arm_instr_isb(r) NULL @@ -30,35 +13,7 @@ #define armv7_read_arm_instr_ldmib_ldmed(r) NULL #define armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(r) NULL #define armv7_read_arm_instr_ldm_user_registers(r) NULL -#define armv7_read_arm_instr_ldrb_literal(r) NULL -#define armv7_read_arm_instr_ldrbt(r) NULL -#define armv7_read_arm_instr_ldrd_immediate(r) NULL -#define armv7_read_arm_instr_ldrd_literal(r) NULL -#define armv7_read_arm_instr_ldrd_register(r) NULL -#define armv7_read_arm_instr_ldrex(r) NULL -#define armv7_read_arm_instr_ldrexb(r) NULL -#define armv7_read_arm_instr_ldrexd(r) NULL -#define armv7_read_arm_instr_ldrexh(r) NULL -#define armv7_read_arm_instr_ldrh_immediate_arm(r) NULL -#define armv7_read_arm_instr_ldrh_literal(r) NULL -#define armv7_read_arm_instr_ldrh_register(r) NULL -#define armv7_read_arm_instr_ldrht(r) NULL #define armv7_read_arm_instr_ldr_register(r) NULL -#define armv7_read_arm_instr_ldrsb_immediate(r) NULL -#define armv7_read_arm_instr_ldrsb_literal(r) NULL -#define armv7_read_arm_instr_ldrsb_register(r) NULL -#define armv7_read_arm_instr_ldrsbt(r) NULL -#define armv7_read_arm_instr_ldrsh_immediate(r) NULL -#define armv7_read_arm_instr_ldrsh_literal(r) NULL -#define armv7_read_arm_instr_ldrsh_register(r) NULL -#define armv7_read_arm_instr_ldrsht(r) NULL -#define armv7_read_arm_instr_ldrt(r) NULL -#define armv7_read_arm_instr_lsl_register(r) NULL -#define armv7_read_arm_instr_lsr_register(r) NULL -#define armv7_read_arm_instr_mcr_mcr2(r) NULL -#define armv7_read_arm_instr_mcrr_mcrr2(r) NULL -#define armv7_read_arm_instr_mrc_mrc2(r) NULL -#define armv7_read_arm_instr_mrrc_mrrc2(r) NULL #define armv7_read_arm_instr_mrs(r) NULL #define armv7_read_arm_instr_mrs_banked_register(r) NULL #define armv7_read_arm_instr_msr_banked_register(r) NULL @@ -66,60 +21,17 @@ #define armv7_read_arm_instr_msr_immediate_b9(r) NULL #define armv7_read_arm_instr_msr_register_a8(r) NULL #define armv7_read_arm_instr_msr_register_b9(r) NULL -#define armv7_read_arm_instr_mvn_register_shifted_register(r) NULL -#define armv7_read_arm_instr_orr_register_shifted_register(r) NULL #define armv7_read_arm_instr_pkh(r) NULL #define armv7_read_arm_instr_pld_literal(r) NULL #define armv7_read_arm_instr_pld_pldw_immediate(r) NULL #define armv7_read_arm_instr_pld_pldw_register(r) NULL #define armv7_read_arm_instr_pli_immediate_literal(r) NULL #define armv7_read_arm_instr_pli_register(r) NULL -#define armv7_read_arm_instr_qadd(r) NULL -#define armv7_read_arm_instr_qadd16(r) NULL -#define armv7_read_arm_instr_qadd8(r) NULL -#define armv7_read_arm_instr_qasx(r) NULL -#define armv7_read_arm_instr_qdadd(r) NULL -#define armv7_read_arm_instr_qdsub(r) NULL -#define armv7_read_arm_instr_qsax(r) NULL -#define armv7_read_arm_instr_qsub(r) NULL -#define armv7_read_arm_instr_qsub16(r) NULL -#define armv7_read_arm_instr_qsub8(r) NULL -#define armv7_read_arm_instr_rbit(r) NULL -#define armv7_read_arm_instr_rev(r) NULL -#define armv7_read_arm_instr_rev16(r) NULL -#define armv7_read_arm_instr_revsh(r) NULL #define armv7_read_arm_instr_rfe(r) NULL -#define armv7_read_arm_instr_ror_immediate(r) NULL -#define armv7_read_arm_instr_ror_register(r) NULL -#define armv7_read_arm_instr_rrx(r) NULL -#define armv7_read_arm_instr_rsb_register_shifted_register(r) NULL -#define armv7_read_arm_instr_rsc_register_shifted_register(r) NULL -#define armv7_read_arm_instr_sadd16(r) NULL -#define armv7_read_arm_instr_sadd8(r) NULL -#define armv7_read_arm_instr_sasx(r) NULL -#define armv7_read_arm_instr_sbc_register_shifted_register(r) NULL -#define armv7_read_arm_instr_sbfx(r) NULL -#define armv7_read_arm_instr_sdiv(r) NULL -#define armv7_read_arm_instr_sel(r) NULL -#define armv7_read_arm_instr_sev(r) NULL -#define armv7_read_arm_instr_shadd16(r) NULL -#define armv7_read_arm_instr_shadd8(r) NULL -#define armv7_read_arm_instr_shasx(r) NULL -#define armv7_read_arm_instr_shsax(r) NULL -#define armv7_read_arm_instr_shsub16(r) NULL -#define armv7_read_arm_instr_shsub8(r) NULL #define armv7_read_arm_instr_smc_previously_smi(r) NULL #define armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(r) NULL -#define armv7_read_arm_instr_smlad(r) NULL #define armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL -#define armv7_read_arm_instr_smlald(r) NULL #define armv7_read_arm_instr_smlawb_smlawt(r) NULL -#define armv7_read_arm_instr_smlsd(r) NULL -#define armv7_read_arm_instr_smlsld(r) NULL -#define armv7_read_arm_instr_smmla(r) NULL -#define armv7_read_arm_instr_smmls(r) NULL -#define armv7_read_arm_instr_smmul(r) NULL -#define armv7_read_arm_instr_smuad(r) NULL #define armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(r) NULL #define armv7_read_arm_instr_smulwb_smulwt(r) NULL #define armv7_read_arm_instr_smusd(r) NULL @@ -148,45 +60,11 @@ #define armv7_read_arm_instr_str_register(r) NULL #define armv7_read_arm_instr_strt(r) NULL #define armv7_read_arm_instr_sub_register_shifted_register(r) NULL -#define armv7_read_arm_instr_svc_previously_swi(r) NULL -#define armv7_read_arm_instr_swp_swpb(r) NULL #define armv7_read_arm_instr_sxtab(r) NULL #define armv7_read_arm_instr_sxtab16(r) NULL #define armv7_read_arm_instr_sxtah(r) NULL #define armv7_read_arm_instr_sxtb(r) NULL #define armv7_read_arm_instr_sxtb16(r) NULL #define armv7_read_arm_instr_sxth(r) NULL -#define armv7_read_arm_instr_teq_register_shifted_register(r) NULL -#define armv7_read_arm_instr_tst_register_shifted_register(r) NULL -#define armv7_read_arm_instr_uadd16(r) NULL -#define armv7_read_arm_instr_uadd8(r) NULL -#define armv7_read_arm_instr_uasx(r) NULL -#define armv7_read_arm_instr_ubfx(r) NULL -#define armv7_read_arm_instr_udiv(r) NULL -#define armv7_read_arm_instr_uhadd16(r) NULL -#define armv7_read_arm_instr_uhadd8(r) NULL -#define armv7_read_arm_instr_uhasx(r) NULL -#define armv7_read_arm_instr_uhsax(r) NULL -#define armv7_read_arm_instr_uhsub16(r) NULL -#define armv7_read_arm_instr_uhsub8(r) NULL -#define armv7_read_arm_instr_uqadd16(r) NULL -#define armv7_read_arm_instr_uqadd8(r) NULL -#define armv7_read_arm_instr_uqasx(r) NULL -#define armv7_read_arm_instr_uqsax(r) NULL -#define armv7_read_arm_instr_uqsub16(r) NULL -#define armv7_read_arm_instr_uqsub8(r) NULL -#define armv7_read_arm_instr_usad8(r) NULL -#define armv7_read_arm_instr_usada8(r) NULL -#define armv7_read_arm_instr_usat(r) NULL -#define armv7_read_arm_instr_usat16(r) NULL -#define armv7_read_arm_instr_usax(r) NULL -#define armv7_read_arm_instr_usub16(r) NULL -#define armv7_read_arm_instr_usub8(r) NULL -#define armv7_read_arm_instr_uxtab(r) NULL -#define armv7_read_arm_instr_uxtab16(r) NULL -#define armv7_read_arm_instr_uxtah(r) NULL -#define armv7_read_arm_instr_uxtb16(r) NULL -#define armv7_read_arm_instr_uxth(r) NULL #define armv7_read_arm_instr_wfe(r) NULL -#define armv7_read_arm_instr_wfi(r) NULL #endif diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h index 8e8572d..1a62c43 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h @@ -1,31 +1,13 @@ #ifndef thumb_16_def_tmp_h #define thumb_16_def_tmp_h -#define armv7_read_thumb_16_instr_asr_register(r) NULL -#define armv7_read_thumb_16_instr_bkpt(r) NULL #define armv7_read_thumb_16_instr_cps_thumb(r) NULL #define armv7_read_thumb_16_instr_it(r) NULL #define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_16_instr_ldrh_immediate_thumb(r) NULL -#define armv7_read_thumb_16_instr_ldrh_register(r) NULL -#define armv7_read_thumb_16_instr_ldrsb_register(r) NULL -#define armv7_read_thumb_16_instr_ldrsh_register(r) NULL -#define armv7_read_thumb_16_instr_lsl_register(r) NULL -#define armv7_read_thumb_16_instr_lsr_register(r) NULL -#define armv7_read_thumb_16_instr_rev(r) NULL -#define armv7_read_thumb_16_instr_rev16(r) NULL -#define armv7_read_thumb_16_instr_revsh(r) NULL -#define armv7_read_thumb_16_instr_ror_register(r) NULL -#define armv7_read_thumb_16_instr_setend(r) NULL -#define armv7_read_thumb_16_instr_sev(r) NULL #define armv7_read_thumb_16_instr_stm_stmia_stmea(r) NULL #define armv7_read_thumb_16_instr_strh_immediate_thumb(r) NULL #define armv7_read_thumb_16_instr_strh_register(r) NULL #define armv7_read_thumb_16_instr_str_register(r) NULL -#define armv7_read_thumb_16_instr_svc_previously_swi(r) NULL #define armv7_read_thumb_16_instr_sxtb(r) NULL #define armv7_read_thumb_16_instr_sxth(r) NULL -#define armv7_read_thumb_16_instr_udf(r) NULL -#define armv7_read_thumb_16_instr_uxth(r) NULL #define armv7_read_thumb_16_instr_wfe(r) NULL -#define armv7_read_thumb_16_instr_wfi(r) NULL #endif diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h index 1970369..c74ab49 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -1,18 +1,8 @@ #ifndef thumb_32_def_tmp_h #define thumb_32_def_tmp_h -#define armv7_read_thumb_32_instr_asr_register(r) NULL -#define armv7_read_thumb_32_instr_bfc(r) NULL -#define armv7_read_thumb_32_instr_bfi(r) NULL #define armv7_read_thumb_32_instr_b_mrs(r) NULL #define armv7_read_thumb_32_instr_b_msr_register(r) NULL -#define armv7_read_thumb_32_instr_bxj(r) NULL -#define armv7_read_thumb_32_instr_cdp_cdp2(r) NULL -#define armv7_read_thumb_32_instr_clrex(r) NULL -#define armv7_read_thumb_32_instr_clz(r) NULL #define armv7_read_thumb_32_instr_cps_thumb(r) NULL -#define armv7_read_thumb_32_instr_dbg(r) NULL -#define armv7_read_thumb_32_instr_dmb(r) NULL -#define armv7_read_thumb_32_instr_dsb(r) NULL #define armv7_read_thumb_32_instr_enterx_leavex(r) NULL #define armv7_read_thumb_32_instr_eret(r) NULL #define armv7_read_thumb_32_instr_hvc(r) NULL @@ -21,39 +11,10 @@ #define armv7_read_thumb_32_instr_ldc_ldc2_literal(r) NULL #define armv7_read_thumb_32_instr_ldmdb_ldmea(r) NULL #define armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_32_instr_ldrb_literal(r) NULL -#define armv7_read_thumb_32_instr_ldrbt(r) NULL -#define armv7_read_thumb_32_instr_ldrd_immediate(r) NULL -#define armv7_read_thumb_32_instr_ldrd_literal(r) NULL -#define armv7_read_thumb_32_instr_ldrex(r) NULL -#define armv7_read_thumb_32_instr_ldrexb(r) NULL -#define armv7_read_thumb_32_instr_ldrexd(r) NULL -#define armv7_read_thumb_32_instr_ldrexh(r) NULL -#define armv7_read_thumb_32_instr_ldrh_immediate_thumb(r) NULL -#define armv7_read_thumb_32_instr_ldrh_literal(r) NULL -#define armv7_read_thumb_32_instr_ldrh_register(r) NULL -#define armv7_read_thumb_32_instr_ldrht(r) NULL -#define armv7_read_thumb_32_instr_ldrsb_immediate(r) NULL -#define armv7_read_thumb_32_instr_ldrsb_literal(r) NULL -#define armv7_read_thumb_32_instr_ldrsb_register(r) NULL -#define armv7_read_thumb_32_instr_ldrsbt(r) NULL -#define armv7_read_thumb_32_instr_ldrsh_immediate(r) NULL -#define armv7_read_thumb_32_instr_ldrsh_literal(r) NULL -#define armv7_read_thumb_32_instr_ldrsh_register(r) NULL -#define armv7_read_thumb_32_instr_ldrsht(r) NULL -#define armv7_read_thumb_32_instr_ldrt(r) NULL -#define armv7_read_thumb_32_instr_lsl_register(r) NULL -#define armv7_read_thumb_32_instr_lsr_register(r) NULL -#define armv7_read_thumb_32_instr_mcr_mcr2(r) NULL -#define armv7_read_thumb_32_instr_mcrr_mcrr2(r) NULL -#define armv7_read_thumb_32_instr_mrc_mrc2(r) NULL -#define armv7_read_thumb_32_instr_mrrc_mrrc2(r) NULL #define armv7_read_thumb_32_instr_mrs(r) NULL #define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL #define armv7_read_thumb_32_instr_msr_banked_register(r) NULL #define armv7_read_thumb_32_instr_msr_register(r) NULL -#define armv7_read_thumb_32_instr_orn_immediate(r) NULL -#define armv7_read_thumb_32_instr_orn_register(r) NULL #define armv7_read_thumb_32_instr_pkh(r) NULL #define armv7_read_thumb_32_instr_pld_immediate(r) NULL #define armv7_read_thumb_32_instr_pld_literal(r) NULL @@ -62,43 +23,11 @@ #define armv7_read_thumb_32_instr_pld_register(r) NULL #define armv7_read_thumb_32_instr_pli_immediate_literal(r) NULL #define armv7_read_thumb_32_instr_pli_register(r) NULL -#define armv7_read_thumb_32_instr_qadd(r) NULL -#define armv7_read_thumb_32_instr_qdadd(r) NULL -#define armv7_read_thumb_32_instr_qdsub(r) NULL -#define armv7_read_thumb_32_instr_qsub(r) NULL -#define armv7_read_thumb_32_instr_rbit(r) NULL -#define armv7_read_thumb_32_instr_rev(r) NULL -#define armv7_read_thumb_32_instr_rev16(r) NULL -#define armv7_read_thumb_32_instr_revsh(r) NULL #define armv7_read_thumb_32_instr_rfe(r) NULL -#define armv7_read_thumb_32_instr_ror_immediate(r) NULL -#define armv7_read_thumb_32_instr_ror_register(r) NULL -#define armv7_read_thumb_32_instr_rrx(r) NULL -#define armv7_read_thumb_32_instr_sadd16(r) NULL -#define armv7_read_thumb_32_instr_sadd8(r) NULL -#define armv7_read_thumb_32_instr_sasx(r) NULL -#define armv7_read_thumb_32_instr_sbfx(r) NULL -#define armv7_read_thumb_32_instr_sdiv(r) NULL -#define armv7_read_thumb_32_instr_sel(r) NULL -#define armv7_read_thumb_32_instr_sev(r) NULL -#define armv7_read_thumb_32_instr_shadd16(r) NULL -#define armv7_read_thumb_32_instr_shadd8(r) NULL -#define armv7_read_thumb_32_instr_shasx(r) NULL -#define armv7_read_thumb_32_instr_shsax(r) NULL -#define armv7_read_thumb_32_instr_shsub16(r) NULL -#define armv7_read_thumb_32_instr_shsub8(r) NULL #define armv7_read_thumb_32_instr_smc_previously_smi(r) NULL #define armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(r) NULL -#define armv7_read_thumb_32_instr_smlad(r) NULL #define armv7_read_thumb_32_instr_smlalbb_smlalbt_smlaltb_smlaltt(r) NULL -#define armv7_read_thumb_32_instr_smlald(r) NULL #define armv7_read_thumb_32_instr_smlawb_smlawt(r) NULL -#define armv7_read_thumb_32_instr_smlsd(r) NULL -#define armv7_read_thumb_32_instr_smlsld(r) NULL -#define armv7_read_thumb_32_instr_smmla(r) NULL -#define armv7_read_thumb_32_instr_smmls(r) NULL -#define armv7_read_thumb_32_instr_smmul(r) NULL -#define armv7_read_thumb_32_instr_smuad(r) NULL #define armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(r) NULL #define armv7_read_thumb_32_instr_smulwb_smulwt(r) NULL #define armv7_read_thumb_32_instr_smusd(r) NULL @@ -137,36 +66,5 @@ #define armv7_read_thumb_32_instr_sxtb16(r) NULL #define armv7_read_thumb_32_instr_sxth(r) NULL #define armv7_read_thumb_32_instr_tbb_tbh(r) NULL -#define armv7_read_thumb_32_instr_uadd16(r) NULL -#define armv7_read_thumb_32_instr_uadd8(r) NULL -#define armv7_read_thumb_32_instr_uasx(r) NULL -#define armv7_read_thumb_32_instr_ubfx(r) NULL -#define armv7_read_thumb_32_instr_udf(r) NULL -#define armv7_read_thumb_32_instr_udiv(r) NULL -#define armv7_read_thumb_32_instr_uhadd16(r) NULL -#define armv7_read_thumb_32_instr_uhadd8(r) NULL -#define armv7_read_thumb_32_instr_uhasx(r) NULL -#define armv7_read_thumb_32_instr_uhsax(r) NULL -#define armv7_read_thumb_32_instr_uhsub16(r) NULL -#define armv7_read_thumb_32_instr_uhsub8(r) NULL -#define armv7_read_thumb_32_instr_uqadd16(r) NULL -#define armv7_read_thumb_32_instr_uqadd8(r) NULL -#define armv7_read_thumb_32_instr_uqasx(r) NULL -#define armv7_read_thumb_32_instr_uqsax(r) NULL -#define armv7_read_thumb_32_instr_uqsub16(r) NULL -#define armv7_read_thumb_32_instr_uqsub8(r) NULL -#define armv7_read_thumb_32_instr_usad8(r) NULL -#define armv7_read_thumb_32_instr_usada8(r) NULL -#define armv7_read_thumb_32_instr_usat(r) NULL -#define armv7_read_thumb_32_instr_usat16(r) NULL -#define armv7_read_thumb_32_instr_usax(r) NULL -#define armv7_read_thumb_32_instr_usub16(r) NULL -#define armv7_read_thumb_32_instr_usub8(r) NULL -#define armv7_read_thumb_32_instr_uxtab(r) NULL -#define armv7_read_thumb_32_instr_uxtab16(r) NULL -#define armv7_read_thumb_32_instr_uxtah(r) NULL -#define armv7_read_thumb_32_instr_uxtb16(r) NULL -#define armv7_read_thumb_32_instr_uxth(r) NULL #define armv7_read_thumb_32_instr_wfe(r) NULL -#define armv7_read_thumb_32_instr_wfi(r) NULL #endif diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am index 607b27f..578e4a5 100644 --- a/src/arch/arm/v7/opdefs/Makefile.am +++ b/src/arch/arm/v7/opdefs/Makefile.am @@ -20,11 +20,22 @@ D2C_ENCODINGS = \ D2C_MACROS = \ -M SetFlags=g_armv7_instruction_define_setflags \ -M Condition=g_arm_instruction_set_cond \ - -M Register=translate_armv7_register \ -M "ExpandImmC32=g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, " \ -M SignExtend=sign_extend_armv7_imm \ - -M SetInsFlag=g_arch_instruction_set_flag + -M SetInsFlag=g_arch_instruction_set_flag \ + -M StoreCondition=g_arm_instruction_set_cond \ + -M ExtendKeyword=g_arch_instruction_extend_keyword +D2C_OPERANDS = \ + -n BarrierLimitation \ + -n BitDiff \ + -n IncWidth \ + -n DecodeImmShift \ + -n MakeMemoryAccess \ + -n Register \ + -n RegisterShift \ + -n UInt \ + -n ZeroExtend FIXED_C_INCLUDES = \ \n\#include \"..\/helpers.h\" \ @@ -44,62 +55,159 @@ FIXED_H_INCLUDES = \ \n\n +# for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done ARMV7_DEFS = \ adc_A881.d \ adc_A882.d \ + adc_A883.d \ add_A884.d \ add_A885.d \ add_A886.d \ add_A887.d \ + add_A888.d \ add_A889.d \ + add_A8810.d \ + add_A8811.d \ adr_A8812.d \ and_A8813.d \ and_A8814.d \ + and_A8815.d \ asr_A8816.d \ + asr_A8817.d \ b_A8818.d \ + bfc_A8819.d \ + bfi_A8820.d \ bic_A8821.d \ bic_A8822.d \ + bic_A8823.d \ + bkpt_A8824.d \ bl_A8825.d \ blx_A8826.d \ bx_A8827.d \ - cbnz_A8829.d \ + bxj_A8828.d \ + cb_A8829.d \ + cdp_A8830.d \ + clrex_A8832.d \ + clz_A8833.d \ cmn_A8834.d \ cmn_A8835.d \ + cmn_A8836.d \ cmp_A8837.d \ cmp_A8838.d \ + cmp_A8839.d \ + dbg_A8842.d \ + dmb_A8843.d \ + dsb_A8844.d \ eor_A8846.d \ eor_A8847.d \ + eor_A8848.d \ ldr_A8862.d \ ldr_A8863.d \ ldr_A8864.d \ ldr_A8865.d \ + ldr_A8866.d \ ldrb_A8867.d \ ldrb_A8868.d \ + ldrb_A8869.d \ ldrb_A8870.d \ + ldrbt_A8871.d \ + ldrd_A8872.d \ + ldrd_A8873.d \ + ldrd_A8874.d \ + ldrex_A8875.d \ + ldrexb_A8876.d \ + ldrexd_A8877.d \ + ldrexh_A8878.d \ + ldrh_A8879.d \ + ldrh_A8880.d \ + ldrh_A8881.d \ + ldrh_A8882.d \ + ldrht_A8883.d \ + ldrsb_A8884.d \ + ldrsb_A8885.d \ + ldrsb_A8886.d \ + ldrsbt_A8887.d \ + ldrsh_A8888.d \ + ldrsh_A8889.d \ + ldrsh_A8890.d \ + ldrsht_A8891.d \ + ldrt_A8892.d \ lsl_A8894.d \ + lsl_A8895.d \ lsr_A8896.d \ + lsr_A8897.d \ + mcr_A8898.d \ + mcrr_A8899.d \ mla_A88100.d \ mls_A88101.d \ mov_A88102.d \ mov_A88103.d \ mov_A88104.d \ movt_A88106.d \ + mrc_A88107.d \ + mrrc_A88108.d \ mul_A88114.d \ mvn_A88115.d \ mvn_A88116.d \ + mvn_A88117.d \ nop_A88119.d \ + orn_A88120.d \ + orn_A88121.d \ orr_A88122.d \ orr_A88123.d \ + orr_A88124.d \ pop_A88131.d \ pop_A88132.d \ push_A88133.d \ + qadd_A88134.d \ + qadd16_A88135.d \ + qadd8_A88136.d \ + qasx_A88137.d \ + qdadd_A88138.d \ + qdsub_A88139.d \ + qsax_A88140.d \ + qsub_A88141.d \ + qsub16_A88142.d \ + qsub8_A88143.d \ + rbit_A88144.d \ + rev_A88145.d \ + rev16_A88146.d \ + revsh_A88147.d \ + ror_A88149.d \ + ror_A88150.d \ + rrx_A88151.d \ rsb_A88152.d \ rsb_A88153.d \ + rsb_A88154.d \ rsc_A88155.d \ rsc_A88156.d \ + rsc_A88157.d \ + sadd16_A88158.d \ + sadd8_A88159.d \ + sasx_A88160.d \ sbc_A88161.d \ sbc_A88162.d \ + sbc_A88163.d \ + sbfx_A88164.d \ + sdiv_A88165.d \ + sel_A88166.d \ + setend_A88167.d \ + sev_A88168.d \ + shadd16_A88169.d \ + shadd8_A88170.d \ + shasx_A88171.d \ + shsax_A88172.d \ + shsub16_A88173.d \ + shsub8_A88174.d \ + smlad_A88177.d \ smlal_A88178.d \ + smlald_A88180.d \ + smlsd_A88182.d \ + smlsld_A88183.d \ + smmla_A88184.d \ + smmls_A88185.d \ + smmul_A88186.d \ + smuad_A88187.d \ smull_A88189.d \ str_A88203.d \ str_A88204.d \ @@ -110,16 +218,52 @@ ARMV7_DEFS = \ sub_A88222.d \ sub_A88223.d \ sub_A88225.d \ + svc_A88228.d \ + swp_A88229.d \ teq_A88237.d \ teq_A88238.d \ + teq_A88239.d \ tst_A88240.d \ tst_A88241.d \ + tst_A88242.d \ + uadd16_A88243.d \ + uadd8_A88244.d \ + uasx_A88245.d \ + ubfx_A88246.d \ + udf_A88247.d \ + udiv_A88248.d \ + uhadd16_A88249.d \ + uhadd8_A88250.d \ + uhasx_A88251.d \ + uhsax_A88252.d \ + uhsub16_A88253.d \ + uhsub8_A88254.d \ umaal_A88255.d \ umlal_A88256.d \ umull_A88257.d \ + uqadd16_A88258.d \ + uqadd8_A88259.d \ + uqasx_A88260.d \ + uqsax_A88261.d \ + uqsub16_A88262.d \ + uqsub8_A88263.d \ + usad8_A88264.d \ + usada8_A88265.d \ + usat_A88266.d \ + usat16_A88267.d \ + usax_A88268.d \ + usub16_A88269.d \ + usub8_A88270.d \ + uxtab_A88271.d \ + uxtab16_A88272.d \ + uxtah_A88273.d \ uxtb_A88274.d \ - yield_A88426.d \ - subs_B9320.d + uxtb16_A88275.d \ + uxth_A88276.d \ + wfi_A88425.d \ + yield_A88426.d + +# subs_B9320.d all: $(ARMV7_DEFS:.d=.g) fmk.done d2c_final_rules diff --git a/src/arch/arm/v7/opdefs/adc_A881.d b/src/arch/arm/v7/opdefs/adc_A881.d index ff37ea0..6bc66e2 100644 --- a/src/arch/arm/v7/opdefs/adc_A881.d +++ b/src/arch/arm/v7/opdefs/adc_A881.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,49 +23,52 @@ @title ADC (immediate) -@encoding(T1) { +@desc Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) +@encoding (T1) { - @syntax {S} + @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @conv { + @syntax - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - const = ThumbExpandImm(i:imm3:imm8) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) - @rules { + } - //if ((d IN {13,15}) || (n IN {13,15})) ; unpredictable + @rules { - } + if (setflags); chk_call ExtendKeyword("s") + + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) + @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax {S} {c} + @syntax - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - const = ARMExpandImm(imm12) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/adc_A882.d b/src/arch/arm/v7/opdefs/adc_A882.d index a43cadb..27ce6ad 100644 --- a/src/arch/arm/v7/opdefs/adc_A882.d +++ b/src/arch/arm/v7/opdefs/adc_A882.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,66 +23,70 @@ @title ADC (register) -@encoding(t1) { +@desc Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) +@encoding (t1) { - @syntax + @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) - @conv { + @syntax "adcs" - Rdn = Register(Rdn) - Rm = Register(Rm) + @conv { - } + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax {S} + @syntax - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) - } + } - @rules { + @rules { - //if d IN {13,15} || n IN {13,15} || m IN {13,15} then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax {S} {c} + @syntax - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/adc_A883.d b/src/arch/arm/v7/opdefs/adc_A883.d new file mode 100644 index 0000000..a9c56d8 --- /dev/null +++ b/src/arch/arm/v7/opdefs/adc_A883.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title ADC (register-shifted register) + +@desc Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/add_A8810.d b/src/arch/arm/v7/opdefs/add_A8810.d new file mode 100644 index 0000000..2047276 --- /dev/null +++ b/src/arch/arm/v7/opdefs/add_A8810.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title ADD (SP plus register, Thumb) + +@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +@encoding (t1) { + + @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) + + @syntax + + @conv { + + reg_DM_1 = Register(DM:Rdm) + reg_DM_2 = Register(DM:Rdm) + SP = Register(13) + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 + + @syntax + + @conv { + + reg_M = Register(Rm) + SP = Register(13) + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + diff --git a/src/arch/arm/v7/opdefs/add_A8811.d b/src/arch/arm/v7/opdefs/add_A8811.d new file mode 100644 index 0000000..5b6c0d1 --- /dev/null +++ b/src/arch/arm/v7/opdefs/add_A8811.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title ADD (SP plus register, ARM) + +@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/add_A884.d b/src/arch/arm/v7/opdefs/add_A884.d index fb79567..8b624a7 100644 --- a/src/arch/arm/v7/opdefs/add_A884.d +++ b/src/arch/arm/v7/opdefs/add_A884.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,95 +23,76 @@ @title ADD (immediate, Thumb) -@encoding(t1) { +@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) +@encoding (t1) { - @syntax + @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) - @conv { + @syntax "adds" - Rd = Register(Rd) - Rn = Register(Rn) - const = ZeroExtend(imm3, 3, 32); + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @rules { - - //setflags = !InITBlock(); - - } + } } -@encoding(t2) { - - @half 0 0 1 1 0 Rdn(3) imm8(8) - - @syntax - - @conv { +@encoding (t2) { - Rdn = Register(Rdn) - const = ZeroExtend(imm8, 8, 32); + @half 0 0 1 1 0 Rdn(3) imm8(8) - } + @syntax "adds" - @rules { + @conv { - //setflags = !InITBlock(); + reg_DN = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) - } + } } -@encoding(T3) { +@encoding (T3) { - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax {S} ".W" + @syntax - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, i) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE CMN (immediate); - //if Rn == '1101' then SEE ADD (SP plus immediate); - //if d == 13 || (d == 15 && S == '0') || n == 15 then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(T4) { +@encoding (T4) { - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" + @syntax "addw" - @conv { + @conv { - Rd = Register(Rd) - Rn = Register(Rn) - const = ZeroExtend(i:imm3:imm8, 12, 32) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - } - - @rules { - - //if Rn == '1111' then SEE ADR; - //if Rn == '1101' then SEE ADD (SP plus immediate); - //setflags = FALSE - //if d IN {13,15} then UNPREDICTABLE; - - } + } } + diff --git a/src/arch/arm/v7/opdefs/add_A885.d b/src/arch/arm/v7/opdefs/add_A885.d index d3220c5..0f4a919 100644 --- a/src/arch/arm/v7/opdefs/add_A885.d +++ b/src/arch/arm/v7/opdefs/add_A885.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,29 @@ @title ADD (immediate, ARM) -@encoding(A1) { +@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) +@encoding (A1) { - @syntax {S} {c} + @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - @conv { + @syntax - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - const = ARMExpandImm(imm12) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) - @rules { + } - //if ((Rn == '1111') && (S == '0')) ; see ADR - //if (Rn == '1101') ; see ADD (SP plus immediate) - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + @rules { - } + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } } + diff --git a/src/arch/arm/v7/opdefs/add_A886.d b/src/arch/arm/v7/opdefs/add_A886.d index fd8f7a4..e4f9e00 100644 --- a/src/arch/arm/v7/opdefs/add_A886.d +++ b/src/arch/arm/v7/opdefs/add_A886.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,68 +23,61 @@ @title ADD (register, Thumb) -@encoding(t1) { +@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) +@encoding (t1) { - @syntax + @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) - @conv { + @syntax "adds" - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) -} - -@encoding(t2) { - - @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) + } - @syntax +} - @conv { +@encoding (t2) { - Rdn = Register(DN:Rdn) - Rm = Register(Rm) + @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) - } + @syntax - @rules { + @conv { - //if (DN:Rdn) == '1101' || Rm == '1101' then SEE ADD (SP plus register); - //if n == 15 && m == 15 then UNPREDICTABLE; - //if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE; + reg_DN = Register(DN:Rdn) + reg_M = Register(Rm) - } + } } -@encoding(T3) { - - @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) +@encoding (T3) { - @syntax {S} ".W" + @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @conv { + @syntax - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) - @rules { + } - //if Rd == '1111' && S == '1' then SEE CMN (register); - //if Rn == '1101' then SEE ADD (SP plus register); - //if d == 13 || (d == 15 && S == '0') || n == 15 || m IN {13,15} then UNPREDICTABLE; + @rules { + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } + diff --git a/src/arch/arm/v7/opdefs/add_A887.d b/src/arch/arm/v7/opdefs/add_A887.d index 17bbe7f..18400a6 100644 --- a/src/arch/arm/v7/opdefs/add_A887.d +++ b/src/arch/arm/v7/opdefs/add_A887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,30 @@ @title ADD (register, ARM) -@encoding(A1) { +@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) +@encoding (A1) { - @syntax {S} {c} + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @conv { + @syntax - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) - @rules { + } - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions - //if Rn == '1101' then SEE ADD (SP plus register); + @rules { - } + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } } + diff --git a/src/arch/arm/v7/opdefs/add_A888.d b/src/arch/arm/v7/opdefs/add_A888.d new file mode 100644 index 0000000..5549145 --- /dev/null +++ b/src/arch/arm/v7/opdefs/add_A888.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title ADD (register-shifted register) + +@desc Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/add_A889.d b/src/arch/arm/v7/opdefs/add_A889.d index 3c9d432..5fab17c 100644 --- a/src/arch/arm/v7/opdefs/add_A889.d +++ b/src/arch/arm/v7/opdefs/add_A889.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,117 +23,101 @@ @title ADD (SP plus immediate) -@encoding(t1) { +@desc This instruction adds an immediate value to the SP value, and writes the result to the destination register. - @half 1 0 1 0 1 Rd(3) imm8(8) +@encoding (t1) { - @syntax + @half 1 0 1 0 1 Rd(3) imm8(8) - @conv { + @syntax - Rd = Register(Rd) - SP = Register(13) - const = ZeroExtend(imm8:'00', 10, 32); + @conv { - } + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + SP = Register(13) - @rules { - - //setflags = FALSE - - } + } } -@encoding(t2) { - - @half 1 0 1 1 0 0 0 0 0 imm7(7) - - @syntax - - @conv { +@encoding (t2) { - SP1 = Register(13) - SP2 = Register(13) - const = ZeroExtend(imm7:'00', 9, 32); + @half 1 0 1 1 0 0 0 0 0 imm7(7) - } + @syntax - @rules { + @conv { - //setflags = FALSE + imm32 = ZeroExtend(imm7:'00', 32) + SP_0 = Register(13) + SP_1 = Register(13) - } + } } -@encoding(T3) { +@encoding (T3) { - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax {S} ".W" + @syntax - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - SP = Register(13) - const = ThumbExpandImm_C(i:imm3:imm8, i) + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + SP = Register(13) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE CMN (immediate); - //if d == 15 && S == '0' then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(T4) { +@encoding (T4) { - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" + @syntax "addw" - @conv { + @conv { - Rd = Register(Rd) - SP = Register(13) - const = ZeroExtend(i:imm3:imm8, 12, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + SP = Register(13) - } - - @rules { - - //if Rd == '1111' && S == '1' then SEE CMN (immediate); - //if d == 15 && S == '0' then UNPREDICTABLE; - - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) + @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax {S} {c} + @syntax - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - SP = Register(13) - const = ARMExpandImm(imm12) + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + SP = Register(13) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/adr_A8812.d b/src/arch/arm/v7/opdefs/adr_A8812.d index 38ad6af..16615cb 100644 --- a/src/arch/arm/v7/opdefs/adr_A8812.d +++ b/src/arch/arm/v7/opdefs/adr_A8812.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,94 +23,92 @@ @title ADR -@encoding(t1) { +@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. - @half 1 0 1 0 0 Rd(3) imm8(8) +@encoding (t1) { - @syntax "add" + @half 1 0 1 0 0 Rd(3) imm8(8) - @conv { + @syntax - Rd = Register(Rd) - PC = Register(15) - imm32 = ZeroExtend(imm8:'00', 10, 32) + @conv { - } + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax "sub" + @syntax ".W" - @conv { + @conv { - Rd = Register(Rd) - PC = Register(15) - imm32 = ZeroExtend(i:imm3:imm8, 12, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - } + } - @rules { +} - //if d IN {13,15} then UNPREDICTABLE; +@encoding (T3) { - } + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) -} + @syntax ".W" -@encoding(T3) { + @conv { - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @syntax "add" + } - @conv { +} - Rd = Register(Rd) - PC = Register(15) - imm32 = ZeroExtend(i:imm3:imm8, 12, 32) +@encoding (A1) { - } + @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - @rules { + @syntax - //if d IN {13,15} then UNPREDICTABLE; + @conv { - } + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) -} + } -@encoding(A1) { + @rules { - @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) + chk_call StoreCondition(cond) - @syntax "add" + } - @conv { +} - Rd = Register(Rd) - PC = Register(15) - const = ARMExpandImm(imm12) +@encoding (A2) { - } + @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) -} + @syntax -@encoding(A2) { + @conv { - @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - @syntax "sub" + } - @conv { + @rules { - Rd = Register(Rd) - PC = Register(15) - const = ARMExpandImm(imm12) + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/and_A8813.d b/src/arch/arm/v7/opdefs/and_A8813.d index f0a1740..3e1d0ed 100644 --- a/src/arch/arm/v7/opdefs/and_A8813.d +++ b/src/arch/arm/v7/opdefs/and_A8813.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,50 +23,52 @@ @title AND (immediate) -@encoding(T1) { +@desc This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. - @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) +@encoding (T1) { - @syntax {S} + @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @conv { + @syntax - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, 0) + @conv { - } + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) - @rules { + } - //if ((Rd == '1111') && (S == '1')) ; see TST (immediate) - //if ((d == 13) || ((d == 15) && (S == '0')) || (n IN {13,15})) ; unpredictable + @rules { - } + if (setflags); chk_call ExtendKeyword("s") + + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) + @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax {S} {c} + @syntax - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - const = ARMExpandImm_C(imm12, 0) + reg_D = Register(Rd) + reg_N = Register(Rn) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/and_A8814.d b/src/arch/arm/v7/opdefs/and_A8814.d index 10593a0..77f7e55 100644 --- a/src/arch/arm/v7/opdefs/and_A8814.d +++ b/src/arch/arm/v7/opdefs/and_A8814.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,67 +23,70 @@ @title AND (register) -@encoding(t1) { +@desc This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) +@encoding (t1) { - @syntax + @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) - @conv { + @syntax "ands" - Rdn = Register(Rdn) - Rm = Register(Rm) + @conv { - } + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax {S} + @syntax - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm3:imm2) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see TST (register) - //if ((d == 13) || ((d == 15) && (S == '0')) || (n IN {13,15})) ; unpredictable + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax {S} {c} + @syntax - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rn = Register(Rn) - Rm = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + shift = DecodeImmShift(type, imm5) - } + } - @rules { + @rules { - //if ((Rd == '1111') && (S == '1')) ; see SUBS PC, LR and related instructions + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/and_A8815.d b/src/arch/arm/v7/opdefs/and_A8815.d new file mode 100644 index 0000000..5ace3fa --- /dev/null +++ b/src/arch/arm/v7/opdefs/and_A8815.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title AND (register-shifted register) + +@desc This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax + + @conv { + + reg_shift = RegisterShift(type, Rs) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/asr_A8816.d b/src/arch/arm/v7/opdefs/asr_A8816.d index 7c1fda6..006a26c 100644 --- a/src/arch/arm/v7/opdefs/asr_A8816.d +++ b/src/arch/arm/v7/opdefs/asr_A8816.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,71 +23,69 @@ @title ASR (immediate) -@encoding(t1) { +@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. - @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) +@encoding (t1) { - @syntax <#imm> + @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) - @conv { + @syntax "asrs" - Rd = Register(Rd) - Rm = Register(Rm) - imm = FixedShift(2, imm5) + @conv { - } + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_imm = DecodeImmShift('10', imm5) - @rules { - - //setflags = !InITBlock(); - - } + } } -@encoding(T2) { +@encoding (T2) { - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) - @syntax {S} ".W" <#imm> + @syntax - @conv { + @conv { - S = SetFlags(S) - Rd = Register(Rd) - Rm = Register(Rm) - imm = FixedShift(2, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('10', imm3:imm2) - } + } - @rules { + @rules { - //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE; + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") - } + } } -@encoding(A1) { +@encoding (A1) { - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) - @syntax {S} {c} <#imm> + @syntax - @conv { + @conv { - S = SetFlags(S) - c = Condition(cond) - Rd = Register(Rd) - Rm = Register(Rm) - imm = FixedShift(2, imm5) + reg_D = Register(Rd) + reg_M = Register(Rm) + setflags = (S == '1') + shift_imm = DecodeImmShift('10', imm5) - } + } - @rules { + @rules { - //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions; + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) - } + } } + diff --git a/src/arch/arm/v7/opdefs/asr_A8817.d b/src/arch/arm/v7/opdefs/asr_A8817.d new file mode 100644 index 0000000..1e1e9c1 --- /dev/null +++ b/src/arch/arm/v7/opdefs/asr_A8817.d @@ -0,0 +1,90 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title ASR (register) + +@desc Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) + + @syntax "asrs" + + @conv { + + reg_DN = Register(Rdn) + reg_M = Register(Rm) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) + + @syntax + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + setflags = (S == '1') + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/b_A8818.d b/src/arch/arm/v7/opdefs/b_A8818.d index 55b123e..9e27753 100644 --- a/src/arch/arm/v7/opdefs/b_A8818.d +++ b/src/arch/arm/v7/opdefs/b_A8818.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,153 +23,135 @@ @title B -@encoding(t1) { +@desc Branch causes a branch to a target address. - @half 1 1 0 1 cond(4) imm8(8) +@encoding (t1) { - @syntax {c}