From 5311a943dffcc410739509b9215ca464f6d1e54c Mon Sep 17 00:00:00 2001 From: Cyrille Bagard Date: Mon, 28 May 2018 22:34:24 +0200 Subject: Included support for ARMv7 system instructions. --- plugins/arm/v7/arm.c | 544 +++++++++++++------------- plugins/arm/v7/core.c | 2 + plugins/arm/v7/helpers.h | 64 +++ plugins/arm/v7/opcodes/opcodes_tmp_arm.h | 19 +- plugins/arm/v7/opcodes/opcodes_tmp_simd.h | 270 ++++++------- plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h | 1 - plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h | 37 +- plugins/arm/v7/opdefs/A88100_mla.d | 120 ++++++ plugins/arm/v7/opdefs/A88101_mls.d | 85 ++++ plugins/arm/v7/opdefs/A88102_mov.d | 210 ++++++++++ plugins/arm/v7/opdefs/A88103_mov.d | 123 ++++++ plugins/arm/v7/opdefs/A88104_mov.d | 93 +++++ plugins/arm/v7/opdefs/A88106_movt.d | 81 ++++ plugins/arm/v7/opdefs/A88107_mrc.d | 133 +++++++ plugins/arm/v7/opdefs/A88108_mrrc.d | 129 ++++++ plugins/arm/v7/opdefs/A88109_mrs.d | 81 ++++ plugins/arm/v7/opdefs/A8810_add.d | 129 ++++++ plugins/arm/v7/opdefs/A88111_msr.d | 60 +++ plugins/arm/v7/opdefs/A88112_msr.d | 81 ++++ plugins/arm/v7/opdefs/A88114_mul.d | 139 +++++++ plugins/arm/v7/opdefs/A88115_mvn.d | 141 +++++++ plugins/arm/v7/opdefs/A88116_mvn.d | 166 ++++++++ plugins/arm/v7/opdefs/A88117_mvn.d | 99 +++++ plugins/arm/v7/opdefs/A88119_nop.d | 81 ++++ plugins/arm/v7/opdefs/A8811_add.d | 97 +++++ plugins/arm/v7/opdefs/A88120_orn.d | 83 ++++ plugins/arm/v7/opdefs/A88121_orn.d | 85 ++++ plugins/arm/v7/opdefs/A88122_orr.d | 145 +++++++ plugins/arm/v7/opdefs/A88123_orr.d | 171 ++++++++ plugins/arm/v7/opdefs/A88124_orr.d | 101 +++++ plugins/arm/v7/opdefs/A88125_pkh.d | 149 +++++++ plugins/arm/v7/opdefs/A88126_pld.d | 183 +++++++++ plugins/arm/v7/opdefs/A88127_pld.d | 73 ++++ plugins/arm/v7/opdefs/A88128_pld.d | 137 +++++++ plugins/arm/v7/opdefs/A8812_adr.d | 150 +++++++ plugins/arm/v7/opdefs/A88130_pli.d | 79 ++++ plugins/arm/v7/opdefs/A88131_pop.d | 111 ++++++ plugins/arm/v7/opdefs/A88132_pop.d | 97 +++++ plugins/arm/v7/opdefs/A88133_push.d | 145 +++++++ plugins/arm/v7/opdefs/A88134_qadd.d | 83 ++++ plugins/arm/v7/opdefs/A88135_qadd16.d | 83 ++++ plugins/arm/v7/opdefs/A88136_qadd8.d | 83 ++++ plugins/arm/v7/opdefs/A88137_qasx.d | 83 ++++ plugins/arm/v7/opdefs/A88138_qdadd.d | 83 ++++ plugins/arm/v7/opdefs/A88139_qdsub.d | 83 ++++ plugins/arm/v7/opdefs/A8813_and.d | 145 +++++++ plugins/arm/v7/opdefs/A88140_qsax.d | 83 ++++ plugins/arm/v7/opdefs/A88141_qsub.d | 83 ++++ plugins/arm/v7/opdefs/A88142_qsub16.d | 83 ++++ plugins/arm/v7/opdefs/A88143_qsub8.d | 83 ++++ plugins/arm/v7/opdefs/A88144_rbit.d | 81 ++++ plugins/arm/v7/opdefs/A88145_rev.d | 102 +++++ plugins/arm/v7/opdefs/A88146_rev16.d | 102 +++++ plugins/arm/v7/opdefs/A88147_revsh.d | 102 +++++ plugins/arm/v7/opdefs/A88149_ror.d | 145 +++++++ plugins/arm/v7/opdefs/A8814_and.d | 171 ++++++++ plugins/arm/v7/opdefs/A88150_ror.d | 167 ++++++++ plugins/arm/v7/opdefs/A88151_rrx.d | 141 +++++++ plugins/arm/v7/opdefs/A88152_rsb.d | 167 ++++++++ plugins/arm/v7/opdefs/A88153_rsb.d | 149 +++++++ plugins/arm/v7/opdefs/A88154_rsb.d | 101 +++++ plugins/arm/v7/opdefs/A88155_rsc.d | 95 +++++ plugins/arm/v7/opdefs/A88156_rsc.d | 97 +++++ plugins/arm/v7/opdefs/A88157_rsc.d | 101 +++++ plugins/arm/v7/opdefs/A88158_sadd16.d | 83 ++++ plugins/arm/v7/opdefs/A88159_sadd8.d | 83 ++++ plugins/arm/v7/opdefs/A8815_and.d | 101 +++++ plugins/arm/v7/opdefs/A88160_sasx.d | 83 ++++ plugins/arm/v7/opdefs/A88161_sbc.d | 145 +++++++ plugins/arm/v7/opdefs/A88162_sbc.d | 171 ++++++++ plugins/arm/v7/opdefs/A88163_sbc.d | 101 +++++ plugins/arm/v7/opdefs/A88164_sbfx.d | 87 ++++ plugins/arm/v7/opdefs/A88165_sdiv.d | 83 ++++ plugins/arm/v7/opdefs/A88166_sel.d | 83 ++++ plugins/arm/v7/opdefs/A88167_setend.d | 73 ++++ plugins/arm/v7/opdefs/A88168_sev.d | 81 ++++ plugins/arm/v7/opdefs/A88169_shadd16.d | 83 ++++ plugins/arm/v7/opdefs/A8816_asr.d | 167 ++++++++ plugins/arm/v7/opdefs/A88170_shadd8.d | 83 ++++ plugins/arm/v7/opdefs/A88171_shasx.d | 83 ++++ plugins/arm/v7/opdefs/A88172_shsax.d | 83 ++++ plugins/arm/v7/opdefs/A88173_shsub16.d | 83 ++++ plugins/arm/v7/opdefs/A88174_shsub8.d | 83 ++++ plugins/arm/v7/opdefs/A88176_smla.d | 261 ++++++++++++ plugins/arm/v7/opdefs/A88177_smlad.d | 149 +++++++ plugins/arm/v7/opdefs/A88178_smlal.d | 120 ++++++ plugins/arm/v7/opdefs/A88179_smlal.d | 261 ++++++++++++ plugins/arm/v7/opdefs/A8817_asr.d | 167 ++++++++ plugins/arm/v7/opdefs/A88180_smlald.d | 149 +++++++ plugins/arm/v7/opdefs/A88181_smlaw.d | 149 +++++++ plugins/arm/v7/opdefs/A88182_smlsd.d | 149 +++++++ plugins/arm/v7/opdefs/A88183_smlsld.d | 149 +++++++ plugins/arm/v7/opdefs/A88184_smmla.d | 149 +++++++ plugins/arm/v7/opdefs/A88185_smmls.d | 149 +++++++ plugins/arm/v7/opdefs/A88186_smmul.d | 145 +++++++ plugins/arm/v7/opdefs/A88187_smuad.d | 145 +++++++ plugins/arm/v7/opdefs/A88188_smul.d | 253 ++++++++++++ plugins/arm/v7/opdefs/A88189_smull.d | 120 ++++++ plugins/arm/v7/opdefs/A8818_b.d | 192 +++++++++ plugins/arm/v7/opdefs/A88190_smulw.d | 145 +++++++ plugins/arm/v7/opdefs/A88191_smusd.d | 145 +++++++ plugins/arm/v7/opdefs/A88193_ssat.d | 85 ++++ plugins/arm/v7/opdefs/A88194_ssat16.d | 83 ++++ plugins/arm/v7/opdefs/A88195_ssax.d | 83 ++++ plugins/arm/v7/opdefs/A88196_ssub16.d | 83 ++++ plugins/arm/v7/opdefs/A88197_ssub8.d | 83 ++++ plugins/arm/v7/opdefs/A88198_stc.d | 461 ++++++++++++++++++++++ plugins/arm/v7/opdefs/A88199_stm.d | 111 ++++++ plugins/arm/v7/opdefs/A8819_bfc.d | 85 ++++ plugins/arm/v7/opdefs/A881_adc.d | 145 +++++++ plugins/arm/v7/opdefs/A88200_stmda.d | 61 +++ plugins/arm/v7/opdefs/A88201_stmdb.d | 83 ++++ plugins/arm/v7/opdefs/A88202_stmib.d | 61 +++ plugins/arm/v7/opdefs/A88203_str.d | 180 +++++++++ plugins/arm/v7/opdefs/A88204_str.d | 129 ++++++ plugins/arm/v7/opdefs/A88205_str.d | 179 +++++++++ plugins/arm/v7/opdefs/A88206_strb.d | 157 ++++++++ plugins/arm/v7/opdefs/A88207_strb.d | 129 ++++++ plugins/arm/v7/opdefs/A88208_strb.d | 179 +++++++++ plugins/arm/v7/opdefs/A88209_strbt.d | 115 ++++++ plugins/arm/v7/opdefs/A8820_bfi.d | 87 ++++ plugins/arm/v7/opdefs/A88210_strd.d | 213 ++++++++++ plugins/arm/v7/opdefs/A88211_strd.d | 132 +++++++ plugins/arm/v7/opdefs/A88212_strex.d | 87 ++++ plugins/arm/v7/opdefs/A88213_strexb.d | 85 ++++ plugins/arm/v7/opdefs/A88214_strexd.d | 87 ++++ plugins/arm/v7/opdefs/A88215_strexh.d | 85 ++++ plugins/arm/v7/opdefs/A88216_strh.d | 157 ++++++++ plugins/arm/v7/opdefs/A88217_strh.d | 129 ++++++ plugins/arm/v7/opdefs/A88218_strh.d | 176 +++++++++ plugins/arm/v7/opdefs/A88219_strht.d | 114 ++++++ plugins/arm/v7/opdefs/A8821_bic.d | 145 +++++++ plugins/arm/v7/opdefs/A88220_strt.d | 115 ++++++ plugins/arm/v7/opdefs/A88221_sub.d | 149 +++++++ plugins/arm/v7/opdefs/A88222_sub.d | 95 +++++ plugins/arm/v7/opdefs/A88223_sub.d | 171 ++++++++ plugins/arm/v7/opdefs/A88224_sub.d | 101 +++++ plugins/arm/v7/opdefs/A88225_sub.d | 189 +++++++++ plugins/arm/v7/opdefs/A88226_sub.d | 149 +++++++ plugins/arm/v7/opdefs/A88228_svc.d | 79 ++++ plugins/arm/v7/opdefs/A88229_swp.d | 97 +++++ plugins/arm/v7/opdefs/A8822_bic.d | 171 ++++++++ plugins/arm/v7/opdefs/A88230_sxtab.d | 85 ++++ plugins/arm/v7/opdefs/A88231_sxtab16.d | 85 ++++ plugins/arm/v7/opdefs/A88232_sxtah.d | 85 ++++ plugins/arm/v7/opdefs/A88233_sxtb.d | 105 +++++ plugins/arm/v7/opdefs/A88234_sxtb16.d | 83 ++++ plugins/arm/v7/opdefs/A88235_sxth.d | 105 +++++ plugins/arm/v7/opdefs/A88237_teq.d | 81 ++++ plugins/arm/v7/opdefs/A88238_teq.d | 83 ++++ plugins/arm/v7/opdefs/A88239_teq.d | 63 +++ plugins/arm/v7/opdefs/A8823_bic.d | 101 +++++ plugins/arm/v7/opdefs/A88240_tst.d | 81 ++++ plugins/arm/v7/opdefs/A88241_tst.d | 104 +++++ plugins/arm/v7/opdefs/A88242_tst.d | 63 +++ plugins/arm/v7/opdefs/A88243_uadd16.d | 83 ++++ plugins/arm/v7/opdefs/A88244_uadd8.d | 83 ++++ plugins/arm/v7/opdefs/A88245_uasx.d | 83 ++++ plugins/arm/v7/opdefs/A88246_ubfx.d | 87 ++++ plugins/arm/v7/opdefs/A88247_udf.d | 93 +++++ plugins/arm/v7/opdefs/A88248_udiv.d | 83 ++++ plugins/arm/v7/opdefs/A88249_uhadd16.d | 83 ++++ plugins/arm/v7/opdefs/A8824_bkpt.d | 73 ++++ plugins/arm/v7/opdefs/A88250_uhadd8.d | 83 ++++ plugins/arm/v7/opdefs/A88251_uhasx.d | 83 ++++ plugins/arm/v7/opdefs/A88252_uhsax.d | 83 ++++ plugins/arm/v7/opdefs/A88253_uhsub16.d | 83 ++++ plugins/arm/v7/opdefs/A88254_uhsub8.d | 83 ++++ plugins/arm/v7/opdefs/A88255_umaal.d | 85 ++++ plugins/arm/v7/opdefs/A88256_umlal.d | 120 ++++++ plugins/arm/v7/opdefs/A88257_umull.d | 120 ++++++ plugins/arm/v7/opdefs/A88258_uqadd16.d | 83 ++++ plugins/arm/v7/opdefs/A88259_uqadd8.d | 83 ++++ plugins/arm/v7/opdefs/A8825_bl.d | 151 +++++++ plugins/arm/v7/opdefs/A88260_uqasx.d | 83 ++++ plugins/arm/v7/opdefs/A88261_uqsax.d | 83 ++++ plugins/arm/v7/opdefs/A88262_uqsub16.d | 83 ++++ plugins/arm/v7/opdefs/A88263_uqsub8.d | 83 ++++ plugins/arm/v7/opdefs/A88264_usad8.d | 83 ++++ plugins/arm/v7/opdefs/A88265_usada8.d | 85 ++++ plugins/arm/v7/opdefs/A88266_usat.d | 85 ++++ plugins/arm/v7/opdefs/A88267_usat16.d | 83 ++++ plugins/arm/v7/opdefs/A88268_usax.d | 83 ++++ plugins/arm/v7/opdefs/A88269_usub16.d | 83 ++++ plugins/arm/v7/opdefs/A8826_blx.d | 79 ++++ plugins/arm/v7/opdefs/A88270_usub8.d | 83 ++++ plugins/arm/v7/opdefs/A88271_uxtab.d | 85 ++++ plugins/arm/v7/opdefs/A88272_uxtab16.d | 85 ++++ plugins/arm/v7/opdefs/A88273_uxtah.d | 85 ++++ plugins/arm/v7/opdefs/A88274_uxtb.d | 105 +++++ plugins/arm/v7/opdefs/A88275_uxtb16.d | 83 ++++ plugins/arm/v7/opdefs/A88276_uxth.d | 105 +++++ plugins/arm/v7/opdefs/A8827_bx.d | 91 +++++ plugins/arm/v7/opdefs/A8828_bxj.d | 79 ++++ plugins/arm/v7/opdefs/A8829_cb.d | 89 +++++ plugins/arm/v7/opdefs/A882_adc.d | 171 ++++++++ plugins/arm/v7/opdefs/A8830_cdp.d | 133 +++++++ plugins/arm/v7/opdefs/A8832_clrex.d | 61 +++ plugins/arm/v7/opdefs/A8833_clz.d | 81 ++++ plugins/arm/v7/opdefs/A8834_cmn.d | 81 ++++ plugins/arm/v7/opdefs/A8835_cmn.d | 104 +++++ plugins/arm/v7/opdefs/A8836_cmn.d | 63 +++ plugins/arm/v7/opdefs/A8837_cmp.d | 102 +++++ plugins/arm/v7/opdefs/A8838_cmp.d | 125 ++++++ plugins/arm/v7/opdefs/A8839_cmp.d | 63 +++ plugins/arm/v7/opdefs/A883_adc.d | 101 +++++ plugins/arm/v7/opdefs/A88424_wfe.d | 81 ++++ plugins/arm/v7/opdefs/A88425_wfi.d | 81 ++++ plugins/arm/v7/opdefs/A88426_yield.d | 81 ++++ plugins/arm/v7/opdefs/A8842_dbg.d | 79 ++++ plugins/arm/v7/opdefs/A8843_dmb.d | 73 ++++ plugins/arm/v7/opdefs/A8844_dsb.d | 73 ++++ plugins/arm/v7/opdefs/A8846_eor.d | 145 +++++++ plugins/arm/v7/opdefs/A8847_eor.d | 171 ++++++++ plugins/arm/v7/opdefs/A8848_eor.d | 101 +++++ plugins/arm/v7/opdefs/A884_add.d | 149 +++++++ plugins/arm/v7/opdefs/A8854_it.d | 59 +++ plugins/arm/v7/opdefs/A8855_ldc.d | 461 ++++++++++++++++++++++ plugins/arm/v7/opdefs/A8856_ldc.d | 201 ++++++++++ plugins/arm/v7/opdefs/A8857_ldm.d | 83 ++++ plugins/arm/v7/opdefs/A8858_ldm.d | 61 +++ plugins/arm/v7/opdefs/A8859_ldmda.d | 61 +++ plugins/arm/v7/opdefs/A885_add.d | 95 +++++ plugins/arm/v7/opdefs/A8860_ldmdb.d | 83 ++++ plugins/arm/v7/opdefs/A8861_ldmib.d | 61 +++ plugins/arm/v7/opdefs/A8862_ldr.d | 180 +++++++++ plugins/arm/v7/opdefs/A8863_ldr.d | 129 ++++++ plugins/arm/v7/opdefs/A8864_ldr.d | 123 ++++++ plugins/arm/v7/opdefs/A8865_ldr.d | 80 ++++ plugins/arm/v7/opdefs/A8866_ldr.d | 132 +++++++ plugins/arm/v7/opdefs/A8867_ldrb.d | 157 ++++++++ plugins/arm/v7/opdefs/A8868_ldrb.d | 129 ++++++ plugins/arm/v7/opdefs/A8869_ldrb.d | 81 ++++ plugins/arm/v7/opdefs/A886_add.d | 129 ++++++ plugins/arm/v7/opdefs/A8870_ldrb.d | 179 +++++++++ plugins/arm/v7/opdefs/A8871_ldrbt.d | 115 ++++++ plugins/arm/v7/opdefs/A8872_ldrd.d | 213 ++++++++++ plugins/arm/v7/opdefs/A8873_ldrd.d | 83 ++++ plugins/arm/v7/opdefs/A8874_ldrd.d | 132 +++++++ plugins/arm/v7/opdefs/A8875_ldrex.d | 85 ++++ plugins/arm/v7/opdefs/A8876_ldrexb.d | 83 ++++ plugins/arm/v7/opdefs/A8877_ldrexd.d | 85 ++++ plugins/arm/v7/opdefs/A8878_ldrexh.d | 83 ++++ plugins/arm/v7/opdefs/A8879_ldrh.d | 157 ++++++++ plugins/arm/v7/opdefs/A887_add.d | 97 +++++ plugins/arm/v7/opdefs/A8880_ldrh.d | 129 ++++++ plugins/arm/v7/opdefs/A8881_ldrh.d | 81 ++++ plugins/arm/v7/opdefs/A8882_ldrh.d | 176 +++++++++ plugins/arm/v7/opdefs/A8883_ldrht.d | 114 ++++++ plugins/arm/v7/opdefs/A8884_ldrsb.d | 230 +++++++++++ plugins/arm/v7/opdefs/A8885_ldrsb.d | 81 ++++ plugins/arm/v7/opdefs/A8886_ldrsb.d | 176 +++++++++ plugins/arm/v7/opdefs/A8887_ldrsbt.d | 114 ++++++ plugins/arm/v7/opdefs/A8888_ldrsh.d | 230 +++++++++++ plugins/arm/v7/opdefs/A8889_ldrsh.d | 81 ++++ plugins/arm/v7/opdefs/A888_add.d | 101 +++++ plugins/arm/v7/opdefs/A8890_ldrsh.d | 176 +++++++++ plugins/arm/v7/opdefs/A8891_ldrsht.d | 114 ++++++ plugins/arm/v7/opdefs/A8892_ldrt.d | 115 ++++++ plugins/arm/v7/opdefs/A8894_lsl.d | 167 ++++++++ plugins/arm/v7/opdefs/A8895_lsl.d | 167 ++++++++ plugins/arm/v7/opdefs/A8896_lsr.d | 167 ++++++++ plugins/arm/v7/opdefs/A8897_lsr.d | 167 ++++++++ plugins/arm/v7/opdefs/A8898_mcr.d | 133 +++++++ plugins/arm/v7/opdefs/A8899_mcrr.d | 129 ++++++ plugins/arm/v7/opdefs/A889_add.d | 211 ++++++++++ plugins/arm/v7/opdefs/B9310_msr.d | 81 ++++ plugins/arm/v7/opdefs/B9311_msr.d | 60 +++ plugins/arm/v7/opdefs/B9312_msr.d | 81 ++++ plugins/arm/v7/opdefs/B9313_rfe.d | 169 ++++++++ plugins/arm/v7/opdefs/B9314_smc.d | 79 ++++ plugins/arm/v7/opdefs/B9315_srs.d | 77 ++++ plugins/arm/v7/opdefs/B9316_srs.d | 131 +++++++ plugins/arm/v7/opdefs/B9317_stm.d | 151 +++++++ plugins/arm/v7/opdefs/B9319_subs.d | 55 +++ plugins/arm/v7/opdefs/B931_cps.d | 147 +++++++ plugins/arm/v7/opdefs/B9320_subs.d | 95 +++++ plugins/arm/v7/opdefs/B9321_vmrs.d | 75 ++++ plugins/arm/v7/opdefs/B9322_vmsr.d | 75 ++++ plugins/arm/v7/opdefs/B932_cps.d | 101 +++++ plugins/arm/v7/opdefs/B933_eret.d | 67 ++++ plugins/arm/v7/opdefs/B934_hvc.d | 73 ++++ plugins/arm/v7/opdefs/B935_ldm.d | 155 ++++++++ plugins/arm/v7/opdefs/B936_ldm.d | 151 +++++++ plugins/arm/v7/opdefs/B938_mrs.d | 81 ++++ plugins/arm/v7/opdefs/B939_mrs.d | 81 ++++ plugins/arm/v7/opdefs/Makefile.am | 544 ++++++++++++++------------ plugins/arm/v7/opdefs/adc_A881.d | 145 ------- plugins/arm/v7/opdefs/adc_A882.d | 171 -------- plugins/arm/v7/opdefs/adc_A883.d | 101 ----- plugins/arm/v7/opdefs/add_A8810.d | 129 ------ plugins/arm/v7/opdefs/add_A8811.d | 97 ----- plugins/arm/v7/opdefs/add_A884.d | 149 ------- plugins/arm/v7/opdefs/add_A885.d | 95 ----- plugins/arm/v7/opdefs/add_A886.d | 129 ------ plugins/arm/v7/opdefs/add_A887.d | 97 ----- plugins/arm/v7/opdefs/add_A888.d | 101 ----- plugins/arm/v7/opdefs/add_A889.d | 211 ---------- plugins/arm/v7/opdefs/adr_A8812.d | 150 ------- plugins/arm/v7/opdefs/and_A8813.d | 145 ------- plugins/arm/v7/opdefs/and_A8814.d | 171 -------- plugins/arm/v7/opdefs/and_A8815.d | 101 ----- plugins/arm/v7/opdefs/asr_A8816.d | 167 -------- plugins/arm/v7/opdefs/asr_A8817.d | 167 -------- plugins/arm/v7/opdefs/b_A8818.d | 192 --------- plugins/arm/v7/opdefs/bfc_A8819.d | 85 ---- plugins/arm/v7/opdefs/bfi_A8820.d | 87 ---- plugins/arm/v7/opdefs/bic_A8821.d | 145 ------- plugins/arm/v7/opdefs/bic_A8822.d | 171 -------- plugins/arm/v7/opdefs/bic_A8823.d | 101 ----- plugins/arm/v7/opdefs/bkpt_A8824.d | 73 ---- plugins/arm/v7/opdefs/bl_A8825.d | 151 ------- plugins/arm/v7/opdefs/blx_A8826.d | 79 ---- plugins/arm/v7/opdefs/bx_A8827.d | 91 ----- plugins/arm/v7/opdefs/bxj_A8828.d | 79 ---- plugins/arm/v7/opdefs/cb_A8829.d | 89 ----- plugins/arm/v7/opdefs/cdp_A8830.d | 133 ------- plugins/arm/v7/opdefs/clrex_A8832.d | 61 --- plugins/arm/v7/opdefs/clz_A8833.d | 81 ---- plugins/arm/v7/opdefs/cmn_A8834.d | 81 ---- plugins/arm/v7/opdefs/cmn_A8835.d | 104 ----- plugins/arm/v7/opdefs/cmn_A8836.d | 63 --- plugins/arm/v7/opdefs/cmp_A8837.d | 102 ----- plugins/arm/v7/opdefs/cmp_A8838.d | 125 ------ plugins/arm/v7/opdefs/cmp_A8839.d | 63 --- plugins/arm/v7/opdefs/dbg_A8842.d | 79 ---- plugins/arm/v7/opdefs/dmb_A8843.d | 73 ---- plugins/arm/v7/opdefs/dsb_A8844.d | 73 ---- plugins/arm/v7/opdefs/eor_A8846.d | 145 ------- plugins/arm/v7/opdefs/eor_A8847.d | 171 -------- plugins/arm/v7/opdefs/eor_A8848.d | 101 ----- plugins/arm/v7/opdefs/it_A8854.d | 59 --- plugins/arm/v7/opdefs/ldc_A8855.d | 461 ---------------------- plugins/arm/v7/opdefs/ldc_A8856.d | 201 ---------- plugins/arm/v7/opdefs/ldm_A8857.d | 83 ---- plugins/arm/v7/opdefs/ldm_A8858.d | 61 --- plugins/arm/v7/opdefs/ldmda_A8859.d | 61 --- plugins/arm/v7/opdefs/ldmdb_A8860.d | 83 ---- plugins/arm/v7/opdefs/ldmib_A8861.d | 61 --- plugins/arm/v7/opdefs/ldr_A8862.d | 180 --------- plugins/arm/v7/opdefs/ldr_A8863.d | 129 ------ plugins/arm/v7/opdefs/ldr_A8864.d | 123 ------ plugins/arm/v7/opdefs/ldr_A8865.d | 80 ---- plugins/arm/v7/opdefs/ldr_A8866.d | 132 ------- plugins/arm/v7/opdefs/ldrb_A8867.d | 157 -------- plugins/arm/v7/opdefs/ldrb_A8868.d | 129 ------ plugins/arm/v7/opdefs/ldrb_A8869.d | 81 ---- plugins/arm/v7/opdefs/ldrb_A8870.d | 179 --------- plugins/arm/v7/opdefs/ldrbt_A8871.d | 115 ------ plugins/arm/v7/opdefs/ldrd_A8872.d | 213 ---------- plugins/arm/v7/opdefs/ldrd_A8873.d | 83 ---- plugins/arm/v7/opdefs/ldrd_A8874.d | 132 ------- plugins/arm/v7/opdefs/ldrex_A8875.d | 85 ---- plugins/arm/v7/opdefs/ldrexb_A8876.d | 83 ---- plugins/arm/v7/opdefs/ldrexd_A8877.d | 85 ---- plugins/arm/v7/opdefs/ldrexh_A8878.d | 83 ---- plugins/arm/v7/opdefs/ldrh_A8879.d | 157 -------- plugins/arm/v7/opdefs/ldrh_A8880.d | 129 ------ plugins/arm/v7/opdefs/ldrh_A8881.d | 81 ---- plugins/arm/v7/opdefs/ldrh_A8882.d | 176 --------- plugins/arm/v7/opdefs/ldrht_A8883.d | 114 ------ plugins/arm/v7/opdefs/ldrsb_A8884.d | 230 ----------- plugins/arm/v7/opdefs/ldrsb_A8885.d | 81 ---- plugins/arm/v7/opdefs/ldrsb_A8886.d | 176 --------- plugins/arm/v7/opdefs/ldrsbt_A8887.d | 114 ------ plugins/arm/v7/opdefs/ldrsh_A8888.d | 230 ----------- plugins/arm/v7/opdefs/ldrsh_A8889.d | 81 ---- plugins/arm/v7/opdefs/ldrsh_A8890.d | 176 --------- plugins/arm/v7/opdefs/ldrsht_A8891.d | 114 ------ plugins/arm/v7/opdefs/ldrt_A8892.d | 115 ------ plugins/arm/v7/opdefs/lsl_A8894.d | 167 -------- plugins/arm/v7/opdefs/lsl_A8895.d | 167 -------- plugins/arm/v7/opdefs/lsr_A8896.d | 167 -------- plugins/arm/v7/opdefs/lsr_A8897.d | 167 -------- plugins/arm/v7/opdefs/mcr_A8898.d | 133 ------- plugins/arm/v7/opdefs/mcrr_A8899.d | 129 ------ plugins/arm/v7/opdefs/mla_A88100.d | 120 ------ plugins/arm/v7/opdefs/mls_A88101.d | 85 ---- plugins/arm/v7/opdefs/mov_A88102.d | 210 ---------- plugins/arm/v7/opdefs/mov_A88103.d | 123 ------ plugins/arm/v7/opdefs/mov_A88104.d | 93 ----- plugins/arm/v7/opdefs/movt_A88106.d | 81 ---- plugins/arm/v7/opdefs/mrc_A88107.d | 133 ------- plugins/arm/v7/opdefs/mrrc_A88108.d | 129 ------ plugins/arm/v7/opdefs/mrs_A88109.d | 81 ---- plugins/arm/v7/opdefs/msr_A88111.d | 60 --- plugins/arm/v7/opdefs/msr_A88112.d | 81 ---- plugins/arm/v7/opdefs/mul_A88114.d | 139 ------- plugins/arm/v7/opdefs/mvn_A88115.d | 141 ------- plugins/arm/v7/opdefs/mvn_A88116.d | 166 -------- plugins/arm/v7/opdefs/mvn_A88117.d | 99 ----- plugins/arm/v7/opdefs/nop_A88119.d | 81 ---- plugins/arm/v7/opdefs/orn_A88120.d | 83 ---- plugins/arm/v7/opdefs/orn_A88121.d | 85 ---- plugins/arm/v7/opdefs/orr_A88122.d | 145 ------- plugins/arm/v7/opdefs/orr_A88123.d | 171 -------- plugins/arm/v7/opdefs/orr_A88124.d | 101 ----- plugins/arm/v7/opdefs/pkh_A88125.d | 149 ------- plugins/arm/v7/opdefs/pld_A88126.d | 183 --------- plugins/arm/v7/opdefs/pld_A88127.d | 73 ---- plugins/arm/v7/opdefs/pld_A88128.d | 137 ------- plugins/arm/v7/opdefs/pli_A88130.d | 79 ---- plugins/arm/v7/opdefs/pop_A88131.d | 111 ------ plugins/arm/v7/opdefs/pop_A88132.d | 97 ----- plugins/arm/v7/opdefs/push_A88133.d | 145 ------- plugins/arm/v7/opdefs/qadd16_A88135.d | 83 ---- plugins/arm/v7/opdefs/qadd8_A88136.d | 83 ---- plugins/arm/v7/opdefs/qadd_A88134.d | 83 ---- plugins/arm/v7/opdefs/qasx_A88137.d | 83 ---- plugins/arm/v7/opdefs/qdadd_A88138.d | 83 ---- plugins/arm/v7/opdefs/qdsub_A88139.d | 83 ---- plugins/arm/v7/opdefs/qsax_A88140.d | 83 ---- plugins/arm/v7/opdefs/qsub16_A88142.d | 83 ---- plugins/arm/v7/opdefs/qsub8_A88143.d | 83 ---- plugins/arm/v7/opdefs/qsub_A88141.d | 83 ---- plugins/arm/v7/opdefs/rbit_A88144.d | 81 ---- plugins/arm/v7/opdefs/rev16_A88146.d | 102 ----- plugins/arm/v7/opdefs/rev_A88145.d | 102 ----- plugins/arm/v7/opdefs/revsh_A88147.d | 102 ----- plugins/arm/v7/opdefs/ror_A88149.d | 145 ------- plugins/arm/v7/opdefs/ror_A88150.d | 167 -------- plugins/arm/v7/opdefs/rrx_A88151.d | 141 ------- plugins/arm/v7/opdefs/rsb_A88152.d | 167 -------- plugins/arm/v7/opdefs/rsb_A88153.d | 149 ------- plugins/arm/v7/opdefs/rsb_A88154.d | 101 ----- plugins/arm/v7/opdefs/rsc_A88155.d | 95 ----- plugins/arm/v7/opdefs/rsc_A88156.d | 97 ----- plugins/arm/v7/opdefs/rsc_A88157.d | 101 ----- plugins/arm/v7/opdefs/sadd16_A88158.d | 83 ---- plugins/arm/v7/opdefs/sadd8_A88159.d | 83 ---- plugins/arm/v7/opdefs/sasx_A88160.d | 83 ---- plugins/arm/v7/opdefs/sbc_A88161.d | 145 ------- plugins/arm/v7/opdefs/sbc_A88162.d | 171 -------- plugins/arm/v7/opdefs/sbc_A88163.d | 101 ----- plugins/arm/v7/opdefs/sbfx_A88164.d | 87 ---- plugins/arm/v7/opdefs/sdiv_A88165.d | 83 ---- plugins/arm/v7/opdefs/sel_A88166.d | 83 ---- plugins/arm/v7/opdefs/setend_A88167.d | 73 ---- plugins/arm/v7/opdefs/sev_A88168.d | 81 ---- plugins/arm/v7/opdefs/shadd16_A88169.d | 83 ---- plugins/arm/v7/opdefs/shadd8_A88170.d | 83 ---- plugins/arm/v7/opdefs/shasx_A88171.d | 83 ---- plugins/arm/v7/opdefs/shsax_A88172.d | 83 ---- plugins/arm/v7/opdefs/shsub16_A88173.d | 83 ---- plugins/arm/v7/opdefs/shsub8_A88174.d | 83 ---- plugins/arm/v7/opdefs/smla_A88176.d | 261 ------------ plugins/arm/v7/opdefs/smlad_A88177.d | 149 ------- plugins/arm/v7/opdefs/smlal_A88178.d | 120 ------ plugins/arm/v7/opdefs/smlal_A88179.d | 261 ------------ plugins/arm/v7/opdefs/smlald_A88180.d | 149 ------- plugins/arm/v7/opdefs/smlaw_A88181.d | 149 ------- plugins/arm/v7/opdefs/smlsd_A88182.d | 149 ------- plugins/arm/v7/opdefs/smlsld_A88183.d | 149 ------- plugins/arm/v7/opdefs/smmla_A88184.d | 149 ------- plugins/arm/v7/opdefs/smmls_A88185.d | 149 ------- plugins/arm/v7/opdefs/smmul_A88186.d | 145 ------- plugins/arm/v7/opdefs/smuad_A88187.d | 145 ------- plugins/arm/v7/opdefs/smul_A88188.d | 253 ------------ plugins/arm/v7/opdefs/smull_A88189.d | 120 ------ plugins/arm/v7/opdefs/smulw_A88190.d | 145 ------- plugins/arm/v7/opdefs/smusd_A88191.d | 145 ------- plugins/arm/v7/opdefs/ssat16_A88194.d | 83 ---- plugins/arm/v7/opdefs/ssat_A88193.d | 85 ---- plugins/arm/v7/opdefs/ssax_A88195.d | 83 ---- plugins/arm/v7/opdefs/ssub16_A88196.d | 83 ---- plugins/arm/v7/opdefs/ssub8_A88197.d | 83 ---- plugins/arm/v7/opdefs/stc_A88198.d | 461 ---------------------- plugins/arm/v7/opdefs/stm_A88199.d | 111 ------ plugins/arm/v7/opdefs/stmda_A88200.d | 61 --- plugins/arm/v7/opdefs/stmdb_A88201.d | 83 ---- plugins/arm/v7/opdefs/stmib_A88202.d | 61 --- plugins/arm/v7/opdefs/str_A88203.d | 180 --------- plugins/arm/v7/opdefs/str_A88204.d | 129 ------ plugins/arm/v7/opdefs/str_A88205.d | 179 --------- plugins/arm/v7/opdefs/strb_A88206.d | 157 -------- plugins/arm/v7/opdefs/strb_A88207.d | 129 ------ plugins/arm/v7/opdefs/strb_A88208.d | 179 --------- plugins/arm/v7/opdefs/strbt_A88209.d | 115 ------ plugins/arm/v7/opdefs/strd_A88210.d | 213 ---------- plugins/arm/v7/opdefs/strd_A88211.d | 132 ------- plugins/arm/v7/opdefs/strex_A88212.d | 87 ---- plugins/arm/v7/opdefs/strexb_A88213.d | 85 ---- plugins/arm/v7/opdefs/strexd_A88214.d | 87 ---- plugins/arm/v7/opdefs/strexh_A88215.d | 85 ---- plugins/arm/v7/opdefs/strh_A88216.d | 157 -------- plugins/arm/v7/opdefs/strh_A88217.d | 129 ------ plugins/arm/v7/opdefs/strh_A88218.d | 176 --------- plugins/arm/v7/opdefs/strht_A88219.d | 114 ------ plugins/arm/v7/opdefs/strt_A88220.d | 115 ------ plugins/arm/v7/opdefs/sub_A88221.d | 149 ------- plugins/arm/v7/opdefs/sub_A88222.d | 95 ----- plugins/arm/v7/opdefs/sub_A88223.d | 171 -------- plugins/arm/v7/opdefs/sub_A88224.d | 101 ----- plugins/arm/v7/opdefs/sub_A88225.d | 189 --------- plugins/arm/v7/opdefs/sub_A88226.d | 149 ------- plugins/arm/v7/opdefs/svc_A88228.d | 79 ---- plugins/arm/v7/opdefs/swp_A88229.d | 97 ----- plugins/arm/v7/opdefs/sxtab16_A88231.d | 85 ---- plugins/arm/v7/opdefs/sxtab_A88230.d | 85 ---- plugins/arm/v7/opdefs/sxtah_A88232.d | 85 ---- plugins/arm/v7/opdefs/sxtb16_A88234.d | 83 ---- plugins/arm/v7/opdefs/sxtb_A88233.d | 105 ----- plugins/arm/v7/opdefs/sxth_A88235.d | 105 ----- plugins/arm/v7/opdefs/teq_A88237.d | 81 ---- plugins/arm/v7/opdefs/teq_A88238.d | 83 ---- plugins/arm/v7/opdefs/teq_A88239.d | 63 --- plugins/arm/v7/opdefs/tst_A88240.d | 81 ---- plugins/arm/v7/opdefs/tst_A88241.d | 104 ----- plugins/arm/v7/opdefs/tst_A88242.d | 63 --- plugins/arm/v7/opdefs/uadd16_A88243.d | 83 ---- plugins/arm/v7/opdefs/uadd8_A88244.d | 83 ---- plugins/arm/v7/opdefs/uasx_A88245.d | 83 ---- plugins/arm/v7/opdefs/ubfx_A88246.d | 87 ---- plugins/arm/v7/opdefs/udf_A88247.d | 93 ----- plugins/arm/v7/opdefs/udiv_A88248.d | 83 ---- plugins/arm/v7/opdefs/uhadd16_A88249.d | 83 ---- plugins/arm/v7/opdefs/uhadd8_A88250.d | 83 ---- plugins/arm/v7/opdefs/uhasx_A88251.d | 83 ---- plugins/arm/v7/opdefs/uhsax_A88252.d | 83 ---- plugins/arm/v7/opdefs/uhsub16_A88253.d | 83 ---- plugins/arm/v7/opdefs/uhsub8_A88254.d | 83 ---- plugins/arm/v7/opdefs/umaal_A88255.d | 85 ---- plugins/arm/v7/opdefs/umlal_A88256.d | 120 ------ plugins/arm/v7/opdefs/umull_A88257.d | 120 ------ plugins/arm/v7/opdefs/uqadd16_A88258.d | 83 ---- plugins/arm/v7/opdefs/uqadd8_A88259.d | 83 ---- plugins/arm/v7/opdefs/uqasx_A88260.d | 83 ---- plugins/arm/v7/opdefs/uqsax_A88261.d | 83 ---- plugins/arm/v7/opdefs/uqsub16_A88262.d | 83 ---- plugins/arm/v7/opdefs/uqsub8_A88263.d | 83 ---- plugins/arm/v7/opdefs/usad8_A88264.d | 83 ---- plugins/arm/v7/opdefs/usada8_A88265.d | 85 ---- plugins/arm/v7/opdefs/usat16_A88267.d | 83 ---- plugins/arm/v7/opdefs/usat_A88266.d | 85 ---- plugins/arm/v7/opdefs/usax_A88268.d | 83 ---- plugins/arm/v7/opdefs/usub16_A88269.d | 83 ---- plugins/arm/v7/opdefs/usub8_A88270.d | 83 ---- plugins/arm/v7/opdefs/uxtab16_A88272.d | 85 ---- plugins/arm/v7/opdefs/uxtab_A88271.d | 85 ---- plugins/arm/v7/opdefs/uxtah_A88273.d | 85 ---- plugins/arm/v7/opdefs/uxtb16_A88275.d | 83 ---- plugins/arm/v7/opdefs/uxtb_A88274.d | 105 ----- plugins/arm/v7/opdefs/uxth_A88276.d | 105 ----- plugins/arm/v7/opdefs/wfe_A88424.d | 81 ---- plugins/arm/v7/opdefs/wfi_A88425.d | 81 ---- plugins/arm/v7/opdefs/yield_A88426.d | 81 ---- plugins/arm/v7/operands/Makefile.am | 1 + plugins/arm/v7/operands/iflags.c | 337 ++++++++++++++++ plugins/arm/v7/operands/iflags.h | 59 +++ plugins/arm/v7/operands/reglist.c | 28 ++ plugins/arm/v7/operands/reglist.h | 3 + plugins/arm/v7/simd.c | 386 +++++++++--------- plugins/arm/v7/thumb_16.c | 170 ++++---- plugins/arm/v7/thumb_32.c | 528 ++++++++++++------------- tools/d2c/coder.c | 241 +++++++----- tools/d2c/coder.h | 5 + tools/d2c/d2c.c | 40 +- 557 files changed, 33942 insertions(+), 31404 deletions(-) create mode 100644 plugins/arm/v7/opdefs/A88100_mla.d create mode 100644 plugins/arm/v7/opdefs/A88101_mls.d create mode 100644 plugins/arm/v7/opdefs/A88102_mov.d create mode 100644 plugins/arm/v7/opdefs/A88103_mov.d create mode 100644 plugins/arm/v7/opdefs/A88104_mov.d create mode 100644 plugins/arm/v7/opdefs/A88106_movt.d create mode 100644 plugins/arm/v7/opdefs/A88107_mrc.d create mode 100644 plugins/arm/v7/opdefs/A88108_mrrc.d create mode 100644 plugins/arm/v7/opdefs/A88109_mrs.d create mode 100644 plugins/arm/v7/opdefs/A8810_add.d create mode 100644 plugins/arm/v7/opdefs/A88111_msr.d create mode 100644 plugins/arm/v7/opdefs/A88112_msr.d create mode 100644 plugins/arm/v7/opdefs/A88114_mul.d create mode 100644 plugins/arm/v7/opdefs/A88115_mvn.d create mode 100644 plugins/arm/v7/opdefs/A88116_mvn.d create mode 100644 plugins/arm/v7/opdefs/A88117_mvn.d create mode 100644 plugins/arm/v7/opdefs/A88119_nop.d create mode 100644 plugins/arm/v7/opdefs/A8811_add.d create mode 100644 plugins/arm/v7/opdefs/A88120_orn.d create mode 100644 plugins/arm/v7/opdefs/A88121_orn.d create mode 100644 plugins/arm/v7/opdefs/A88122_orr.d create mode 100644 plugins/arm/v7/opdefs/A88123_orr.d create mode 100644 plugins/arm/v7/opdefs/A88124_orr.d create mode 100644 plugins/arm/v7/opdefs/A88125_pkh.d create mode 100644 plugins/arm/v7/opdefs/A88126_pld.d create mode 100644 plugins/arm/v7/opdefs/A88127_pld.d create mode 100644 plugins/arm/v7/opdefs/A88128_pld.d create mode 100644 plugins/arm/v7/opdefs/A8812_adr.d create mode 100644 plugins/arm/v7/opdefs/A88130_pli.d create mode 100644 plugins/arm/v7/opdefs/A88131_pop.d create mode 100644 plugins/arm/v7/opdefs/A88132_pop.d create mode 100644 plugins/arm/v7/opdefs/A88133_push.d create mode 100644 plugins/arm/v7/opdefs/A88134_qadd.d create mode 100644 plugins/arm/v7/opdefs/A88135_qadd16.d create mode 100644 plugins/arm/v7/opdefs/A88136_qadd8.d create mode 100644 plugins/arm/v7/opdefs/A88137_qasx.d create mode 100644 plugins/arm/v7/opdefs/A88138_qdadd.d create mode 100644 plugins/arm/v7/opdefs/A88139_qdsub.d create mode 100644 plugins/arm/v7/opdefs/A8813_and.d create mode 100644 plugins/arm/v7/opdefs/A88140_qsax.d create mode 100644 plugins/arm/v7/opdefs/A88141_qsub.d create mode 100644 plugins/arm/v7/opdefs/A88142_qsub16.d create mode 100644 plugins/arm/v7/opdefs/A88143_qsub8.d create mode 100644 plugins/arm/v7/opdefs/A88144_rbit.d create mode 100644 plugins/arm/v7/opdefs/A88145_rev.d create mode 100644 plugins/arm/v7/opdefs/A88146_rev16.d create mode 100644 plugins/arm/v7/opdefs/A88147_revsh.d create mode 100644 plugins/arm/v7/opdefs/A88149_ror.d create mode 100644 plugins/arm/v7/opdefs/A8814_and.d create mode 100644 plugins/arm/v7/opdefs/A88150_ror.d create mode 100644 plugins/arm/v7/opdefs/A88151_rrx.d create mode 100644 plugins/arm/v7/opdefs/A88152_rsb.d create mode 100644 plugins/arm/v7/opdefs/A88153_rsb.d create mode 100644 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*process_armv7_arm_data_processing_and_miscellaneous_ins result = process_armv7_arm_data_processing_immediate(raw); else if (op1 == b10000) - result = armv7_read_arm_instr_mov_immediate(raw); + result = armv7_read_arm_instr_a8_mov_immediate(raw); else if (op1 == b10100) - result = armv7_read_arm_instr_movt(raw); + result = armv7_read_arm_instr_a8_movt(raw); else if ((op1 & b11011) == b10010) result = process_armv7_arm_msr_immediate_and_hints(raw); @@ -325,28 +325,28 @@ static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t raw op2 = (raw >> 5) & 0x3; if ((op & b11110) == b00000) - result = armv7_read_arm_instr_and_register(raw); + result = armv7_read_arm_instr_a8_and_register(raw); else if ((op & b11110) == b00010) - result = armv7_read_arm_instr_eor_register(raw); + result = armv7_read_arm_instr_a8_eor_register(raw); else if ((op & b11110) == b00100) - result = armv7_read_arm_instr_sub_register(raw); + result = armv7_read_arm_instr_a8_sub_register(raw); else if ((op & b11110) == b00110) - result = armv7_read_arm_instr_rsb_register(raw); + result = armv7_read_arm_instr_a8_rsb_register(raw); else if ((op & b11110) == b01000) - result = armv7_read_arm_instr_add_register_arm(raw); + result = armv7_read_arm_instr_a8_add_register_arm(raw); else if ((op & b11110) == b01010) - result = armv7_read_arm_instr_adc_register(raw); + result = armv7_read_arm_instr_a8_adc_register(raw); else if ((op & b11110) == b01100) - result = armv7_read_arm_instr_sbc_register(raw); + result = armv7_read_arm_instr_a8_sbc_register(raw); else if ((op & b11110) == b01110) - result = armv7_read_arm_instr_rsc_register(raw); + result = armv7_read_arm_instr_a8_rsc_register(raw); /* else if ((op & b11001) == b10000) @@ -354,55 +354,55 @@ static GArchInstruction *process_armv7_arm_data_processing_register(uint32_t raw */ else if (op == b10001) - result = armv7_read_arm_instr_tst_register(raw); + result = armv7_read_arm_instr_a8_tst_register(raw); else if (op == b10011) - result = armv7_read_arm_instr_teq_register(raw); + result = armv7_read_arm_instr_a8_teq_register(raw); else if (op == b10101) - result = armv7_read_arm_instr_cmp_register(raw); + result = armv7_read_arm_instr_a8_cmp_register(raw); else if (op == b10111) - result = armv7_read_arm_instr_cmn_register(raw); + result = armv7_read_arm_instr_a8_cmn_register(raw); else if ((op & b11110) == b11000) - result = armv7_read_arm_instr_orr_register(raw); + result = armv7_read_arm_instr_a8_orr_register(raw); else if ((op & b11110) == b11010) { if (op2 == b00) { if (imm5 == b00000) - result = armv7_read_arm_instr_mov_register_arm(raw); + result = armv7_read_arm_instr_a8_mov_register_arm(raw); else - result = armv7_read_arm_instr_lsl_immediate(raw); + result = armv7_read_arm_instr_a8_lsl_immediate(raw); } else if (op2 == b01) - result = armv7_read_arm_instr_lsr_immediate(raw); + result = armv7_read_arm_instr_a8_lsr_immediate(raw); else if (op2 == b10) - result = armv7_read_arm_instr_asr_immediate(raw); + result = armv7_read_arm_instr_a8_asr_immediate(raw); else if (op2 == b11) { if (imm5 == b00000) - result = armv7_read_arm_instr_rrx(raw); + result = armv7_read_arm_instr_a8_rrx(raw); else - result = armv7_read_arm_instr_ror_immediate(raw); + result = armv7_read_arm_instr_a8_ror_immediate(raw); } } else if ((op & b11110) == b11100) - result = armv7_read_arm_instr_bic_register(raw); + result = armv7_read_arm_instr_a8_bic_register(raw); else if ((op & b11110) == b11110) - result = armv7_read_arm_instr_mvn_register(raw); + result = armv7_read_arm_instr_a8_mvn_register(raw); return result; @@ -440,28 +440,28 @@ static GArchInstruction *process_armv7_arm_data_processing_register_shifted_regi op2 = (raw >> 5) & 0x3; if ((op1 & b11110) == b00000) - result = armv7_read_arm_instr_and_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_and_register_shifted_register(raw); else if ((op1 & b11110) == b00010) - result = armv7_read_arm_instr_eor_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_eor_register_shifted_register(raw); else if ((op1 & b11110) == b00100) - result = armv7_read_arm_instr_sub_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_sub_register_shifted_register(raw); else if ((op1 & b11110) == b00110) - result = armv7_read_arm_instr_rsb_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_rsb_register_shifted_register(raw); else if ((op1 & b11110) == b01000) - result = armv7_read_arm_instr_add_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_add_register_shifted_register(raw); else if ((op1 & b11110) == b01010) - result = armv7_read_arm_instr_adc_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_adc_register_shifted_register(raw); else if ((op1 & b11110) == b01100) - result = armv7_read_arm_instr_sbc_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_sbc_register_shifted_register(raw); else if ((op1 & b11110) == b01110) - result = armv7_read_arm_instr_rsc_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_rsc_register_shifted_register(raw); #if 0 else if ((op1 & b11001) == b10000) @@ -469,41 +469,41 @@ static GArchInstruction *process_armv7_arm_data_processing_register_shifted_regi #endif else if (op1 == b10001) - result = armv7_read_arm_instr_tst_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_tst_register_shifted_register(raw); else if (op1 == b10011) - result = armv7_read_arm_instr_teq_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_teq_register_shifted_register(raw); else if (op1 == b10101) - result = armv7_read_arm_instr_cmp_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_cmp_register_shifted_register(raw); else if (op1 == b10111) - result = armv7_read_arm_instr_cmn_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_cmn_register_shifted_register(raw); else if ((op1 & b11110) == b11000) - result = armv7_read_arm_instr_orr_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_orr_register_shifted_register(raw); else if ((op1 & b11110) == b11010) { if (op2 == b00) - result = armv7_read_arm_instr_lsl_register(raw); + result = armv7_read_arm_instr_a8_lsl_register(raw); else if (op2 == b01) - result = armv7_read_arm_instr_lsr_register(raw); + result = armv7_read_arm_instr_a8_lsr_register(raw); else if (op2 == b10) - result = armv7_read_arm_instr_asr_register(raw); + result = armv7_read_arm_instr_a8_asr_register(raw); else if (op2 == b11) - result = armv7_read_arm_instr_ror_register(raw); + result = armv7_read_arm_instr_a8_ror_register(raw); } else if ((op1 & b11110) == b11100) - result = armv7_read_arm_instr_bic_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_bic_register_shifted_register(raw); else if ((op1 & b11110) == b11110) - result = armv7_read_arm_instr_mvn_register_shifted_register(raw); + result = armv7_read_arm_instr_a8_mvn_register_shifted_register(raw); return result; @@ -541,42 +541,42 @@ static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t ra rn = (raw >> 16) & 0xf; if ((op & b11110) == b00000) - result = armv7_read_arm_instr_and_immediate(raw); + result = armv7_read_arm_instr_a8_and_immediate(raw); else if ((op & b11110) == b00010) - result = armv7_read_arm_instr_eor_immediate(raw); + result = armv7_read_arm_instr_a8_eor_immediate(raw); else if ((op & b11110) == b00100) { if (rn == b1111) - result = armv7_read_arm_instr_adr(raw); + result = armv7_read_arm_instr_a8_adr(raw); else - result = armv7_read_arm_instr_sub_immediate_arm(raw); + result = armv7_read_arm_instr_a8_sub_immediate_arm(raw); } else if ((op & b11110) == b00110) - result = armv7_read_arm_instr_rsb_immediate(raw); + result = armv7_read_arm_instr_a8_rsb_immediate(raw); else if ((op & b11110) == b01000) { if (rn == b1111) - result = armv7_read_arm_instr_adr(raw); + result = armv7_read_arm_instr_a8_adr(raw); else - result = armv7_read_arm_instr_add_immediate_arm(raw); + result = armv7_read_arm_instr_a8_add_immediate_arm(raw); } else if ((op & b11110) == b01010) - result = armv7_read_arm_instr_adc_immediate(raw); + result = armv7_read_arm_instr_a8_adc_immediate(raw); else if ((op & b11110) == b01100) - result = armv7_read_arm_instr_sbc_immediate(raw); + result = armv7_read_arm_instr_a8_sbc_immediate(raw); else if ((op & b11110) == b01110) - result = armv7_read_arm_instr_rsc_immediate(raw); + result = armv7_read_arm_instr_a8_rsc_immediate(raw); /* else if ((op & b11110) == b10000) @@ -584,28 +584,28 @@ static GArchInstruction *process_armv7_arm_data_processing_immediate(uint32_t ra */ else if (op == b10001) - result = armv7_read_arm_instr_tst_immediate(raw); + result = armv7_read_arm_instr_a8_tst_immediate(raw); else if (op == b10011) - result = armv7_read_arm_instr_teq_immediate(raw); + result = armv7_read_arm_instr_a8_teq_immediate(raw); else if (op == b10101) - result = armv7_read_arm_instr_cmp_immediate(raw); + result = armv7_read_arm_instr_a8_cmp_immediate(raw); else if (op == b10111) - result = armv7_read_arm_instr_cmn_immediate(raw); + result = armv7_read_arm_instr_a8_cmn_immediate(raw); else if ((op & b11110) == b11000) - result = armv7_read_arm_instr_orr_immediate(raw); + result = armv7_read_arm_instr_a8_orr_immediate(raw); else if ((op & b11110) == b11010) - result = armv7_read_arm_instr_mov_immediate(raw); + result = armv7_read_arm_instr_a8_mov_immediate(raw); else if ((op & b11110) == b11100) - result = armv7_read_arm_instr_bic_immediate(raw); + result = armv7_read_arm_instr_a8_bic_immediate(raw); else if ((op & b11110) == b11110) - result = armv7_read_arm_instr_mvn_immediate(raw); + result = armv7_read_arm_instr_a8_mvn_immediate(raw); return result; @@ -641,34 +641,34 @@ static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint op = (raw >> 20) & 0xf; if ((op & b1110) == b0000) - result = armv7_read_arm_instr_mul(raw); + result = armv7_read_arm_instr_a8_mul(raw); else if ((op & b1110) == b0010) - result = armv7_read_arm_instr_mla(raw); + result = armv7_read_arm_instr_a8_mla(raw); else if (op == b0100) - result = armv7_read_arm_instr_umaal(raw); + result = armv7_read_arm_instr_a8_umaal(raw); else if (op == b0101) result = NULL; /* Non défini */ else if (op == b0110) - result = armv7_read_arm_instr_mls(raw); + result = armv7_read_arm_instr_a8_mls(raw); else if (op == b0111) result = NULL; /* Non défini */ else if ((op & b1110) == b1000) - result = armv7_read_arm_instr_umull(raw); + result = armv7_read_arm_instr_a8_umull(raw); else if ((op & b1110) == b1010) - result = armv7_read_arm_instr_umlal(raw); + result = armv7_read_arm_instr_a8_umlal(raw); else if ((op & b1110) == b1100) - result = armv7_read_arm_instr_smull(raw); + result = armv7_read_arm_instr_a8_smull(raw); else if ((op & b1110) == b1110) - result = armv7_read_arm_instr_smlal(raw); + result = armv7_read_arm_instr_a8_smlal(raw); return result; @@ -704,16 +704,16 @@ static GArchInstruction *process_armv7_arm_saturating_addition_and_subtraction(u op = (raw >> 21) & 0x3; if (op == b00) - result = armv7_read_arm_instr_qadd(raw); + result = armv7_read_arm_instr_a8_qadd(raw); else if (op == b01) - result = armv7_read_arm_instr_qsub(raw); + result = armv7_read_arm_instr_a8_qsub(raw); else if (op == b10) - result = armv7_read_arm_instr_qdadd(raw); + result = armv7_read_arm_instr_a8_qdadd(raw); else if (op == b11) - result = armv7_read_arm_instr_qdsub(raw); + result = armv7_read_arm_instr_a8_qdsub(raw); return result; @@ -751,23 +751,23 @@ static GArchInstruction *process_armv7_arm_halfword_multiply_and_multiply_accumu op = (raw >> 5) & 0x1; if (op1 == b00) - result = armv7_read_arm_instr_smlabb_smlabt_smlatb_smlatt(raw); + result = armv7_read_arm_instr_a8_smlabb_smlabt_smlatb_smlatt(raw); else if (op1 == b01) { if (op == b0) - result = armv7_read_arm_instr_smlawb_smlawt(raw); + result = armv7_read_arm_instr_a8_smlawb_smlawt(raw); else/* if (op == b1)*/ - result = armv7_read_arm_instr_smulwb_smulwt(raw); + result = armv7_read_arm_instr_a8_smulwb_smulwt(raw); } else if (op1 == b10) - result = armv7_read_arm_instr_smlalbb_smlalbt_smlaltb_smlaltt(raw); + result = armv7_read_arm_instr_a8_smlalbb_smlalbt_smlaltb_smlaltt(raw); else if (op1 == b11) - result = armv7_read_arm_instr_smulbb_smulbt_smultb_smultt(raw); + result = armv7_read_arm_instr_a8_smulbb_smulbt_smultb_smultt(raw); return result; @@ -809,21 +809,21 @@ static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_ if (op2 == b01) { if ((op1 & b00101) == b00000) - result = armv7_read_arm_instr_strh_register(raw); + result = armv7_read_arm_instr_a8_strh_register(raw); else if ((op1 & b00101) == b00001) - result = armv7_read_arm_instr_ldrh_register(raw); + result = armv7_read_arm_instr_a8_ldrh_register(raw); else if ((op1 & b00101) == b00100) - result = armv7_read_arm_instr_strh_immediate_arm(raw); + result = armv7_read_arm_instr_a8_strh_immediate_arm(raw); else/* if ((op1 & b00101) == b00101)*/ { if (rn == b1111) - result = armv7_read_arm_instr_ldrh_literal(raw); + result = armv7_read_arm_instr_a8_ldrh_literal(raw); else - result = armv7_read_arm_instr_ldrh_immediate_arm(raw); + result = armv7_read_arm_instr_a8_ldrh_immediate_arm(raw); } @@ -832,28 +832,28 @@ static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_ else if (op2 == b10) { if ((op1 & b00101) == b00000) - result = armv7_read_arm_instr_ldrd_register(raw); + result = armv7_read_arm_instr_a8_ldrd_register(raw); else if ((op1 & b00101) == b00001) - result = armv7_read_arm_instr_ldrsb_register(raw); + result = armv7_read_arm_instr_a8_ldrsb_register(raw); else if ((op1 & b00101) == b00100) { if (rn == b1111) - result = armv7_read_arm_instr_ldrd_literal(raw); + result = armv7_read_arm_instr_a8_ldrd_literal(raw); else - result = armv7_read_arm_instr_ldrd_immediate(raw); + result = armv7_read_arm_instr_a8_ldrd_immediate(raw); } else/* if ((op1 & b00101) == b00101)*/ { if (rn == b1111) - result = armv7_read_arm_instr_ldrsb_literal(raw); + result = armv7_read_arm_instr_a8_ldrsb_literal(raw); else - result = armv7_read_arm_instr_ldrsb_immediate(raw); + result = armv7_read_arm_instr_a8_ldrsb_immediate(raw); } @@ -862,21 +862,21 @@ static GArchInstruction *process_armv7_arm_extra_load_store_instructions(uint32_ else if (op2 == b11) { if ((op1 & b00101) == b00000) - result = armv7_read_arm_instr_strd_register(raw); + result = armv7_read_arm_instr_a8_strd_register(raw); else if ((op1 & b00101) == b00001) - result = armv7_read_arm_instr_ldrsh_register(raw); + result = armv7_read_arm_instr_a8_ldrsh_register(raw); else if ((op1 & b00101) == b00100) - result = armv7_read_arm_instr_strd_immediate(raw); + result = armv7_read_arm_instr_a8_strd_immediate(raw); else/* if ((op1 & b00101) == b00101)*/ { if (rn == b1111) - result = armv7_read_arm_instr_ldrsh_literal(raw); + result = armv7_read_arm_instr_a8_ldrsh_literal(raw); else - result = armv7_read_arm_instr_ldrsh_immediate(raw); + result = armv7_read_arm_instr_a8_ldrsh_immediate(raw); } @@ -920,24 +920,24 @@ static GArchInstruction *process_armv7_arm_extra_load_store_instructions_unprivi if (op2 == b01) { if (op == b0) - result = armv7_read_arm_instr_strht(raw); + result = armv7_read_arm_instr_a8_strht(raw); else/* if (op == b1)*/ - result = armv7_read_arm_instr_ldrht(raw); + result = armv7_read_arm_instr_a8_ldrht(raw); } else if (op2 == b10) { if (op == b1) - result = armv7_read_arm_instr_ldrsbt(raw); + result = armv7_read_arm_instr_a8_ldrsbt(raw); } else if (op2 == b11) { if (op == b1) - result = armv7_read_arm_instr_ldrsht(raw); + result = armv7_read_arm_instr_a8_ldrsht(raw); } @@ -975,31 +975,31 @@ static GArchInstruction *process_armv7_arm_synchronization_primitives(uint32_t r op = (raw >> 20) & 0xf; if ((op & b1011) == b0000) - result = armv7_read_arm_instr_swp_swpb(raw); + result = armv7_read_arm_instr_a8_swp_swpb(raw); else if (op == b1000) - result = armv7_read_arm_instr_strex(raw); + result = armv7_read_arm_instr_a8_strex(raw); else if (op == b1001) - result = armv7_read_arm_instr_ldrex(raw); + result = armv7_read_arm_instr_a8_ldrex(raw); else if (op == b1010) - result = armv7_read_arm_instr_strexd(raw); + result = armv7_read_arm_instr_a8_strexd(raw); else if (op == b1011) - result = armv7_read_arm_instr_ldrexd(raw); + result = armv7_read_arm_instr_a8_ldrexd(raw); else if (op == b1100) - result = armv7_read_arm_instr_strexb(raw); + result = armv7_read_arm_instr_a8_strexb(raw); else if (op == b1101) - result = armv7_read_arm_instr_ldrexb(raw); + result = armv7_read_arm_instr_a8_ldrexb(raw); else if (op == b1110) - result = armv7_read_arm_instr_strexh(raw); + result = armv7_read_arm_instr_a8_strexh(raw); else if (op == b1111) - result = armv7_read_arm_instr_ldrexh(raw); + result = armv7_read_arm_instr_a8_ldrexh(raw); return result; @@ -1043,35 +1043,35 @@ static GArchInstruction *process_armv7_arm_msr_immediate_and_hints(uint32_t raw) if (op1 == b0000) { if (op2 == b00000000) - result = armv7_read_arm_instr_nop(raw); + result = armv7_read_arm_instr_a8_nop(raw); else if (op2 == b00000001) - result = armv7_read_arm_instr_yield(raw); + result = armv7_read_arm_instr_a8_yield(raw); else if (op2 == b00000010) - result = armv7_read_arm_instr_wfe(raw); + result = armv7_read_arm_instr_a8_wfe(raw); else if (op2 == b00000011) - result = armv7_read_arm_instr_wfi(raw); + result = armv7_read_arm_instr_a8_wfi(raw); else if (op2 == b00000100) - result = armv7_read_arm_instr_sev(raw); + result = armv7_read_arm_instr_a8_sev(raw); else if ((op2 & b11110000) == b11110000) - result = armv7_read_arm_instr_dbg(raw); + result = armv7_read_arm_instr_a8_dbg(raw); } else if (op1 == b0100 || (op1 & b1011) == b1000) - result = armv7_read_arm_instr_msr_immediate_a8(raw); + result = armv7_read_arm_instr_a8_msr_immediate(raw); else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010) - result = armv7_read_arm_instr_msr_immediate_b9(raw); + result = armv7_read_arm_instr_b9_msr_immediate(raw); } else/* if (op == b1)*/ - result = armv7_read_arm_instr_msr_immediate_b9(raw); + result = armv7_read_arm_instr_b9_msr_immediate(raw); return result; @@ -1117,29 +1117,29 @@ static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t r if (b == b1) { if ((op & b01) == b00) - result = armv7_read_arm_instr_mrs_banked_register(raw); + result = armv7_read_arm_instr_b9_mrs_banked_register(raw); else/* if ((op & b01) == b01)*/ - result = armv7_read_arm_instr_msr_banked_register(raw); + result = armv7_read_arm_instr_b9_msr_banked_register(raw); } else/* if (b == b0)*/ { if ((op & b01) == b00) - result = armv7_read_arm_instr_mrs(raw); + result = armv7_read_arm_instr_a8_mrs(raw); /* B9 ? */ else if (op == b01) { if ((op1 & b0011) == b0000) - result = armv7_read_arm_instr_msr_register_a8(raw); + result = armv7_read_arm_instr_a8_msr_register(raw); else if ((op1 & b0011) == b0001 || (op1 & b0010) == b0010) - result = armv7_read_arm_instr_msr_register_b9(raw); + result = armv7_read_arm_instr_b9_msr_register(raw); } else if (op == b11) - result = armv7_read_arm_instr_msr_register_b9(raw); + result = armv7_read_arm_instr_b9_msr_register(raw); } @@ -1148,24 +1148,24 @@ static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t r else if (op2 == b001) { if (op == b01) - result = armv7_read_arm_instr_bx(raw); + result = armv7_read_arm_instr_a8_bx(raw); else if (op == b11) - result = armv7_read_arm_instr_clz(raw); + result = armv7_read_arm_instr_a8_clz(raw); } else if (op2 == b010) { if (op == b01) - result = armv7_read_arm_instr_bxj(raw); + result = armv7_read_arm_instr_a8_bxj(raw); } else if (op2 == b011) { if (op == b01) - result = armv7_read_arm_instr_blx_register(raw); + result = armv7_read_arm_instr_a8_blx_register(raw); } @@ -1175,20 +1175,20 @@ static GArchInstruction *process_armv7_arm_miscellaneous_instructions(uint32_t r else if (op2 == b110) { if (op == b11) - result = armv7_read_arm_instr_eret(raw); + result = armv7_read_arm_instr_b9_eret(raw); } else if (op2 == b111) { if (op == b) - result = armv7_read_arm_instr_bkpt(raw); + result = armv7_read_arm_instr_a8_bkpt(raw); else if (op == b) - result = armv7_read_arm_instr_hvc(raw); + result = armv7_read_arm_instr_b9_hvc(raw); else if (op == b) - result = armv7_read_arm_instr_smc_previously_smi(raw); + result = armv7_read_arm_instr_b9_smc_previously_smi(raw); } @@ -1234,65 +1234,65 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin if (a == b0) { if ((op1 & b00101) == b00000 && (op1 & b10111) != b00010) - result = armv7_read_arm_instr_str_immediate_arm(raw); + result = armv7_read_arm_instr_a8_str_immediate_arm(raw); else if ((op1 & b10111) == b00010) - result = armv7_read_arm_instr_strt(raw); + result = armv7_read_arm_instr_a8_strt(raw); else if ((op1 & b00101) == b00001 && (op1 & b10111) != b00011) { if (rn != b1111) - result = armv7_read_arm_instr_ldr_immediate_arm(raw); + result = armv7_read_arm_instr_a8_ldr_immediate_arm(raw); else - result = armv7_read_arm_instr_ldr_literal(raw); + result = armv7_read_arm_instr_a8_ldr_literal(raw); } else if ((op1 & b10111) == b00011) - result = armv7_read_arm_instr_ldrt(raw); + result = armv7_read_arm_instr_a8_ldrt(raw); else if ((op1 & b00101) == b00100 && (op1 & b10110) != b00110) - result = armv7_read_arm_instr_strb_immediate_arm(raw); + result = armv7_read_arm_instr_a8_strb_immediate_arm(raw); else if ((op1 & b10110) == b00110) - result = armv7_read_arm_instr_strbt(raw); + result = armv7_read_arm_instr_a8_strbt(raw); else if ((op1 & b00101) == b00101 && (op1 & b10111) != b00111) { if (rn != b1111) - result = armv7_read_arm_instr_ldrb_immediate_arm(raw); + result = armv7_read_arm_instr_a8_ldrb_immediate_arm(raw); else - result = armv7_read_arm_instr_ldrb_literal(raw); + result = armv7_read_arm_instr_a8_ldrb_literal(raw); } else if ((op1 & b10111) == b00111) - result = armv7_read_arm_instr_ldrbt(raw); + result = armv7_read_arm_instr_a8_ldrbt(raw); } else /*if (a == b1)*/ { if ((op1 & b00101) == b00000 && (op1 & b10111) != b00010 && b == b0) - result = armv7_read_arm_instr_str_register(raw); + result = armv7_read_arm_instr_a8_str_register(raw); else if ((op1 & b10111) == b00010 && b == b0) - result = armv7_read_arm_instr_strt(raw); + result = armv7_read_arm_instr_a8_strt(raw); else if ((op1 & b00101) == b00001 && (op1 & b10111) != b00011 && b == b0) - result = armv7_read_arm_instr_ldr_register_arm(raw); + result = armv7_read_arm_instr_a8_ldr_register_arm(raw); else if ((op1 & b10111) == b00011 && b == b0) - result = armv7_read_arm_instr_ldrt(raw); + result = armv7_read_arm_instr_a8_ldrt(raw); else if ((op1 & b00101) == b00100 && (op1 & b10110) != b00110 && b == b0) - result = armv7_read_arm_instr_strb_register(raw); + result = armv7_read_arm_instr_a8_strb_register(raw); else if ((op1 & b10110) == b00110 && b == b0) - result = armv7_read_arm_instr_strbt(raw); + result = armv7_read_arm_instr_a8_strbt(raw); else if ((op1 & b00101) == b00101 && (op1 & b10111) != b00111 && b == b0) - result = armv7_read_arm_instr_ldrb_register(raw); + result = armv7_read_arm_instr_a8_ldrb_register(raw); else if ((op1 & b10111) == b00111 && b == b0) - result = armv7_read_arm_instr_ldrbt(raw); + result = armv7_read_arm_instr_a8_ldrbt(raw); } @@ -1354,9 +1354,9 @@ static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw) if (op2 == b000) { if (rd == b1111) - result = armv7_read_arm_instr_usad8(raw); + result = armv7_read_arm_instr_a8_usad8(raw); else - result = armv7_read_arm_instr_usada8(raw); + result = armv7_read_arm_instr_a8_usada8(raw); } goto a54_done; @@ -1366,7 +1366,7 @@ static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw) else if ((op1 & b11110) == b11010) { if ((op2 & b011) == b010) - result = armv7_read_arm_instr_sbfx(raw); + result = armv7_read_arm_instr_a8_sbfx(raw); goto a54_done; @@ -1377,9 +1377,9 @@ static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw) if ((op2 & b011) == b000) { if (rn == b1111) - result = armv7_read_arm_instr_bfc(raw); + result = armv7_read_arm_instr_a8_bfc(raw); else - result = armv7_read_arm_instr_bfi(raw); + result = armv7_read_arm_instr_a8_bfi(raw); } goto a54_done; @@ -1389,14 +1389,14 @@ static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw) else if ((op1 & b11110) == b11110) { if ((op2 & b011) == b010) - result = armv7_read_arm_instr_ubfx(raw); + result = armv7_read_arm_instr_a8_ubfx(raw); goto a54_done; } else if (op1 == b11111 && op2 == b111 && cond == b1110) - result = armv7_read_arm_instr_ubfx(raw); + result = armv7_read_arm_instr_a8_udf(raw); a54_done: @@ -1438,66 +1438,66 @@ static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_sig if (op1 == b01) { if (op2 == b000) - result = armv7_read_arm_instr_sadd16(raw); + result = armv7_read_arm_instr_a8_sadd16(raw); else if (op2 == b001) - result = armv7_read_arm_instr_sasx(raw); + result = armv7_read_arm_instr_a8_sasx(raw); else if (op2 == b010) - result = armv7_read_arm_instr_ssax(raw); + result = armv7_read_arm_instr_a8_ssax(raw); else if (op2 == b011) - result = armv7_read_arm_instr_ssub16(raw); + result = armv7_read_arm_instr_a8_ssub16(raw); else if (op2 == b100) - result = armv7_read_arm_instr_sadd8(raw); + result = armv7_read_arm_instr_a8_sadd8(raw); else if (op2 == b111) - result = armv7_read_arm_instr_ssub8(raw); + result = armv7_read_arm_instr_a8_ssub8(raw); } else if (op1 == b10) { if (op2 == b000) - result = armv7_read_arm_instr_qadd16(raw); + result = armv7_read_arm_instr_a8_qadd16(raw); else if (op2 == b001) - result = armv7_read_arm_instr_qasx(raw); + result = armv7_read_arm_instr_a8_qasx(raw); else if (op2 == b010) - result = armv7_read_arm_instr_qsax(raw); + result = armv7_read_arm_instr_a8_qsax(raw); else if (op2 == b011) - result = armv7_read_arm_instr_qsub16(raw); + result = armv7_read_arm_instr_a8_qsub16(raw); else if (op2 == b100) - result = armv7_read_arm_instr_qadd8(raw); + result = armv7_read_arm_instr_a8_qadd8(raw); else if (op2 == b111) - result = armv7_read_arm_instr_qsub8(raw); + result = armv7_read_arm_instr_a8_qsub8(raw); } else if (op1 == b11) { if (op2 == b000) - result = armv7_read_arm_instr_shadd16(raw); + result = armv7_read_arm_instr_a8_shadd16(raw); else if (op2 == b001) - result = armv7_read_arm_instr_shasx(raw); + result = armv7_read_arm_instr_a8_shasx(raw); else if (op2 == b010) - result = armv7_read_arm_instr_shsax(raw); + result = armv7_read_arm_instr_a8_shsax(raw); else if (op2 == b011) - result = armv7_read_arm_instr_shsub16(raw); + result = armv7_read_arm_instr_a8_shsub16(raw); else if (op2 == b100) - result = armv7_read_arm_instr_shadd8(raw); + result = armv7_read_arm_instr_a8_shadd8(raw); else if (op2 == b111) - result = armv7_read_arm_instr_shsub8(raw); + result = armv7_read_arm_instr_a8_shsub8(raw); } @@ -1539,66 +1539,66 @@ static GArchInstruction *process_armv7_arm_parallel_addition_and_subtraction_uns if (op1 == b01) { if (op2 == b000) - result = armv7_read_arm_instr_uadd16(raw); + result = armv7_read_arm_instr_a8_uadd16(raw); else if (op2 == b001) - result = armv7_read_arm_instr_uasx(raw); + result = armv7_read_arm_instr_a8_uasx(raw); else if (op2 == b010) - result = armv7_read_arm_instr_usax(raw); + result = armv7_read_arm_instr_a8_usax(raw); else if (op2 == b011) - result = armv7_read_arm_instr_usub16(raw); + result = armv7_read_arm_instr_a8_usub16(raw); else if (op2 == b100) - result = armv7_read_arm_instr_uadd8(raw); + result = armv7_read_arm_instr_a8_uadd8(raw); else if (op2 == b111) - result = armv7_read_arm_instr_usub8(raw); + result = armv7_read_arm_instr_a8_usub8(raw); } else if (op1 == b10) { if (op2 == b000) - result = armv7_read_arm_instr_uqadd16(raw); + result = armv7_read_arm_instr_a8_uqadd16(raw); else if (op2 == b001) - result = armv7_read_arm_instr_uqasx(raw); + result = armv7_read_arm_instr_a8_uqasx(raw); else if (op2 == b010) - result = armv7_read_arm_instr_uqsax(raw); + result = armv7_read_arm_instr_a8_uqsax(raw); else if (op2 == b011) - result = armv7_read_arm_instr_uqsub16(raw); + result = armv7_read_arm_instr_a8_uqsub16(raw); else if (op2 == b100) - result = armv7_read_arm_instr_uqadd8(raw); + result = armv7_read_arm_instr_a8_uqadd8(raw); else if (op2 == b111) - result = armv7_read_arm_instr_uqsub8(raw); + result = armv7_read_arm_instr_a8_uqsub8(raw); } else if (op1 == b11) { if (op2 == b000) - result = armv7_read_arm_instr_uhadd16(raw); + result = armv7_read_arm_instr_a8_uhadd16(raw); else if (op2 == b001) - result = armv7_read_arm_instr_uhasx(raw); + result = armv7_read_arm_instr_a8_uhasx(raw); else if (op2 == b010) - result = armv7_read_arm_instr_uhsax(raw); + result = armv7_read_arm_instr_a8_uhsax(raw); else if (op2 == b011) - result = armv7_read_arm_instr_uhsub16(raw); + result = armv7_read_arm_instr_a8_uhsub16(raw); else if (op2 == b100) - result = armv7_read_arm_instr_uhadd8(raw); + result = armv7_read_arm_instr_a8_uhadd8(raw); else if (op2 == b111) - result = armv7_read_arm_instr_uhsub8(raw); + result = armv7_read_arm_instr_a8_uhsub8(raw); } @@ -1643,32 +1643,32 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve { if ((op2 & b001) == b000) { - result = armv7_read_arm_instr_pkh(raw); + result = armv7_read_arm_instr_a8_pkh(raw); goto a543_done; } else if (op2 == b011) { if (a == b1111) { - result = armv7_read_arm_instr_sxtb16(raw); + result = armv7_read_arm_instr_a8_sxtb16(raw); goto a543_done; } else { - result = armv7_read_arm_instr_sxtab16(raw); + result = armv7_read_arm_instr_a8_sxtab16(raw); goto a543_done; } } else if (op2 == b101) { - result = armv7_read_arm_instr_sel(raw); + result = armv7_read_arm_instr_a8_sel(raw); goto a543_done; } } else if ((op1 & b110) == b010 && (op2 & b001) == b000) { - result = armv7_read_arm_instr_ssat(raw); + result = armv7_read_arm_instr_a8_ssat(raw); goto a543_done; } @@ -1676,19 +1676,19 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve { if (op2 == b001) { - result = armv7_read_arm_instr_ssat16(raw); + result = armv7_read_arm_instr_a8_ssat16(raw); goto a543_done; } else if (op2 == b011) { if (a == b1111) { - result = armv7_read_arm_instr_sxtb(raw); + result = armv7_read_arm_instr_a8_sxtb(raw); goto a543_done; } else { - result = armv7_read_arm_instr_sxtab(raw); + result = armv7_read_arm_instr_a8_sxtab(raw); goto a543_done; } } @@ -1698,25 +1698,25 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve { if (op2 == b001) { - result = armv7_read_arm_instr_rev(raw); + result = armv7_read_arm_instr_a8_rev(raw); goto a543_done; } else if (op2 == b011) { if (a == b1111) { - result = armv7_read_arm_instr_sxth(raw); + result = armv7_read_arm_instr_a8_sxth(raw); goto a543_done; } else { - result = armv7_read_arm_instr_sxtah(raw); + result = armv7_read_arm_instr_a8_sxtah(raw); goto a543_done; } } else if (op2 == b101) { - result = armv7_read_arm_instr_rev16(raw); + result = armv7_read_arm_instr_a8_rev16(raw); goto a543_done; } } @@ -1725,19 +1725,19 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve { if (a == b1111) { - result = armv7_read_arm_instr_uxtb16(raw); + result = armv7_read_arm_instr_a8_uxtb16(raw); goto a543_done; } else { - result = armv7_read_arm_instr_uxtab16(raw); + result = armv7_read_arm_instr_a8_uxtab16(raw); goto a543_done; } } else if ((op1 & b110) == b110 && (op2 & b001) == b000) { - result = armv7_read_arm_instr_usat(raw); + result = armv7_read_arm_instr_a8_usat(raw); goto a543_done; } @@ -1745,19 +1745,19 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve { if (op2 == b001) { - result = armv7_read_arm_instr_usat16(raw); + result = armv7_read_arm_instr_a8_usat16(raw); goto a543_done; } else if (op2 == b011) { if (a == b1111) { - result = armv7_read_arm_instr_uxtb(raw); + result = armv7_read_arm_instr_a8_uxtb(raw); goto a543_done; } else { - result = armv7_read_arm_instr_uxtab(raw); + result = armv7_read_arm_instr_a8_uxtab(raw); goto a543_done; } } @@ -1767,25 +1767,25 @@ static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reve { if (op2 == b001) { - result = armv7_read_arm_instr_rbit(raw); + result = armv7_read_arm_instr_a8_rbit(raw); goto a543_done; } else if (op2 == b011) { if (a == b1111) { - result = armv7_read_arm_instr_uxth(raw); + result = armv7_read_arm_instr_a8_uxth(raw); goto a543_done; } else { - result = armv7_read_arm_instr_uxtah(raw); + result = armv7_read_arm_instr_a8_uxtah(raw); goto a543_done; } } else if (op2 == b101) { - result = armv7_read_arm_instr_revsh(raw); + result = armv7_read_arm_instr_a8_revsh(raw); goto a543_done; } } @@ -1834,18 +1834,18 @@ static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_d if ((op2 & b110) == b000) { if (a != b1111) - result = armv7_read_arm_instr_smlad(raw); + result = armv7_read_arm_instr_a8_smlad(raw); else/* if (a == b1111)*/ - result = armv7_read_arm_instr_smuad(raw); + result = armv7_read_arm_instr_a8_smuad(raw); } else if ((op2 & b110) == b010) { if (a != b1111) - result = armv7_read_arm_instr_smlsd(raw); + result = armv7_read_arm_instr_a8_smlsd(raw); else/* if (a == b1111)*/ - result = armv7_read_arm_instr_smusd(raw); + result = armv7_read_arm_instr_a8_smusd(raw); } @@ -1854,24 +1854,24 @@ static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_d else if (op1 == b001) { if (op2 == b000) - result = armv7_read_arm_instr_sdiv(raw); + result = armv7_read_arm_instr_a8_sdiv(raw); } else if (op1 == b011) { if (op2 == b000) - result = armv7_read_arm_instr_udiv(raw); + result = armv7_read_arm_instr_a8_udiv(raw); } else if (op1 == b100) { if ((op2 & b110) == b000) - result = armv7_read_arm_instr_smlald(raw); + result = armv7_read_arm_instr_a8_smlald(raw); else if ((op2 & b110) == b010) - result = armv7_read_arm_instr_smlsld(raw); + result = armv7_read_arm_instr_a8_smlsld(raw); } @@ -1880,14 +1880,14 @@ static GArchInstruction *process_armv7_arm_signed_multiply_signed_and_unsigned_d if ((op2 & b110) == b000) { if (a != b1111) - result = armv7_read_arm_instr_smmla(raw); + result = armv7_read_arm_instr_a8_smmla(raw); else/* if (a == b1111)*/ - result = armv7_read_arm_instr_smmul(raw); + result = armv7_read_arm_instr_a8_smmul(raw); } else if ((op2 & b110) == b110) - result = armv7_read_arm_instr_smmls(raw); + result = armv7_read_arm_instr_a8_smmls(raw); } @@ -1929,61 +1929,61 @@ static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_dat r = (raw >> 15) & 0x1; if ((op & b111101) == b000000) - result = armv7_read_arm_instr_stmda_stmed(raw); + result = armv7_read_arm_instr_a8_stmda_stmed(raw); else if ((op & b111101) == b000001) - result = armv7_read_arm_instr_ldmda_ldmfa(raw); + result = armv7_read_arm_instr_a8_ldmda_ldmfa(raw); else if ((op & b111101) == b001000) - result = armv7_read_arm_instr_stm_stmia_stmea(raw); + result = armv7_read_arm_instr_a8_stm_stmia_stmea(raw); else if (op == b001001) - result = armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(raw); + result = armv7_read_arm_instr_a8_ldm_ldmia_ldmfd_arm(raw); else if (op == b001011) { if (rn != b1101) - result = armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(raw); + result = armv7_read_arm_instr_a8_ldm_ldmia_ldmfd_arm(raw); else /* if (rn == b1101) */ - result = armv7_read_arm_instr_pop_arm(raw); + result = armv7_read_arm_instr_a8_pop_arm(raw); } else if (op == b010000) - result = armv7_read_arm_instr_stmdb_stmfd(raw); + result = armv7_read_arm_instr_a8_stmdb_stmfd(raw); else if (op == b010010) { if (rn != b1101) - result = armv7_read_arm_instr_stmdb_stmfd(raw); + result = armv7_read_arm_instr_a8_stmdb_stmfd(raw); else /* if (rn == b1101) */ - result = armv7_read_arm_instr_push(raw); + result = armv7_read_arm_instr_a8_push(raw); } else if ((op & b111101) == b010001) - result = armv7_read_arm_instr_ldmdb_ldmea(raw); + result = armv7_read_arm_instr_a8_ldmdb_ldmea(raw); else if ((op & b111101) == b011000) - result = armv7_read_arm_instr_stmib_stmfa(raw); + result = armv7_read_arm_instr_a8_stmib_stmfa(raw); else if ((op & b111101) == b011001) - result = armv7_read_arm_instr_ldmib_ldmed(raw); + result = armv7_read_arm_instr_a8_ldmib_ldmed(raw); else if ((op & b100101) == b000100) - result = armv7_read_arm_instr_stm_user_registers(raw); + result = armv7_read_arm_instr_b9_stm_user_registers(raw); else if ((op & b100101) == b000101) { if (r == b0) - result = armv7_read_arm_instr_ldm_user_registers(raw); + result = armv7_read_arm_instr_b9_ldm_user_registers(raw); else /* if (r == b1) */ - result = armv7_read_arm_instr_ldm_exception_return(raw); + result = armv7_read_arm_instr_b9_ldm_exception_return(raw); } else if ((op & b110000) == b100000) - result = armv7_read_arm_instr_b(raw); + result = armv7_read_arm_instr_a8_b(raw); else if ((op & b110000) == b110000) - result = armv7_read_arm_instr_bl_blx_immediate(raw); + result = armv7_read_arm_instr_a8_bl_blx_immediate(raw); return result; @@ -2028,37 +2028,37 @@ static GArchInstruction *process_armv7_arm_coprocessor_instructions_and_supervis result = g_undef_instruction_new(IBS_UNDEFINED); else if ((op1 & b110000) == b110000) - result = armv7_read_arm_instr_svc_previously_swi(raw); + result = armv7_read_arm_instr_a8_svc_previously_swi(raw); else if ((coproc & b1110) != b1010) { if ((op1 & b100001) == b000000 && (op1 & b111011) != b000000) - result = armv7_read_arm_instr_stc_stc2(raw); + result = armv7_read_arm_instr_a8_stc_stc2(raw); else if ((op1 & b100001) == b000001 && (op1 & b111011) != b000001) { if (rn != b1111) - result = armv7_read_arm_instr_ldc_ldc2_immediate(raw); + result = armv7_read_arm_instr_a8_ldc_ldc2_immediate(raw); else - result = armv7_read_arm_instr_ldc_ldc2_literal(raw); + result = armv7_read_arm_instr_a8_ldc_ldc2_literal(raw); } else if (op1 == b000100) - result = armv7_read_arm_instr_mcrr_mcrr2(raw); + result = armv7_read_arm_instr_a8_mcrr_mcrr2(raw); else if (op1 == b000101) - result = armv7_read_arm_instr_mrrc_mrrc2(raw); + result = armv7_read_arm_instr_a8_mrrc_mrrc2(raw); else if ((op1 & b110000) == b100000 && op == b0) - result = armv7_read_arm_instr_cdp_cdp2(raw); + result = armv7_read_arm_instr_a8_cdp_cdp2(raw); else if ((op1 & b110001) == b100000 && op == b1) - result = armv7_read_arm_instr_mcr_mcr2(raw); + result = armv7_read_arm_instr_a8_mcr_mcr2(raw); else if ((op1 & b110001) == b100001 && op == b1) - result = armv7_read_arm_instr_mrc_mrc2(raw); + result = armv7_read_arm_instr_a8_mrc_mrc2(raw); } @@ -2109,39 +2109,39 @@ static GArchInstruction *process_armv7_arm_unconditional_instructions(uint32_t r result = process_armv7_arm_memory_hints_advanced_simd_instructions_and_miscellaneous_instructions(raw); else if ((op1 & b11100101) == b10000100) - result = armv7_read_arm_instr_srs_arm(raw); + result = armv7_read_arm_instr_b9_srs_arm(raw); else if ((op1 & b11100101) == b10000001) - result = armv7_read_arm_instr_rfe(raw); + result = armv7_read_arm_instr_b9_rfe(raw); else if ((op1 & b11100000) == b10100000) - result = armv7_read_arm_instr_bl_blx_immediate(raw); + result = armv7_read_arm_instr_a8_bl_blx_immediate(raw); else if ((op1 & b11100001) == b11000000 && (op1 & b11111011) != b11000000) - result = armv7_read_arm_instr_stc_stc2(raw); + result = armv7_read_arm_instr_a8_stc_stc2(raw); else if ((op1 & b11100001) == b11000001 && (op1 & b11111011) != b11000001) { if (rn != b1111) - result = armv7_read_arm_instr_ldc_ldc2_immediate(raw); + result = armv7_read_arm_instr_a8_ldc_ldc2_immediate(raw); else/* if (rn == b1111)*/ - result = armv7_read_arm_instr_ldc_ldc2_literal(raw); + result = armv7_read_arm_instr_a8_ldc_ldc2_literal(raw); } else if (op1 == b11000100) - result = armv7_read_arm_instr_mcrr_mcrr2(raw); + result = armv7_read_arm_instr_a8_mcrr_mcrr2(raw); else if (op1 == b11000101) - result = armv7_read_arm_instr_mrrc_mrrc2(raw); + result = armv7_read_arm_instr_a8_mrrc_mrrc2(raw); else if ((op1 & b11110000) == b11100000 && op == b0) - result = armv7_read_arm_instr_cdp_cdp2(raw); + result = armv7_read_arm_instr_a8_cdp_cdp2(raw); else if ((op1 & b11110001) == b11100000 && op == b1) - result = armv7_read_arm_instr_mcr_mcr2(raw); + result = armv7_read_arm_instr_a8_mcr_mcr2(raw); else if ((op1 & b11110001) == b11100001 && op == b1) - result = armv7_read_arm_instr_mrc_mrc2(raw); + result = armv7_read_arm_instr_a8_mrc_mrc2(raw); return result; @@ -2183,10 +2183,10 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio if (op1 == b0010000) { if ((op2 & b0010) == b0000 && (rn & b0001) == b0000) - result = armv7_read_arm_instr_cps_arm(raw); + result = armv7_read_arm_instr_b9_cps_arm(raw); else if (op2 == b0000 && (rn & b0001) == b0001) - result = armv7_read_arm_instr_cps_arm(raw); + result = armv7_read_arm_instr_a8_setend(raw); } @@ -2200,7 +2200,7 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio result = g_undef_instruction_new(IBS_NOP); else if ((op1 & b1110111) == b1000101) - result = armv7_read_arm_instr_pli_immediate_literal(raw); + result = armv7_read_arm_instr_a8_pli_immediate_literal(raw); else if ((op1 & b1110011) == b1000011) result = g_undef_instruction_new(IBS_UNPREDICTABLE); @@ -2208,7 +2208,7 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio else if ((op1 & b1110111) == b1010101) { if (rn != b1111) - result = armv7_read_arm_instr_pld_pldw_immediate(raw); + result = armv7_read_arm_instr_a8_pld_pldw_immediate(raw); else result = g_undef_instruction_new(IBS_UNPREDICTABLE); @@ -2217,9 +2217,9 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio else if ((op1 & b1110111) == b1010101) { if (rn != b1111) - result = armv7_read_arm_instr_pld_pldw_immediate(raw); + result = armv7_read_arm_instr_a8_pld_pldw_immediate(raw); else - result = armv7_read_arm_instr_pld_literal(raw); + result = armv7_read_arm_instr_a8_pld_literal(raw); } @@ -2232,19 +2232,19 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if (op2 == b0001) - result = armv7_read_arm_instr_clrex(raw); + result = armv7_read_arm_instr_a8_clrex(raw); else if ((op2 & b1110) == b0010) result = g_undef_instruction_new(IBS_UNPREDICTABLE); else if (op2 == b0100) - result = armv7_read_arm_instr_dsb(raw); + result = armv7_read_arm_instr_a8_dsb(raw); else if (op2 == b0101) - result = armv7_read_arm_instr_dmb(raw); + result = armv7_read_arm_instr_a8_dmb(raw); else if (op2 == b0110) - result = armv7_read_arm_instr_isb(raw); + result = armv7_read_arm_instr_a8_isb(raw); else if (op2 == b0111) result = g_undef_instruction_new(IBS_UNPREDICTABLE); @@ -2261,10 +2261,10 @@ static GArchInstruction *process_armv7_arm_memory_hints_advanced_simd_instructio result = g_undef_instruction_new(IBS_NOP); else if ((op1 & b1110111) == b1100101 && (op2 & b0001) == b0000) - result = armv7_read_arm_instr_pli_register(raw); + result = armv7_read_arm_instr_a8_pli_register(raw); else if ((op1 & b1110111) == b1110001 && (op2 & b0001) == b0000) - result = armv7_read_arm_instr_pld_pldw_register(raw); + result = armv7_read_arm_instr_a8_pld_pldw_register(raw); return result; diff --git a/plugins/arm/v7/core.c b/plugins/arm/v7/core.c index cd5cdd8..5fd355c 100644 --- a/plugins/arm/v7/core.c +++ b/plugins/arm/v7/core.c @@ -30,6 +30,7 @@ #include "instruction.h" #include "processor.h" #include "operands/estate.h" +#include "operands/iflags.h" #include "operands/it.h" #include "operands/limitation.h" #include "operands/maccess.h" @@ -68,6 +69,7 @@ static void register_armv7_gtypes(void) g_type_ensure(G_TYPE_ARMV7_INSTRUCTION); g_type_ensure(G_TYPE_ARMV7_ENDIAN_OPERAND); + g_type_ensure(G_TYPE_ARMV7_IFLAGS_OPERAND); g_type_ensure(G_TYPE_ARMV7_ITCOND_OPERAND); g_type_ensure(G_TYPE_ARMV7_LIMITATION_OPERAND); g_type_ensure(G_TYPE_ARMV7_MACCESS_OPERAND); diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index d41f6e8..ad23bc7 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -31,12 +31,14 @@ #include "pseudo.h" #include "operands/estate.h" +#include "operands/iflags.h" #include "operands/it.h" #include "operands/maccess.h" #include "operands/register.h" #include "operands/reglist.h" #include "operands/rotation.h" #include "operands/shift.h" +#include "registers/banked.h" #include "registers/basic.h" #include "registers/coproc.h" #include "registers/special.h" @@ -72,6 +74,19 @@ }) +#define BankedRegister(r, sysm) \ + ({ \ + GArchOperand *__result; \ + GArchRegister *__reg; \ + __reg = g_armv7_banked_register_new(r, sysm); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(__reg)); \ + __result; \ + }) + + #define BitDiff(msb, lsb) \ ({ \ GArchOperand *__result; \ @@ -154,6 +169,13 @@ }) +#define IFlagsDefinition(a, i, f) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_iflags_operand_new(a, i, f); \ + __result; \ + }) + #define ITCond(firstcond, mask) \ ({ \ GArchOperand *__result; \ @@ -273,6 +295,48 @@ }) +#define RegListWithoutPC(mask) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__pc; \ + GArmV7RegListOperand *__list; \ + __result = RegList(mask); \ + if (__result != NULL) \ + { \ + __pc = G_ARMV7_REGISTER(g_armv7_basic_register_new(15)); \ + __list = G_ARMV7_REGLIST_OPERAND(result); \ + if (g_armv7_reglist_operand_has_register(__list, __pc)) \ + { \ + g_object_unref(G_OBJECT(__result)); \ + __result = NULL; \ + } \ + g_object_unref(G_OBJECT(__pc)); \ + } \ + __result; \ + }) + + +#define RegListWithPC(mask) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__pc; \ + GArmV7RegListOperand *__list; \ + __result = RegList(mask); \ + if (__result != NULL) \ + { \ + __pc = G_ARMV7_REGISTER(g_armv7_basic_register_new(15)); \ + __list = G_ARMV7_REGLIST_OPERAND(result); \ + if (!g_armv7_reglist_operand_has_register(__list, __pc)) \ + { \ + g_object_unref(G_OBJECT(__result)); \ + __result = NULL; \ + } \ + g_object_unref(G_OBJECT(__pc)); \ + } \ + __result; \ + }) + + #define Rotation(val5) \ ({ \ GArchOperand *__result; \ diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h index a43474f..d6c4bc3 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h @@ -1,20 +1,5 @@ #ifndef arm_def_tmp_h #define arm_def_tmp_h -#define armv7_read_arm_instr_cps_arm(r) NULL -#define armv7_read_arm_instr_eret(r) NULL -#define armv7_read_arm_instr_hvc(r) NULL -#define armv7_read_arm_instr_isb(r) NULL -#define armv7_read_arm_instr_ldm_exception_return(r) NULL -#define armv7_read_arm_instr_ldm_user_registers(r) NULL -#define armv7_read_arm_instr_mrs_banked_register(r) NULL -#define armv7_read_arm_instr_msr_banked_register(r) NULL -#define armv7_read_arm_instr_msr_immediate_a8(r) NULL -#define armv7_read_arm_instr_msr_immediate_b9(r) NULL -#define armv7_read_arm_instr_msr_register_a8(r) NULL -#define armv7_read_arm_instr_msr_register_b9(r) NULL -#define armv7_read_arm_instr_pli_immediate_literal(r) NULL -#define armv7_read_arm_instr_rfe(r) NULL -#define armv7_read_arm_instr_smc_previously_smi(r) NULL -#define armv7_read_arm_instr_srs_arm(r) NULL -#define armv7_read_arm_instr_stm_user_registers(r) NULL +#define armv7_read_arm_instr_a8_isb(r) NULL +#define armv7_read_arm_instr_a8_pli_immediate_literal(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_simd.h b/plugins/arm/v7/opcodes/opcodes_tmp_simd.h index 1d7023e..9eab3f1 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_simd.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_simd.h @@ -1,138 +1,138 @@ #ifndef simd_def_tmp_h #define simd_def_tmp_h -#define armv7_read_simd_instr_vaba_vabal(r, a) NULL -#define armv7_read_simd_instr_vabd_floating_point(r, a) NULL -#define armv7_read_simd_instr_vabd_vabdl_integer(r, a) NULL -#define armv7_read_simd_instr_vabs(r, a) NULL -#define armv7_read_simd_instr_vacge_vacgt_vacle_vaclt(r, a) NULL -#define armv7_read_simd_instr_vadd_floating_point(r, a) NULL -#define armv7_read_simd_instr_vaddhn(r, a) NULL -#define armv7_read_simd_instr_vadd_integer(r, a) NULL -#define armv7_read_simd_instr_vaddl_vaddw(r, a) NULL -#define armv7_read_simd_instr_vand_register(r, a) NULL -#define armv7_read_simd_instr_vbic_immediate(r, a) NULL -#define armv7_read_simd_instr_vbic_register(r, a) NULL -#define armv7_read_simd_instr_vbif_vbit_vbsl(r, a) NULL -#define armv7_read_simd_instr_vceq_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vceq_register(r, a) NULL -#define armv7_read_simd_instr_vcge_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vcge_register(r, a) NULL -#define armv7_read_simd_instr_vcgt_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vcgt_register(r, a) NULL -#define armv7_read_simd_instr_vcle_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vcls(r, a) NULL -#define armv7_read_simd_instr_vclt_immediate_0(r, a) NULL -#define armv7_read_simd_instr_vclz(r, a) NULL -#define armv7_read_simd_instr_vcmp_vcmpe(r, a) NULL -#define armv7_read_simd_instr_vcnt(r, a) NULL -#define armv7_read_simd_instr_vcvt_between_double_precision_and_single_precision(r, a) NULL -#define armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_advanced_simd(r, a) NULL -#define armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(r, a) NULL -#define armv7_read_simd_instr_vcvtb_vcvtt(r, a) NULL -#define armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(r, a) NULL -#define armv7_read_simd_instr_vdiv(r, a) NULL -#define armv7_read_simd_instr_vdup_arm_core_register(r, a) NULL -#define armv7_read_simd_instr_vdup_scalar(r, a) NULL -#define armv7_read_simd_instr_veor(r, a) NULL -#define armv7_read_simd_instr_vext(r, a) NULL -#define armv7_read_simd_instr_vfma_vfms(r, a) NULL -#define armv7_read_simd_instr_vfnma_vfnms(r, a) NULL -#define armv7_read_simd_instr_vhadd_vhsub(r, a) NULL -#define armv7_read_simd_instr_vld1_multiple_single_elements(r, a) NULL -#define armv7_read_simd_instr_vld1_single_element_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld1_single_element_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vld2_multiple_2_element_structures(r, a) NULL -#define armv7_read_simd_instr_vld2_single_2_element_structure_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vld3_multiple_3_element_structures(r, a) NULL -#define armv7_read_simd_instr_vld3_single_3_element_structure_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vld4_multiple_4_element_structures(r, a) NULL -#define armv7_read_simd_instr_vld4_single_4_element_structure_to_all_lanes(r, a) NULL -#define armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(r, a) NULL -#define armv7_read_simd_instr_vldm(r, a) NULL -#define armv7_read_simd_instr_vldr(r, a) NULL -#define armv7_read_simd_instr_vmax_vmin_floating_point(r, a) NULL -#define armv7_read_simd_instr_vmax_vmin_integer(r, a) NULL -#define armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(r, a) NULL -#define armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(r, a) NULL -#define armv7_read_simd_instr_vmla_vmls_floating_point(r, a) NULL -#define armv7_read_simd_instr_vmov_arm_core_register_to_scalar(r, a) NULL -#define armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(r, a) NULL -#define armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(r, a) NULL -#define armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_two_single_precision_registers(r, a) NULL -#define armv7_read_simd_instr_vmov_immediate(r, a) NULL -#define armv7_read_simd_instr_vmovl(r, a) NULL -#define armv7_read_simd_instr_vmov_register(r, a) NULL -#define armv7_read_simd_instr_vmov_scalar_to_arm_core_register(r, a) NULL -#define armv7_read_simd_instr_vmrs(r, a) NULL -#define armv7_read_simd_instr_vmrs_b9(r, a) NULL -#define armv7_read_simd_instr_vmsr(r, a) NULL -#define armv7_read_simd_instr_vmsr_b9(r, a) NULL -#define armv7_read_simd_instr_vmul_floating_point(r, a) NULL -#define armv7_read_simd_instr_vmul_vmull_by_scalar(r, a) NULL -#define armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(r, a) NULL -#define armv7_read_simd_instr_vmvn_immediate(r, a) NULL -#define armv7_read_simd_instr_vmvn_register(r, a) NULL -#define armv7_read_simd_instr_vneg(r, a) NULL -#define armv7_read_simd_instr_vnmla_vnmls_vnmul(r, a) NULL -#define armv7_read_simd_instr_vorn_register(r, a) NULL -#define armv7_read_simd_instr_vorr_immediate(r, a) NULL -#define armv7_read_simd_instr_vorr_register(r, a) NULL -#define armv7_read_simd_instr_vpadal(r, a) NULL -#define armv7_read_simd_instr_vpadd_floating_point(r, a) NULL -#define armv7_read_simd_instr_vpadd_integer(r, a) NULL -#define armv7_read_simd_instr_vpaddl(r, a) NULL -#define armv7_read_simd_instr_vpmax_vpmin_floating_point(r, a) NULL -#define armv7_read_simd_instr_vpmax_vpmin_integer(r, a) NULL -#define armv7_read_simd_instr_vpop(r, a) NULL -#define armv7_read_simd_instr_vpush(r, a) NULL -#define armv7_read_simd_instr_vqabs(r, a) NULL -#define armv7_read_simd_instr_vqadd(r, a) NULL -#define armv7_read_simd_instr_vqdmlal_vqdmlsl(r, a) NULL -#define armv7_read_simd_instr_vqdmulh(r, a) NULL -#define armv7_read_simd_instr_vqdmull(r, a) NULL -#define armv7_read_simd_instr_vqneg(r, a) NULL -#define armv7_read_simd_instr_vqrdmulh(r, a) NULL -#define armv7_read_simd_instr_vqrshl(r, a) NULL -#define armv7_read_simd_instr_vqrshrn_vqrshrun(r, a) NULL -#define armv7_read_simd_instr_vqshl_register(r, a) NULL -#define armv7_read_simd_instr_vqshl_vqshlu_immediate(r, a) NULL -#define armv7_read_simd_instr_vqshrn_vqshrun(r, a) NULL -#define armv7_read_simd_instr_vqsub(r, a) NULL -#define armv7_read_simd_instr_vraddhn(r, a) NULL -#define armv7_read_simd_instr_vrecps(r, a) NULL -#define armv7_read_simd_instr_vrev16_vrev32_vrev64(r, a) NULL -#define armv7_read_simd_instr_vrhadd(r, a) NULL -#define armv7_read_simd_instr_vrshl(r, a) NULL -#define armv7_read_simd_instr_vrshr(r, a) NULL -#define armv7_read_simd_instr_vrshrn(r, a) NULL -#define armv7_read_simd_instr_vrsqrts(r, a) NULL -#define armv7_read_simd_instr_vrsra(r, a) NULL -#define armv7_read_simd_instr_vrsubhn(r, a) NULL -#define armv7_read_simd_instr_vshl_immediate(r, a) NULL -#define armv7_read_simd_instr_vshll(r, a) NULL -#define armv7_read_simd_instr_vshl_register(r, a) NULL -#define armv7_read_simd_instr_vshr(r, a) NULL -#define armv7_read_simd_instr_vshrn(r, a) NULL -#define armv7_read_simd_instr_vsli(r, a) NULL -#define armv7_read_simd_instr_vsqrt(r, a) NULL -#define armv7_read_simd_instr_vsra(r, a) NULL -#define armv7_read_simd_instr_vsri(r, a) NULL -#define armv7_read_simd_instr_vst1_multiple_single_elements(r, a) NULL -#define armv7_read_simd_instr_vst1_single_element_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vst2_multiple_2_element_structures(r, a) NULL -#define armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vst3_multiple_3_element_structures(r, a) NULL -#define armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vst4_multiple_4_element_structures(r, a) NULL -#define armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(r, a) NULL -#define armv7_read_simd_instr_vstm(r, a) NULL -#define armv7_read_simd_instr_vstr(r, a) NULL -#define armv7_read_simd_instr_vsub_floating_point(r, a) NULL -#define armv7_read_simd_instr_vsubhn(r, a) NULL -#define armv7_read_simd_instr_vsub_integer(r, a) NULL -#define armv7_read_simd_instr_vsubl_vsubw(r, a) NULL -#define armv7_read_simd_instr_vtbl_vtbx(r, a) NULL -#define armv7_read_simd_instr_vtst(r, a) NULL +#define armv7_read_simd_instr_a8_vaba_vabal(r, a) NULL +#define armv7_read_simd_instr_a8_vabd_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vabd_vabdl_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vabs(r, a) NULL +#define armv7_read_simd_instr_a8_vacge_vacgt_vacle_vaclt(r, a) NULL +#define armv7_read_simd_instr_a8_vadd_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vaddhn(r, a) NULL +#define armv7_read_simd_instr_a8_vadd_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vaddl_vaddw(r, a) NULL +#define armv7_read_simd_instr_a8_vand_register(r, a) NULL +#define armv7_read_simd_instr_a8_vbic_immediate(r, a) NULL +#define armv7_read_simd_instr_a8_vbic_register(r, a) NULL +#define armv7_read_simd_instr_a8_vbif_vbit_vbsl(r, a) NULL +#define armv7_read_simd_instr_a8_vceq_immediate_0(r, a) NULL +#define armv7_read_simd_instr_a8_vceq_register(r, a) NULL +#define armv7_read_simd_instr_a8_vcge_immediate_0(r, a) NULL +#define armv7_read_simd_instr_a8_vcge_register(r, a) NULL +#define armv7_read_simd_instr_a8_vcgt_immediate_0(r, a) NULL +#define armv7_read_simd_instr_a8_vcgt_register(r, a) NULL +#define armv7_read_simd_instr_a8_vcle_immediate_0(r, a) NULL +#define armv7_read_simd_instr_a8_vcls(r, a) NULL +#define armv7_read_simd_instr_a8_vclt_immediate_0(r, a) NULL +#define armv7_read_simd_instr_a8_vclz(r, a) NULL +#define armv7_read_simd_instr_a8_vcmp_vcmpe(r, a) NULL +#define armv7_read_simd_instr_a8_vcnt(r, a) NULL +#define armv7_read_simd_instr_a8_vcvt_between_double_precision_and_single_precision(r, a) NULL +#define armv7_read_simd_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(r, a) NULL +#define armv7_read_simd_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vcvtb_vcvtt(r, a) NULL +#define armv7_read_simd_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vdiv(r, a) NULL +#define armv7_read_simd_instr_a8_vdup_arm_core_register(r, a) NULL +#define armv7_read_simd_instr_a8_vdup_scalar(r, a) NULL +#define armv7_read_simd_instr_a8_veor(r, a) NULL +#define armv7_read_simd_instr_a8_vext(r, a) NULL +#define armv7_read_simd_instr_a8_vfma_vfms(r, a) NULL +#define armv7_read_simd_instr_a8_vfnma_vfnms(r, a) NULL +#define armv7_read_simd_instr_a8_vhadd_vhsub(r, a) NULL +#define armv7_read_simd_instr_a8_vld1_multiple_single_elements(r, a) NULL +#define armv7_read_simd_instr_a8_vld1_single_element_to_all_lanes(r, a) NULL +#define armv7_read_simd_instr_a8_vld1_single_element_to_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vld2_multiple_2_element_structures(r, a) NULL +#define armv7_read_simd_instr_a8_vld2_single_2_element_structure_to_all_lanes(r, a) NULL +#define armv7_read_simd_instr_a8_vld2_single_2_element_structure_to_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vld3_multiple_3_element_structures(r, a) NULL +#define armv7_read_simd_instr_a8_vld3_single_3_element_structure_to_all_lanes(r, a) NULL +#define armv7_read_simd_instr_a8_vld3_single_3_element_structure_to_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vld4_multiple_4_element_structures(r, a) NULL +#define armv7_read_simd_instr_a8_vld4_single_4_element_structure_to_all_lanes(r, a) NULL +#define armv7_read_simd_instr_a8_vld4_single_4_element_structure_to_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vldm(r, a) NULL +#define armv7_read_simd_instr_a8_vldr(r, a) NULL +#define armv7_read_simd_instr_a8_vmax_vmin_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vmax_vmin_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(r, a) NULL +#define armv7_read_simd_instr_a8_vmla_vmlal_vmls_vmlsl_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vmla_vmls_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_arm_core_register_to_scalar(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_between_arm_core_register_and_single_precision_register(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_between_two_arm_core_registers_and_two_single_precision_registers(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_immediate(r, a) NULL +#define armv7_read_simd_instr_a8_vmovl(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_register(r, a) NULL +#define armv7_read_simd_instr_a8_vmov_scalar_to_arm_core_register(r, a) NULL +#define armv7_read_simd_instr_a8_vmrs(r, a) NULL +#define armv7_read_simd_instr_a8_vmsr(r, a) NULL +#define armv7_read_simd_instr_a8_vmul_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vmul_vmull_by_scalar(r, a) NULL +#define armv7_read_simd_instr_a8_vmul_vmull_integer_and_polynomial(r, a) NULL +#define armv7_read_simd_instr_a8_vmvn_immediate(r, a) NULL +#define armv7_read_simd_instr_a8_vmvn_register(r, a) NULL +#define armv7_read_simd_instr_a8_vneg(r, a) NULL +#define armv7_read_simd_instr_a8_vnmla_vnmls_vnmul(r, a) NULL +#define armv7_read_simd_instr_a8_vorn_register(r, a) NULL +#define armv7_read_simd_instr_a8_vorr_immediate(r, a) NULL +#define armv7_read_simd_instr_a8_vorr_register(r, a) NULL +#define armv7_read_simd_instr_a8_vpadal(r, a) NULL +#define armv7_read_simd_instr_a8_vpadd_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vpadd_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vpaddl(r, a) NULL +#define armv7_read_simd_instr_a8_vpmax_vpmin_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vpmax_vpmin_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vpop(r, a) NULL +#define armv7_read_simd_instr_a8_vpush(r, a) NULL +#define armv7_read_simd_instr_a8_vqabs(r, a) NULL +#define armv7_read_simd_instr_a8_vqadd(r, a) NULL +#define armv7_read_simd_instr_a8_vqdmlal_vqdmlsl(r, a) NULL +#define armv7_read_simd_instr_a8_vqdmulh(r, a) NULL +#define armv7_read_simd_instr_a8_vqdmull(r, a) NULL +#define armv7_read_simd_instr_a8_vqneg(r, a) NULL +#define armv7_read_simd_instr_a8_vqrdmulh(r, a) NULL +#define armv7_read_simd_instr_a8_vqrshl(r, a) NULL +#define armv7_read_simd_instr_a8_vqrshrn_vqrshrun(r, a) NULL +#define armv7_read_simd_instr_a8_vqshl_register(r, a) NULL +#define armv7_read_simd_instr_a8_vqshl_vqshlu_immediate(r, a) NULL +#define armv7_read_simd_instr_a8_vqshrn_vqshrun(r, a) NULL +#define armv7_read_simd_instr_a8_vqsub(r, a) NULL +#define armv7_read_simd_instr_a8_vraddhn(r, a) NULL +#define armv7_read_simd_instr_a8_vrecps(r, a) NULL +#define armv7_read_simd_instr_a8_vrev16_vrev32_vrev64(r, a) NULL +#define armv7_read_simd_instr_a8_vrhadd(r, a) NULL +#define armv7_read_simd_instr_a8_vrshl(r, a) NULL +#define armv7_read_simd_instr_a8_vrshr(r, a) NULL +#define armv7_read_simd_instr_a8_vrshrn(r, a) NULL +#define armv7_read_simd_instr_a8_vrsqrts(r, a) NULL +#define armv7_read_simd_instr_a8_vrsra(r, a) NULL +#define armv7_read_simd_instr_a8_vrsubhn(r, a) NULL +#define armv7_read_simd_instr_a8_vshl_immediate(r, a) NULL +#define armv7_read_simd_instr_a8_vshll(r, a) NULL +#define armv7_read_simd_instr_a8_vshl_register(r, a) NULL +#define armv7_read_simd_instr_a8_vshr(r, a) NULL +#define armv7_read_simd_instr_a8_vshrn(r, a) NULL +#define armv7_read_simd_instr_a8_vsli(r, a) NULL +#define armv7_read_simd_instr_a8_vsqrt(r, a) NULL +#define armv7_read_simd_instr_a8_vsra(r, a) NULL +#define armv7_read_simd_instr_a8_vsri(r, a) NULL +#define armv7_read_simd_instr_a8_vst1_multiple_single_elements(r, a) NULL +#define armv7_read_simd_instr_a8_vst1_single_element_from_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vst2_multiple_2_element_structures(r, a) NULL +#define armv7_read_simd_instr_a8_vst2_single_2_element_structure_from_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vst3_multiple_3_element_structures(r, a) NULL +#define armv7_read_simd_instr_a8_vst3_single_3_element_structure_from_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vst4_multiple_4_element_structures(r, a) NULL +#define armv7_read_simd_instr_a8_vst4_single_4_element_structure_from_one_lane(r, a) NULL +#define armv7_read_simd_instr_a8_vstm(r, a) NULL +#define armv7_read_simd_instr_a8_vstr(r, a) NULL +#define armv7_read_simd_instr_a8_vsub_floating_point(r, a) NULL +#define armv7_read_simd_instr_a8_vsubhn(r, a) NULL +#define armv7_read_simd_instr_a8_vsub_integer(r, a) NULL +#define armv7_read_simd_instr_a8_vsubl_vsubw(r, a) NULL +#define armv7_read_simd_instr_a8_vtbl_vtbx(r, a) NULL +#define armv7_read_simd_instr_a8_vtst(r, a) NULL +#define armv7_read_simd_instr_b9_vmrs(r, a) NULL +#define armv7_read_simd_instr_b9_vmsr(r, a) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h index 449ea09..d21b056 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_16.h @@ -1,4 +1,3 @@ #ifndef thumb_16_def_tmp_h #define thumb_16_def_tmp_h -#define armv7_read_thumb_16_instr_cps_thumb(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h index 4ecba24..ce803c6 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -1,27 +1,16 @@ #ifndef thumb_32_def_tmp_h #define thumb_32_def_tmp_h -#define armv7_read_thumb_32_instr_b_mrs(r) NULL -#define armv7_read_thumb_32_instr_b_msr_register(r) NULL -#define armv7_read_thumb_32_instr_cps_thumb(r) NULL -#define armv7_read_thumb_32_instr_enterx_leavex(r) NULL -#define armv7_read_thumb_32_instr_eret(r) NULL -#define armv7_read_thumb_32_instr_hvc(r) NULL -#define armv7_read_thumb_32_instr_isb(r) NULL -#define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL -#define armv7_read_thumb_32_instr_msr_banked_register(r) NULL -#define armv7_read_thumb_32_instr_pld_immediate(r) NULL -#define armv7_read_thumb_32_instr_pld_register(r) NULL -#define armv7_read_thumb_32_instr_pli_immediate_literal(r) NULL -#define armv7_read_thumb_32_instr_rfe(r) NULL -#define armv7_read_thumb_32_instr_smc_previously_smi(r) NULL -#define armv7_read_thumb_32_instr_sqadd16(r) NULL -#define armv7_read_thumb_32_instr_sqadd8(r) NULL -#define armv7_read_thumb_32_instr_sqasx(r) NULL -#define armv7_read_thumb_32_instr_sqsax(r) NULL -#define armv7_read_thumb_32_instr_sqsub16(r) NULL -#define armv7_read_thumb_32_instr_sqsub8(r) NULL -#define armv7_read_thumb_32_instr_srs_thumb(r) NULL -#define armv7_read_thumb_32_instr_sub_register_thumb(r) NULL -#define armv7_read_thumb_32_instr_subs_pc_lr_thumb(r) NULL -#define armv7_read_thumb_32_instr_tbb_tbh(r) NULL +#define armv7_read_thumb_32_instr_a8_isb(r) NULL +#define armv7_read_thumb_32_instr_a8_pld_immediate(r) NULL +#define armv7_read_thumb_32_instr_a8_pld_register(r) NULL +#define armv7_read_thumb_32_instr_a8_pli_immediate_literal(r) NULL +#define armv7_read_thumb_32_instr_a8_sqadd16(r) NULL +#define armv7_read_thumb_32_instr_a8_sqadd8(r) NULL +#define armv7_read_thumb_32_instr_a8_sqasx(r) NULL +#define armv7_read_thumb_32_instr_a8_sqsax(r) NULL +#define armv7_read_thumb_32_instr_a8_sqsub16(r) NULL +#define armv7_read_thumb_32_instr_a8_sqsub8(r) NULL +#define armv7_read_thumb_32_instr_a8_sub_register_thumb(r) NULL +#define armv7_read_thumb_32_instr_a8_tbb_tbh(r) NULL +#define armv7_read_thumb_32_instr_a9_enterx_leavex(r) NULL #endif diff --git a/plugins/arm/v7/opdefs/A88100_mla.d b/plugins/arm/v7/opdefs/A88100_mla.d new file mode 100644 index 0000000..d5d0b94 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88100_mla.d @@ -0,0 +1,120 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MLA + +@id 94 + +@desc { + + Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 305 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mla reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 306 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mla reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 307 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mlas reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88101_mls.d b/plugins/arm/v7/opdefs/A88101_mls.d new file mode 100644 index 0000000..7fc527b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88101_mls.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MLS + +@id 95 + +@desc { + + Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 308 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mls reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 1 0 Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 309 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mls reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88102_mov.d b/plugins/arm/v7/opdefs/A88102_mov.d new file mode 100644 index 0000000..d3925b6 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88102_mov.d @@ -0,0 +1,210 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MOV (immediate) + +@id 96 + +@desc { + + Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} + +@encoding (t1) { + + @half 0 0 1 0 0 Rd(3) imm8(8) + + @syntax { + + @subid 310 + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm mov reg_D imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 311 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm mov.w reg_D const + + } + + @syntax { + + @subid 312 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm movs.w reg_D const + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 313 + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) + + } + + @asm movw reg_D imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) + + @syntax { + + @subid 314 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mov reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 315 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm movs reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) + + @syntax { + + @subid 316 + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) + + } + + @asm movw reg_D imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88103_mov.d b/plugins/arm/v7/opdefs/A88103_mov.d new file mode 100644 index 0000000..4f40758 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88103_mov.d @@ -0,0 +1,123 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MOV (register, Thumb) + +@id 97 + +@desc { + + Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3) + + @syntax { + + @subid 317 + + @conv { + + reg_D = Register(D:Rd) + reg_M = Register(Rm) + + } + + @asm mov reg_D reg_M + + } + +} + +@encoding (t2) { + + @half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3) + + @syntax { + + @subid 318 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm movs reg_D reg_M + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 319 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mov.w reg_D reg_M + + } + + @syntax { + + @subid 320 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm movs.w reg_D reg_M + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88104_mov.d b/plugins/arm/v7/opdefs/A88104_mov.d new file mode 100644 index 0000000..e6a758c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88104_mov.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MOV (register, ARM) + +@id 98 + +@desc { + + Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 Rm(4) + + @syntax { + + @subid 321 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mov reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 322 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm movs reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88106_movt.d b/plugins/arm/v7/opdefs/A88106_movt.d new file mode 100644 index 0000000..fc6bd84 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88106_movt.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MOVT + +@id 100 + +@desc { + + Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 323 + + @conv { + + reg_D = Register(Rd) + imm16 = UInt(imm4:i:imm3:imm8) + + } + + @asm movt reg_D imm16 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12) + + @syntax { + + @subid 324 + + @conv { + + reg_D = Register(Rd) + imm16 = UInt(imm4:imm12) + + } + + @asm movt reg_D imm16 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88107_mrc.d b/plugins/arm/v7/opdefs/A88107_mrc.d new file mode 100644 index 0000000..1053e95 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88107_mrc.d @@ -0,0 +1,133 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MRC, MRC2 + +@id 101 + +@desc { + + Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 325 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 326 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 327 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 328 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88108_mrrc.d b/plugins/arm/v7/opdefs/A88108_mrrc.d new file mode 100644 index 0000000..3f451d5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88108_mrrc.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MRRC, MRRC2 + +@id 102 + +@desc { + + Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 329 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 330 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 331 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 332 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88109_mrs.d b/plugins/arm/v7/opdefs/A88109_mrs.d new file mode 100644 index 0000000..dd6215c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88109_mrs.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MRS + +@id 103 + +@desc { + + Move to Register from Special register moves the value from the APSR into an ARM core register. For details of system level use of this instruction, see MRS on page B9-1988. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 333 + + @conv { + + reg_D = Register(Rd) + spec_reg = SpecRegAPSR() + + } + + @asm mrs reg_D spec_reg + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 0 1 1 1 1 Rd(4) 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 334 + + @conv { + + reg_D = Register(Rd) + spec_reg = SpecRegAPSR() + + } + + @asm mrs reg_D spec_reg + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8810_add.d b/plugins/arm/v7/opdefs/A8810_add.d new file mode 100644 index 0000000..357dadc --- /dev/null +++ b/plugins/arm/v7/opdefs/A8810_add.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (SP plus register, Thumb) + +@id 9 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) + + @syntax { + + @subid 33 + + @conv { + + reg_D = Register(DM:Rdm) + reg_SP = Register(13) + reg_M = Register(DM:Rdm) + + } + + @asm add ?reg_D reg_SP reg_M + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 + + @syntax { + + @subid 34 + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + reg_M = Register(Rm) + + } + + @asm add ?reg_D reg_SP reg_M + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 35 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_SP reg_M ?shift + + } + + @syntax { + + @subid 36 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm adds.w ?reg_D reg_SP reg_M ?shift + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88111_msr.d b/plugins/arm/v7/opdefs/A88111_msr.d new file mode 100644 index 0000000..5def4c5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88111_msr.d @@ -0,0 +1,60 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MSR (immediate) + +@id 105 + +@desc { + + Move immediate value to Special register moves selected bits of an immediate value to the corresponding bits in the APSR. For details of system level use of this instruction, see MSR (immediate) on page B9-1994. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 mask(2) 0 0 1 1 1 1 imm12(12) + + @syntax { + + @subid 335 + + @conv { + + spec_reg = SpecRegFromMask(mask) + imm32 = ARMExpandImm(imm12) + + } + + @asm msr spec_reg imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88112_msr.d b/plugins/arm/v7/opdefs/A88112_msr.d new file mode 100644 index 0000000..4967f01 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88112_msr.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MSR (register) + +@id 106 + +@desc { + + Move to Special register from ARM core register moves selected bits of an ARM core register to the APSR. For details of system level use of this instruction, see MSR (register) on page B9-1996. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 0 0 Rn(4) 1 0 0 0 mask(2) 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 336 + + @conv { + + spec_reg = SpecRegFromMask(mask) + reg_N = Register(Rn) + + } + + @asm msr spec_reg reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 mask(2) 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Rn(4) + + @syntax { + + @subid 337 + + @conv { + + spec_reg = SpecRegFromMask(mask) + reg_N = Register(Rn) + + } + + @asm msr spec_reg reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88114_mul.d b/plugins/arm/v7/opdefs/A88114_mul.d new file mode 100644 index 0000000..341de39 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88114_mul.d @@ -0,0 +1,139 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MUL + +@id 108 + +@desc { + + Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) + + @syntax { + + @subid 338 + + @conv { + + reg_D = Register(Rdm) + reg_N = Register(Rn) + reg_M = Register(Rdm) + + } + + @asm mul reg_D reg_N ?reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 339 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm mul reg_D reg_N ?reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 340 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm mul reg_D reg_N ?reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 341 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm muls reg_D reg_N ?reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88115_mvn.d b/plugins/arm/v7/opdefs/A88115_mvn.d new file mode 100644 index 0000000..ed0e7b8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88115_mvn.d @@ -0,0 +1,141 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MVN (immediate) + +@id 109 + +@desc { + + Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 342 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm mvn reg_D const + + } + + @syntax { + + @subid 343 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm mvns reg_D const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) + + @syntax { + + @subid 344 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvn reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 345 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvns reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88116_mvn.d b/plugins/arm/v7/opdefs/A88116_mvn.d new file mode 100644 index 0000000..208e7ad --- /dev/null +++ b/plugins/arm/v7/opdefs/A88116_mvn.d @@ -0,0 +1,166 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MVN (register) + +@id 110 + +@desc { + + Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) + + @syntax { + + @subid 346 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mvn reg_D reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 347 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm mvn.w reg_D reg_M ?shift + + } + + @syntax { + + @subid 348 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm mvns.w reg_D reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 349 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvn reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 350 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvns reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88117_mvn.d b/plugins/arm/v7/opdefs/A88117_mvn.d new file mode 100644 index 0000000..a4cd19f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88117_mvn.d @@ -0,0 +1,99 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MVN (register-shifted register) + +@id 111 + +@desc { + + Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 351 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm mvn reg_D reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 352 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm mvns reg_D reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88119_nop.d b/plugins/arm/v7/opdefs/A88119_nop.d new file mode 100644 index 0000000..a46e84a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88119_nop.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title NOP + +@id 113 + +@desc { + + No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 353 + + @asm nop + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 354 + + @asm nop.w + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 355 + + @asm nop + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8811_add.d b/plugins/arm/v7/opdefs/A8811_add.d new file mode 100644 index 0000000..f5c19aa --- /dev/null +++ b/plugins/arm/v7/opdefs/A8811_add.d @@ -0,0 +1,97 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (SP plus register, ARM) + +@id 10 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 37 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 38 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88120_orn.d b/plugins/arm/v7/opdefs/A88120_orn.d new file mode 100644 index 0000000..61c2b20 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88120_orn.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ORN (immediate) + +@id 114 + +@desc { + + Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 356 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm orn ?reg_D reg_N const + + } + + @syntax { + + @subid 357 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm orns ?reg_D reg_N const + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88121_orn.d b/plugins/arm/v7/opdefs/A88121_orn.d new file mode 100644 index 0000000..cacb69d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88121_orn.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ORN (register) + +@id 115 + +@desc { + + Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 358 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm orn ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 359 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm orns ?reg_D reg_N reg_M ?shift + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88122_orr.d b/plugins/arm/v7/opdefs/A88122_orr.d new file mode 100644 index 0000000..0f502a5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88122_orr.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ORR (immediate) + +@id 116 + +@desc { + + Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 360 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm orr ?reg_D reg_N const + + } + + @syntax { + + @subid 361 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm orrs ?reg_D reg_N const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 362 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm orr ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 363 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm orrs ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88123_orr.d b/plugins/arm/v7/opdefs/A88123_orr.d new file mode 100644 index 0000000..c7a82dd --- /dev/null +++ b/plugins/arm/v7/opdefs/A88123_orr.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ORR (register) + +@id 117 + +@desc { + + Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3) + + @syntax { + + @subid 364 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm orr ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 365 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm orr.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 366 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm orrs.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 367 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm orr ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 368 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm orrs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88124_orr.d b/plugins/arm/v7/opdefs/A88124_orr.d new file mode 100644 index 0000000..f38333d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88124_orr.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ORR (register-shifted register) + +@id 118 + +@desc { + + Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 369 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm orr ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 370 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm orrs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88125_pkh.d b/plugins/arm/v7/opdefs/A88125_pkh.d new file mode 100644 index 0000000..4b0c330 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88125_pkh.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title PKH + +@id 119 + +@desc { + + Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) tb(1) T(1) Rm(4) + + @syntax { + + @subid 371 + + @assert { + + tb == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm3:imm2) + + } + + @asm pkhbt ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 372 + + @assert { + + tb == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm3:imm2) + + } + + @asm pkhtb ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) imm5(5) tb(1) 0 1 Rm(4) + + @syntax { + + @subid 373 + + @assert { + + tb == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm5) + + } + + @asm pkhbt ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 374 + + @assert { + + tb == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(tb:'0', imm5) + + } + + @asm pkhtb ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88126_pld.d b/plugins/arm/v7/opdefs/A88126_pld.d new file mode 100644 index 0000000..174ef24 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88126_pld.d @@ -0,0 +1,183 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title PLD, PLDW (immediate) + +@id 120 + +@desc { + + Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. On an architecture variant that includes both the PLD and PLDW instructions, the PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 1 0 W(1) 1 Rn(4) 1 1 1 1 imm12(12) + + @syntax { + + @subid 375 + + @assert { + + W == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pld maccess + + } + + @syntax { + + @subid 376 + + @assert { + + W == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pldw maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 1 1 1 1 0 0 imm8(8) + + @syntax { + + @subid 377 + + @assert { + + W == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pld maccess + + } + + @syntax { + + @subid 378 + + @assert { + + W == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pldw maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 U(1) R(1) 0 1 Rn(4) 1 1 1 1 imm12(12) + + @syntax { + + @subid 379 + + @assert { + + R == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pld maccess + + } + + @syntax { + + @subid 380 + + @assert { + + R == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm pldw maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88127_pld.d b/plugins/arm/v7/opdefs/A88127_pld.d new file mode 100644 index 0000000..5f85a38 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88127_pld.d @@ -0,0 +1,73 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title PLD (literal) + +@id 121 + +@desc { + + Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. The effect of a PLD instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 1 1 1 1 imm12(12) + + @syntax { + + @subid 381 + + @conv { + + imm32 = ZeroExtend(imm12, 32) + + } + + @asm pld imm32 + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 U(1) 1 0 1 1 1 1 1 1 1 1 1 imm12(12) + + @syntax { + + @subid 382 + + @conv { + + imm32 = ZeroExtend(imm12, 32) + + } + + @asm pld imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88128_pld.d b/plugins/arm/v7/opdefs/A88128_pld.d new file mode 100644 index 0000000..cfe6b0c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88128_pld.d @@ -0,0 +1,137 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title PLD, PLDW (register) + +@id 122 + +@desc { + + Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. On an architecture variant that includes both the PLD and PLDW instructions, the PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 1 1 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 383 + + @assert { + + W == 0 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pld maccess + + } + + @syntax { + + @subid 384 + + @assert { + + W == 1 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pldw maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 1 1 U(1) R(1) 0 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 385 + + @assert { + + R == 1 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pld maccess + + } + + @syntax { + + @subid 386 + + @assert { + + R == 0 + + } + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pldw maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8812_adr.d b/plugins/arm/v7/opdefs/A8812_adr.d new file mode 100644 index 0000000..1f77eea --- /dev/null +++ b/plugins/arm/v7/opdefs/A8812_adr.d @@ -0,0 +1,150 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADR + +@id 11 + +@desc { + + This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. + +} + +@encoding (t1) { + + @half 1 0 1 0 0 Rd(3) imm8(8) + + @syntax { + + @subid 39 + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm adr reg_D imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 40 + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm adr.w reg_D imm32 + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 41 + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm adr.w reg_D imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) + + @syntax { + + @subid 42 + + @conv { + + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) + + } + + @asm adr reg_D imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) + + @syntax { + + @subid 43 + + @conv { + + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) + + } + + @asm adr reg_D imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88130_pli.d b/plugins/arm/v7/opdefs/A88130_pli.d new file mode 100644 index 0000000..97cff04 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88130_pli.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title PLI (register) + +@id 123 + +@desc { + + Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache. For more information, see Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. The effect of a PLI instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) 1 1 1 1 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 387 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pli maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 1 0 U(1) 1 0 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 388 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm pli maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88131_pop.d b/plugins/arm/v7/opdefs/A88131_pop.d new file mode 100644 index 0000000..41fe0b7 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88131_pop.d @@ -0,0 +1,111 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title POP (Thumb) + +@id 124 + +@desc { + + Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 0 P(1) register_list(8) + + @syntax { + + @subid 389 + + @conv { + + registers = RegList(P:'0000000':register_list) + + } + + @asm pop registers + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13) + + @syntax { + + @subid 390 + + @conv { + + registers = RegList(P:M:'0':register_list) + + } + + @asm pop.w registers + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0 + + @syntax { + + @subid 391 + + @conv { + + registers = SingleRegList(Rt) + + } + + @asm pop.w registers + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88132_pop.d b/plugins/arm/v7/opdefs/A88132_pop.d new file mode 100644 index 0000000..9b95613 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88132_pop.d @@ -0,0 +1,97 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title POP (ARM) + +@id 125 + +@desc { + + Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) + + @syntax { + + @subid 392 + + @conv { + + registers = RegList(register_list) + + } + + @asm pop registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax { + + @subid 393 + + @conv { + + registers = SingleRegList(Rt) + + } + + @asm pop registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + link = handle_armv7_return_from_pop + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88133_push.d b/plugins/arm/v7/opdefs/A88133_push.d new file mode 100644 index 0000000..bb1502d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88133_push.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title PUSH + +@id 126 + +@desc { + + Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 1 0 M(1) register_list(8) + + @syntax { + + @subid 394 + + @conv { + + registers = RegList('0':M:'000000':register_list) + + } + + @asm push registers + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13) + + @syntax { + + @subid 395 + + @conv { + + registers = RegList('0':M:'0':register_list) + + } + + @asm push.w registers + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0 + + @syntax { + + @subid 396 + + @conv { + + registers = SingleRegList(Rt) + + } + + @asm push.w registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16) + + @syntax { + + @subid 397 + + @conv { + + registers = RegList(register_list) + + } + + @asm push registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax { + + @subid 398 + + @conv { + + registers = SingleRegList(Rt) + + } + + @asm push registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88134_qadd.d b/plugins/arm/v7/opdefs/A88134_qadd.d new file mode 100644 index 0000000..4617c02 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88134_qadd.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QADD + +@id 127 + +@desc { + + Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax { + + @subid 399 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qadd ?reg_D reg_M reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax { + + @subid 400 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qadd ?reg_D reg_M reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88135_qadd16.d b/plugins/arm/v7/opdefs/A88135_qadd16.d new file mode 100644 index 0000000..7aa565b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88135_qadd16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QADD16 + +@id 128 + +@desc { + + Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 401 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qadd16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 402 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qadd16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88136_qadd8.d b/plugins/arm/v7/opdefs/A88136_qadd8.d new file mode 100644 index 0000000..0b00037 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88136_qadd8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QADD8 + +@id 129 + +@desc { + + Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 403 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qadd8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax { + + @subid 404 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qadd8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88137_qasx.d b/plugins/arm/v7/opdefs/A88137_qasx.d new file mode 100644 index 0000000..be7a880 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88137_qasx.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QASX + +@id 130 + +@desc { + + Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 405 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qasx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 406 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qasx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88138_qdadd.d b/plugins/arm/v7/opdefs/A88138_qdadd.d new file mode 100644 index 0000000..0058e44 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88138_qdadd.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QDADD + +@id 131 + +@desc { + + Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) + + @syntax { + + @subid 407 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qdadd ?reg_D reg_M reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax { + + @subid 408 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qdadd ?reg_D reg_M reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88139_qdsub.d b/plugins/arm/v7/opdefs/A88139_qdsub.d new file mode 100644 index 0000000..cd7cd21 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88139_qdsub.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QDSUB + +@id 132 + +@desc { + + Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) + + @syntax { + + @subid 409 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qdsub ?reg_D reg_M reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax { + + @subid 410 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qdsub ?reg_D reg_M reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8813_and.d b/plugins/arm/v7/opdefs/A8813_and.d new file mode 100644 index 0000000..988bdd7 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8813_and.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title AND (immediate) + +@id 12 + +@desc { + + This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 44 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm and ?reg_D reg_N const + + } + + @syntax { + + @subid 45 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm ands ?reg_D reg_N const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 46 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm and ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 47 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm ands ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88140_qsax.d b/plugins/arm/v7/opdefs/A88140_qsax.d new file mode 100644 index 0000000..3aec301 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88140_qsax.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QSAX + +@id 133 + +@desc { + + Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 411 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qsax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @subid 412 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qsax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88141_qsub.d b/plugins/arm/v7/opdefs/A88141_qsub.d new file mode 100644 index 0000000..6f9631f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88141_qsub.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QSUB + +@id 134 + +@desc { + + Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) + + @syntax { + + @subid 413 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qsub ?reg_D reg_M reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) + + @syntax { + + @subid 414 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) + + } + + @asm qsub ?reg_D reg_M reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88142_qsub16.d b/plugins/arm/v7/opdefs/A88142_qsub16.d new file mode 100644 index 0000000..9d9eb8a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88142_qsub16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QSUB16 + +@id 135 + +@desc { + + Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 415 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qsub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @subid 416 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qsub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88143_qsub8.d b/plugins/arm/v7/opdefs/A88143_qsub8.d new file mode 100644 index 0000000..23e77be --- /dev/null +++ b/plugins/arm/v7/opdefs/A88143_qsub8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title QSUB8 + +@id 136 + +@desc { + + Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) + + @syntax { + + @subid 417 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qsub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @subid 418 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm qsub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88144_rbit.d b/plugins/arm/v7/opdefs/A88144_rbit.d new file mode 100644 index 0000000..f28a7d9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88144_rbit.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RBIT + +@id 137 + +@desc { + + Reverse Bits reverses the bit order in a 32-bit register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) + + @syntax { + + @subid 419 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rbit reg_D reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 420 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rbit reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88145_rev.d b/plugins/arm/v7/opdefs/A88145_rev.d new file mode 100644 index 0000000..33ed857 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88145_rev.d @@ -0,0 +1,102 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title REV + +@id 138 + +@desc { + + Byte-Reverse Word reverses the byte order in a 32-bit register. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 0 1 0 0 0 Rm(3) Rd(3) + + @syntax { + + @subid 421 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev reg_D reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax { + + @subid 422 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev.w reg_D reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 423 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88146_rev16.d b/plugins/arm/v7/opdefs/A88146_rev16.d new file mode 100644 index 0000000..326a5e6 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88146_rev16.d @@ -0,0 +1,102 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title REV16 + +@id 139 + +@desc { + + Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3) + + @syntax { + + @subid 424 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev16 reg_D reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) + + @syntax { + + @subid 425 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev16.w reg_D reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) + + @syntax { + + @subid 426 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev16 reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88147_revsh.d b/plugins/arm/v7/opdefs/A88147_revsh.d new file mode 100644 index 0000000..824e46d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88147_revsh.d @@ -0,0 +1,102 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title REVSH + +@id 140 + +@desc { + + Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 0 1 0 1 1 Rm(3) Rd(3) + + @syntax { + + @subid 427 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm revsh reg_D reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) + + @syntax { + + @subid 428 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm revsh.w reg_D reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) + + @syntax { + + @subid 429 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm revsh reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88149_ror.d b/plugins/arm/v7/opdefs/A88149_ror.d new file mode 100644 index 0000000..402cbbd --- /dev/null +++ b/plugins/arm/v7/opdefs/A88149_ror.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ROR (immediate) + +@id 142 + +@desc { + + Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 1 Rm(4) + + @syntax { + + @subid 430 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm3:imm2) + + } + + @asm ror ?reg_D reg_M shift_n + + } + + @syntax { + + @subid 431 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm3:imm2) + + } + + @asm rors ?reg_D reg_M shift_n + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 1 0 Rm(4) + + @syntax { + + @subid 432 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm5) + + } + + @asm ror ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 433 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm5) + + } + + @asm rors ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8814_and.d b/plugins/arm/v7/opdefs/A8814_and.d new file mode 100644 index 0000000..1a807f9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8814_and.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title AND (register) + +@id 13 + +@desc { + + This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) + + @syntax { + + @subid 48 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm and ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 49 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm and.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 50 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm ands.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 51 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm and ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 52 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm ands ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88150_ror.d b/plugins/arm/v7/opdefs/A88150_ror.d new file mode 100644 index 0000000..c2ff476 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88150_ror.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ROR (register) + +@id 143 + +@desc { + + Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 1 1 Rm(3) Rdn(3) + + @syntax { + + @subid 434 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm ror ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 435 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ror.w ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 436 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm rors.w ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 1 1 Rn(4) + + @syntax { + + @subid 437 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ror ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 438 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm rors ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88151_rrx.d b/plugins/arm/v7/opdefs/A88151_rrx.d new file mode 100644 index 0000000..f78791d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88151_rrx.d @@ -0,0 +1,141 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RRX + +@id 144 + +@desc { + + Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4) + + @syntax { + + @subid 439 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrx ?reg_D reg_M + + } + + @syntax { + + @subid 440 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrxs ?reg_D reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4) + + @syntax { + + @subid 441 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrx ?reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 442 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrxs ?reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88152_rsb.d b/plugins/arm/v7/opdefs/A88152_rsb.d new file mode 100644 index 0000000..cc5a1c6 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88152_rsb.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RSB (immediate) + +@id 145 + +@desc { + + Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) + + @syntax { + + @subid 443 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = Zeros(32) + + } + + @asm rsb ?reg_D reg_N imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 444 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm rsb.w ?reg_D reg_N imm32 + + } + + @syntax { + + @subid 445 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm rsbs.w ?reg_D reg_N imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 446 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsb ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 447 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsbs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88153_rsb.d b/plugins/arm/v7/opdefs/A88153_rsb.d new file mode 100644 index 0000000..aedd51d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88153_rsb.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RSB (register) + +@id 146 + +@desc { + + Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 448 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm rsb ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 449 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm rsbs ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 450 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsb ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 451 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsbs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88154_rsb.d b/plugins/arm/v7/opdefs/A88154_rsb.d new file mode 100644 index 0000000..8fe52ef --- /dev/null +++ b/plugins/arm/v7/opdefs/A88154_rsb.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RSB (register-shifted register) + +@id 147 + +@desc { + + Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 452 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsb ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 453 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsbs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88155_rsc.d b/plugins/arm/v7/opdefs/A88155_rsc.d new file mode 100644 index 0000000..8f2688f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88155_rsc.d @@ -0,0 +1,95 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RSC (immediate) + +@id 148 + +@desc { + + Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 1 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 454 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 455 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rscs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88156_rsc.d b/plugins/arm/v7/opdefs/A88156_rsc.d new file mode 100644 index 0000000..0efd043 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88156_rsc.d @@ -0,0 +1,97 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RSC (register) + +@id 149 + +@desc { + + Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 456 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 457 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rscs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88157_rsc.d b/plugins/arm/v7/opdefs/A88157_rsc.d new file mode 100644 index 0000000..6d2a46f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88157_rsc.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RSC (register-shifted register) + +@id 150 + +@desc { + + Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 458 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsc ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 459 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rscs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88158_sadd16.d b/plugins/arm/v7/opdefs/A88158_sadd16.d new file mode 100644 index 0000000..10917ec --- /dev/null +++ b/plugins/arm/v7/opdefs/A88158_sadd16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SADD16 + +@id 151 + +@desc { + + Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 460 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sadd16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 461 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sadd16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88159_sadd8.d b/plugins/arm/v7/opdefs/A88159_sadd8.d new file mode 100644 index 0000000..cf9bb74 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88159_sadd8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SADD8 + +@id 152 + +@desc { + + Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 462 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sadd8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax { + + @subid 463 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sadd8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8815_and.d b/plugins/arm/v7/opdefs/A8815_and.d new file mode 100644 index 0000000..3d890cb --- /dev/null +++ b/plugins/arm/v7/opdefs/A8815_and.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title AND (register-shifted register) + +@id 14 + +@desc { + + This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 53 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm and ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 54 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm ands ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88160_sasx.d b/plugins/arm/v7/opdefs/A88160_sasx.d new file mode 100644 index 0000000..676915a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88160_sasx.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SASX + +@id 153 + +@desc { + + Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 464 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sasx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 465 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sasx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88161_sbc.d b/plugins/arm/v7/opdefs/A88161_sbc.d new file mode 100644 index 0000000..9962438 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88161_sbc.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SBC (immediate) + +@id 154 + +@desc { + + Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 466 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sbc ?reg_D reg_N imm32 + + } + + @syntax { + + @subid 467 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sbcs ?reg_D reg_N imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 1 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 468 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sbc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 469 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sbcs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88162_sbc.d b/plugins/arm/v7/opdefs/A88162_sbc.d new file mode 100644 index 0000000..f931d4d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88162_sbc.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SBC (register) + +@id 155 + +@desc { + + Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) + + @syntax { + + @subid 470 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm sbc ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 471 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sbc.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 472 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sbcs.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 473 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 474 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88163_sbc.d b/plugins/arm/v7/opdefs/A88163_sbc.d new file mode 100644 index 0000000..f287959 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88163_sbc.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SBC (register-shifted register) + +@id 156 + +@desc { + + Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 475 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sbc ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 476 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sbcs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88164_sbfx.d b/plugins/arm/v7/opdefs/A88164_sbfx.d new file mode 100644 index 0000000..bdc3fbd --- /dev/null +++ b/plugins/arm/v7/opdefs/A88164_sbfx.d @@ -0,0 +1,87 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SBFX + +@id 157 + +@desc { + + Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) + + @syntax { + + @subid 477 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) + + } + + @asm sbfx reg_D reg_N lsbit width + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 0 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) + + @syntax { + + @subid 478 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) + + } + + @asm sbfx reg_D reg_N lsbit width + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88165_sdiv.d b/plugins/arm/v7/opdefs/A88165_sdiv.d new file mode 100644 index 0000000..498cafd --- /dev/null +++ b/plugins/arm/v7/opdefs/A88165_sdiv.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SDIV + +@id 158 + +@desc { + + Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) + + @syntax { + + @subid 479 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sdiv ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) + + @syntax { + + @subid 480 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sdiv ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88166_sel.d b/plugins/arm/v7/opdefs/A88166_sel.d new file mode 100644 index 0000000..3fb9747 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88166_sel.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SEL + +@id 159 + +@desc { + + Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax { + + @subid 481 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sel ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 1 1 Rm(4) + + @syntax { + + @subid 482 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sel ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88167_setend.d b/plugins/arm/v7/opdefs/A88167_setend.d new file mode 100644 index 0000000..c9d3f0a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88167_setend.d @@ -0,0 +1,73 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SETEND + +@id 160 + +@desc { + + Set Endianness writes a new value to ENDIANSTATE. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 1 1 0 0 1 0 1 E(1) 0 0 0 + + @syntax { + + @subid 483 + + @conv { + + endian_specifier = Endian(E) + + } + + @asm setend endian_specifier + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 E(1) 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 484 + + @conv { + + endian_specifier = Endian(E) + + } + + @asm setend endian_specifier + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88168_sev.d b/plugins/arm/v7/opdefs/A88168_sev.d new file mode 100644 index 0000000..23d7cae --- /dev/null +++ b/plugins/arm/v7/opdefs/A88168_sev.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SEV + +@id 161 + +@desc { + + Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 + + @syntax { + + @subid 485 + + @asm sev + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax { + + @subid 486 + + @asm sev.w + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 + + @syntax { + + @subid 487 + + @asm sev + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88169_shadd16.d b/plugins/arm/v7/opdefs/A88169_shadd16.d new file mode 100644 index 0000000..c0f8fd5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88169_shadd16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SHADD16 + +@id 162 + +@desc { + + Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax { + + @subid 488 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shadd16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 489 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shadd16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8816_asr.d b/plugins/arm/v7/opdefs/A8816_asr.d new file mode 100644 index 0000000..401c4c5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8816_asr.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ASR (immediate) + +@id 15 + +@desc { + + Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) + + @syntax { + + @subid 55 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asr ?reg_D reg_M shift_n + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) + + @syntax { + + @subid 56 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm3:imm2) + + } + + @asm asr.w ?reg_D reg_M shift_n + + } + + @syntax { + + @subid 57 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm3:imm2) + + } + + @asm asrs.w ?reg_D reg_M shift_n + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) + + @syntax { + + @subid 58 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asr ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 59 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asrs ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88170_shadd8.d b/plugins/arm/v7/opdefs/A88170_shadd8.d new file mode 100644 index 0000000..d08052e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88170_shadd8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SHADD8 + +@id 163 + +@desc { + + Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax { + + @subid 490 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shadd8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax { + + @subid 491 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shadd8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88171_shasx.d b/plugins/arm/v7/opdefs/A88171_shasx.d new file mode 100644 index 0000000..5761f3d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88171_shasx.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SHASX + +@id 164 + +@desc { + + Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax { + + @subid 492 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shasx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 493 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shasx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88172_shsax.d b/plugins/arm/v7/opdefs/A88172_shsax.d new file mode 100644 index 0000000..af81443 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88172_shsax.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SHSAX + +@id 165 + +@desc { + + Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax { + + @subid 494 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shsax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @subid 495 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shsax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88173_shsub16.d b/plugins/arm/v7/opdefs/A88173_shsub16.d new file mode 100644 index 0000000..de01a16 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88173_shsub16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SHSUB16 + +@id 166 + +@desc { + + Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax { + + @subid 496 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shsub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @subid 497 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shsub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88174_shsub8.d b/plugins/arm/v7/opdefs/A88174_shsub8.d new file mode 100644 index 0000000..e8b6eab --- /dev/null +++ b/plugins/arm/v7/opdefs/A88174_shsub8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SHSUB8 + +@id 167 + +@desc { + + Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) + + @syntax { + + @subid 498 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shsub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @subid 499 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm shsub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88176_smla.d b/plugins/arm/v7/opdefs/A88176_smla.d new file mode 100644 index 0000000..10d9bcc --- /dev/null +++ b/plugins/arm/v7/opdefs/A88176_smla.d @@ -0,0 +1,261 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLABB, SMLABT, SMLATB, SMLATT + +@id 169 + +@desc { + + Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. It is not possible for overflow to occur during the multiplication. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 1 Rn(4) Ra(4) Rd(4) 0 0 N(1) M(1) Rm(4) + + @syntax { + + @subid 500 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatt reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 501 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatb reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 502 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabt reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 503 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabb reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 1 M(1) N(1) 0 Rn(4) + + @syntax { + + @subid 504 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatt reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 505 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlatb reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 506 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabt reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 507 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlabb reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88177_smlad.d b/plugins/arm/v7/opdefs/A88177_smlad.d new file mode 100644 index 0000000..c27b907 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88177_smlad.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLAD + +@id 170 + +@desc { + + Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 508 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlad reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 509 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smladx reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 M(1) 1 Rn(4) + + @syntax { + + @subid 510 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlad reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 511 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smladx reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88178_smlal.d b/plugins/arm/v7/opdefs/A88178_smlal.d new file mode 100644 index 0000000..cb1909a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88178_smlal.d @@ -0,0 +1,120 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLAL + +@id 171 + +@desc { + + Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 512 + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlal reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 513 + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlal reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 514 + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlals reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88179_smlal.d b/plugins/arm/v7/opdefs/A88179_smlal.d new file mode 100644 index 0000000..fa09e7c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88179_smlal.d @@ -0,0 +1,261 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLALBB, SMLALBT, SMLALTB, SMLALTT + +@id 172 + +@desc { + + Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and accumulated with a 64-bit accumulate value. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 0 N(1) M(1) Rm(4) + + @syntax { + + @subid 515 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltt reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 516 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltb reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 517 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbt reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 518 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbb reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 M(1) N(1) 0 Rn(4) + + @syntax { + + @subid 519 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltt reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 520 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaltb reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 521 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbt reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 522 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlalbb reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8817_asr.d b/plugins/arm/v7/opdefs/A8817_asr.d new file mode 100644 index 0000000..0ddeae9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8817_asr.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ASR (register) + +@id 16 + +@desc { + + Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) + + @syntax { + + @subid 60 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm asr ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 61 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asr.w ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 62 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asrs.w ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) + + @syntax { + + @subid 63 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 64 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88180_smlald.d b/plugins/arm/v7/opdefs/A88180_smlald.d new file mode 100644 index 0000000..39a475c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88180_smlald.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLALD + +@id 173 + +@desc { + + Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) + + @syntax { + + @subid 523 + + @assert { + + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlald reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 524 + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaldx reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4) + + @syntax { + + @subid 525 + + @assert { + + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlald reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 526 + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaldx reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88181_smlaw.d b/plugins/arm/v7/opdefs/A88181_smlaw.d new file mode 100644 index 0000000..d7aaa7f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88181_smlaw.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLAWB, SMLAWT + +@id 174 + +@desc { + + Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No overflow can occur during the multiplication. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 527 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawt reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 528 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawb reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 Rd(4) Ra(4) Rm(4) 1 M(1) 0 0 Rn(4) + + @syntax { + + @subid 529 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawt reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 530 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlawb reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88182_smlsd.d b/plugins/arm/v7/opdefs/A88182_smlsd.d new file mode 100644 index 0000000..90a2ca7 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88182_smlsd.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLSD + +@id 175 + +@desc { + + Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 531 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsd reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 532 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsdx reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4) + + @syntax { + + @subid 533 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsd reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 534 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsdx reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88183_smlsld.d b/plugins/arm/v7/opdefs/A88183_smlsld.d new file mode 100644 index 0000000..bca92d9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88183_smlsld.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMLSLD + +@id 176 + +@desc { + + Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 0 1 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) + + @syntax { + + @subid 535 + + @assert { + + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsld reg_DLO reg_DHI reg_N reg_M + + } + + @syntax { + + @subid 536 + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsldx reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 1 M(1) 1 Rn(4) + + @syntax { + + @subid 537 + + @assert { + + M == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsld reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 538 + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsldx reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88184_smmla.d b/plugins/arm/v7/opdefs/A88184_smmla.d new file mode 100644 index 0000000..a805bff --- /dev/null +++ b/plugins/arm/v7/opdefs/A88184_smmla.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMMLA + +@id 177 + +@desc { + + Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) + + @syntax { + + @subid 539 + + @assert { + + R == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmla reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 540 + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlar reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4) + + @syntax { + + @subid 541 + + @assert { + + R == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmla reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 542 + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlar reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88185_smmls.d b/plugins/arm/v7/opdefs/A88185_smmls.d new file mode 100644 index 0000000..e195b3b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88185_smmls.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMMLS + +@id 178 + +@desc { + + Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) + + @syntax { + + @subid 543 + + @assert { + + R == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmls reg_D reg_N reg_M reg_A + + } + + @syntax { + + @subid 544 + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlsr reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 1 1 R(1) 1 Rn(4) + + @syntax { + + @subid 545 + + @assert { + + R == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmls reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 546 + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlsr reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88186_smmul.d b/plugins/arm/v7/opdefs/A88186_smmul.d new file mode 100644 index 0000000..31ed01d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88186_smmul.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMMUL + +@id 179 + +@desc { + + Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4) + + @syntax { + + @subid 547 + + @assert { + + R == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmul ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 548 + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmulr ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4) + + @syntax { + + @subid 549 + + @assert { + + R == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmul ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 550 + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmulr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88187_smuad.d b/plugins/arm/v7/opdefs/A88187_smuad.d new file mode 100644 index 0000000..47d4d9e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88187_smuad.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMUAD + +@id 180 + +@desc { + + Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 551 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuad ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 552 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuadx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4) + + @syntax { + + @subid 553 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuad ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 554 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuadx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88188_smul.d b/plugins/arm/v7/opdefs/A88188_smul.d new file mode 100644 index 0000000..6d01041 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88188_smul.d @@ -0,0 +1,253 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMULBB, SMULBT, SMULTB, SMULTT + +@id 181 + +@desc { + + Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 N(1) M(1) Rm(4) + + @syntax { + + @subid 555 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultt ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 556 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultb ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 557 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbt ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 558 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbb ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 Rd(4) 0 0 0 0 Rm(4) 1 M(1) N(1) 0 Rn(4) + + @syntax { + + @subid 559 + + @assert { + + N == 1 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultt ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 560 + + @assert { + + N == 1 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smultb ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 561 + + @assert { + + N == 0 + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbt ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 562 + + @assert { + + N == 0 + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulbb ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88189_smull.d b/plugins/arm/v7/opdefs/A88189_smull.d new file mode 100644 index 0000000..35e1d46 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88189_smull.d @@ -0,0 +1,120 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMULL + +@id 182 + +@desc { + + Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 563 + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smull reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 564 + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smull reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 565 + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8818_b.d b/plugins/arm/v7/opdefs/A8818_b.d new file mode 100644 index 0000000..d10b297 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8818_b.d @@ -0,0 +1,192 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title B + +@id 17 + +@desc { + + Branch causes a branch to a target address. + +} + +@encoding (t1) { + + @half 1 1 0 1 cond(4) imm8(8) + + @syntax { + + @subid 65 + + @conv { + + imm32 = SignExtend(imm8:'0', 32, 8) + + } + + @asm b imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (t2) { + + @half 1 1 1 0 0 imm11(11) + + @syntax { + + @subid 66 + + @conv { + + imm32 = SignExtend(imm11:'0', 32, 11) + + } + + @asm b imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) + + @syntax { + + @subid 67 + + @conv { + + imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32, 20) + + } + + @asm b imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + check g_armv7_instruction_extend_keyword(".W") + + } + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) + + @syntax { + + @subid 68 + + @conv { + + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) + + } + + @asm b.w imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_thumb + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 1 0 imm24(24) + + @syntax { + + @subid 69 + + @conv { + + imm32 = SignExtend(imm24:'00', 32, 25) + + } + + @asm b imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + fetch = help_fetching_with_instruction_b_from_arm + link = handle_arm_conditional_branch_as_link + post = post_process_branch_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88190_smulw.d b/plugins/arm/v7/opdefs/A88190_smulw.d new file mode 100644 index 0000000..8c3a2e1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88190_smulw.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMULWB, SMULWT + +@id 183 + +@desc { + + Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 566 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwt ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 567 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwb ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 Rd(4) 0 0 0 0 Rm(4) 1 M(1) 1 0 Rn(4) + + @syntax { + + @subid 568 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwt ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 569 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulwb ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88191_smusd.d b/plugins/arm/v7/opdefs/A88191_smusd.d new file mode 100644 index 0000000..d6f8aed --- /dev/null +++ b/plugins/arm/v7/opdefs/A88191_smusd.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMUSD + +@id 184 + +@desc { + + Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow cannot occur. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) + + @syntax { + + @subid 570 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusd ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 571 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusdx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 1 M(1) 1 Rn(4) + + @syntax { + + @subid 572 + + @assert { + + M == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusd ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 573 + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smusdx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88193_ssat.d b/plugins/arm/v7/opdefs/A88193_ssat.d new file mode 100644 index 0000000..e381f92 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88193_ssat.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SSAT + +@id 186 + +@desc { + + Signed Saturate saturates an optionally-shifted signed value to a selectable signed range. The Q flag is set if the operation saturates. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) + + @syntax { + + @subid 574 + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm3:imm2) + + } + + @asm ssat reg_D saturate_to reg_N ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) + + @syntax { + + @subid 575 + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm5) + + } + + @asm ssat reg_D saturate_to reg_N ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88194_ssat16.d b/plugins/arm/v7/opdefs/A88194_ssat16.d new file mode 100644 index 0000000..02c52df --- /dev/null +++ b/plugins/arm/v7/opdefs/A88194_ssat16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SSAT16 + +@id 187 + +@desc { + + Signed Saturate 16 saturates two signed 16-bit values to a selected signed range. The Q flag is set if the operation saturates. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) + + @syntax { + + @subid 576 + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + + } + + @asm ssat16 reg_D saturate_to reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) + + @syntax { + + @subid 577 + + @conv { + + reg_D = Register(Rd) + saturate_to = UIntInc(sat_imm) + reg_N = Register(Rn) + + } + + @asm ssat16 reg_D saturate_to reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88195_ssax.d b/plugins/arm/v7/opdefs/A88195_ssax.d new file mode 100644 index 0000000..257be5e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88195_ssax.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SSAX + +@id 188 + +@desc { + + Signed Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 578 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @subid 579 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88196_ssub16.d b/plugins/arm/v7/opdefs/A88196_ssub16.d new file mode 100644 index 0000000..54ed2dd --- /dev/null +++ b/plugins/arm/v7/opdefs/A88196_ssub16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SSUB16 + +@id 189 + +@desc { + + Signed Subtract 16 performs two 16-bit signed integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 580 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @subid 581 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88197_ssub8.d b/plugins/arm/v7/opdefs/A88197_ssub8.d new file mode 100644 index 0000000..43f32ba --- /dev/null +++ b/plugins/arm/v7/opdefs/A88197_ssub8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SSUB8 + +@id 190 + +@desc { + + Signed Subtract 8 performs four 8-bit signed integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 582 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @subid 583 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ssub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88198_stc.d b/plugins/arm/v7/opdefs/A88198_stc.d new file mode 100644 index 0000000..764d611 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88198_stc.d @@ -0,0 +1,461 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STC, STC2 + +@id 191 + +@desc { + + Store Coprocessor stores data from a coprocessor to a sequence of consecutive memory addresses. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid STC and STC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted STC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the STC pseudocode does not show this possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 584 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 585 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 586 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 587 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 588 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 589 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 590 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 591 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 592 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 593 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 594 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 595 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 596 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 597 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 598 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm stc cp direct_CRd maccess + + } + + @syntax { + + @subid 599 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm stc cp direct_CRd maccess option + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88199_stm.d b/plugins/arm/v7/opdefs/A88199_stm.d new file mode 100644 index 0000000..610c757 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88199_stm.d @@ -0,0 +1,111 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STM (STMIA, STMEA) + +@id 192 + +@desc { + + Store Multiple Increment After (Store Multiple Empty Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the last of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (t1) { + + @half 1 1 0 0 0 Rn(3) register_list(8) + + @syntax { + + @subid 600 + + @conv { + + reg_N = Register(Rn) + wb_reg = UncheckedWrittenBackReg(reg_N) + registers = RegList('00000000':register_list) + + } + + @asm stm wb_reg registers + + } + + @hooks { + + fetch = apply_write_back + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 0 1 0 W(1) 0 Rn(4) 0 M(1) 0 register_list(13) + + @syntax { + + @subid 601 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList('0':M:'0':register_list) + + } + + @asm stm.w wb_reg registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 1 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 602 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stm wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8819_bfc.d b/plugins/arm/v7/opdefs/A8819_bfc.d new file mode 100644 index 0000000..f8875e5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8819_bfc.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BFC + +@id 18 + +@desc { + + Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 msb(5) + + @syntax { + + @subid 70 + + @conv { + + reg_D = Register(Rd) + lsbit = UInt(imm3:imm2) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) + + } + + @asm bfc reg_D lsbit width + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 1 1 1 1 + + @syntax { + + @subid 71 + + @conv { + + reg_D = Register(Rd) + lsbit = UInt(lsb) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) + + } + + @asm bfc reg_D lsbit width + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A881_adc.d b/plugins/arm/v7/opdefs/A881_adc.d new file mode 100644 index 0000000..d470638 --- /dev/null +++ b/plugins/arm/v7/opdefs/A881_adc.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADC (immediate) + +@id 0 + +@desc { + + Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 0 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adc ?reg_D reg_N imm32 + + } + + @syntax { + + @subid 1 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adcs ?reg_D reg_N imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 2 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 3 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adcs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88200_stmda.d b/plugins/arm/v7/opdefs/A88200_stmda.d new file mode 100644 index 0000000..192f7e9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88200_stmda.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STMDA (STMED) + +@id 193 + +@desc { + + Store Multiple Decrement After (Store Multiple Empty Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 0 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 603 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stmda wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88201_stmdb.d b/plugins/arm/v7/opdefs/A88201_stmdb.d new file mode 100644 index 0000000..cce1a8b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88201_stmdb.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STMDB (STMFD) + +@id 194 + +@desc { + + Store Multiple Decrement Before (Store Multiple Full Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the first of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 1 0 0 W(1) 0 Rn(4) 0 M(1) 0 register_list(13) + + @syntax { + + @subid 604 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList('0':M:'0':register_list) + + } + + @asm stmdb wb_reg registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 0 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 605 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stmdb wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88202_stmib.d b/plugins/arm/v7/opdefs/A88202_stmib.d new file mode 100644 index 0000000..fa881e0 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88202_stmib.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STMIB (STMFA) + +@id 195 + +@desc { + + Store Multiple Increment Before (Store Multiple Full Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 1 0 W(1) 0 Rn(4) register_list(16) + + @syntax { + + @subid 606 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm stmib wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88203_str.d b/plugins/arm/v7/opdefs/A88203_str.d new file mode 100644 index 0000000..680562f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88203_str.d @@ -0,0 +1,180 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STR (immediate, Thumb) + +@id 196 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) + + @syntax { + + @subid 607 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + +} + +@encoding (t2) { + + @half 1 0 0 1 0 Rt(3) imm8(8) + + @syntax { + + @subid 608 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 609 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str.w reg_T maccess + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 610 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @subid 611 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @subid 612 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88204_str.d b/plugins/arm/v7/opdefs/A88204_str.d new file mode 100644 index 0000000..d280fb4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88204_str.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STR (immediate, ARM) + +@id 197 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 613 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 614 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 615 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88205_str.d b/plugins/arm/v7/opdefs/A88205_str.d new file mode 100644 index 0000000..0e33f0e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88205_str.d @@ -0,0 +1,179 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STR (register) + +@id 198 + +@desc { + + Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 616 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm str reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 617 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm str.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 618 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 619 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 620 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88206_strb.d b/plugins/arm/v7/opdefs/A88206_strb.d new file mode 100644 index 0000000..acceb11 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88206_strb.d @@ -0,0 +1,157 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRB (immediate, Thumb) + +@id 199 + +@desc { + + Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 1 1 0 imm5(5) Rn(3) Rt(3) + + @syntax { + + @subid 621 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 0 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 622 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb.w reg_T maccess + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 623 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + + @syntax { + + @subid 624 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + + @syntax { + + @subid 625 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88207_strb.d b/plugins/arm/v7/opdefs/A88207_strb.d new file mode 100644 index 0000000..74e43c8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88207_strb.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRB (immediate, ARM) + +@id 200 + +@desc { + + Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 626 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 627 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 628 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88208_strb.d b/plugins/arm/v7/opdefs/A88208_strb.d new file mode 100644 index 0000000..07801b0 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88208_strb.d @@ -0,0 +1,179 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRB (register) + +@id 201 + +@desc { + + Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 629 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strb reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 630 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm strb.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 631 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 632 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 633 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88209_strbt.d b/plugins/arm/v7/opdefs/A88209_strbt.d new file mode 100644 index 0000000..b7f4bfb --- /dev/null +++ b/plugins/arm/v7/opdefs/A88209_strbt.d @@ -0,0 +1,115 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRBT + +@id 202 + +@desc { + + Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 634 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strbt reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 635 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strbt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 636 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strbt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8820_bfi.d b/plugins/arm/v7/opdefs/A8820_bfi.d new file mode 100644 index 0000000..aa71aa8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8820_bfi.d @@ -0,0 +1,87 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BFI + +@id 19 + +@desc { + + Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 0 1 1 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 msb(5) + + @syntax { + + @subid 72 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) + + } + + @asm bfi reg_D reg_N lsbit width + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 Rn(4) + + @syntax { + + @subid 73 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) + + } + + @asm bfi reg_D reg_N lsbit width + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88210_strd.d b/plugins/arm/v7/opdefs/A88210_strd.d new file mode 100644 index 0000000..41a9cf8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88210_strd.d @@ -0,0 +1,213 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRD (immediate) + +@id 203 + +@desc { + + Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) + + @syntax { + + @subid 637 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + + @syntax { + + @subid 638 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + + @syntax { + + @subid 639 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax { + + @subid 640 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 641 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 642 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88211_strd.d b/plugins/arm/v7/opdefs/A88211_strd.d new file mode 100644 index 0000000..407dfe3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88211_strd.d @@ -0,0 +1,132 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRD (register) + +@id 204 + +@desc { + + Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax { + + @subid 643 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 644 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 645 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88212_strex.d b/plugins/arm/v7/opdefs/A88212_strex.d new file mode 100644 index 0000000..b73767e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88212_strex.d @@ -0,0 +1,87 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STREX + +@id 205 + +@desc { + + Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) + + @syntax { + + @subid 646 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strex reg_D reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax { + + @subid 647 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strex reg_D reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88213_strexb.d b/plugins/arm/v7/opdefs/A88213_strexb.d new file mode 100644 index 0000000..40aa68e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88213_strexb.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STREXB + +@id 206 + +@desc { + + Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) + + @syntax { + + @subid 648 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm strexb reg_D reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax { + + @subid 649 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm strexb reg_D reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88214_strexd.d b/plugins/arm/v7/opdefs/A88214_strexd.d new file mode 100644 index 0000000..cef38ed --- /dev/null +++ b/plugins/arm/v7/opdefs/A88214_strexd.d @@ -0,0 +1,87 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STREXD + +@id 207 + +@desc { + + Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) + + @syntax { + + @subid 650 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm strexd reg_D reg_T reg_T2 maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax { + + @subid 651 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm strexd reg_D reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88215_strexh.d b/plugins/arm/v7/opdefs/A88215_strexh.d new file mode 100644 index 0000000..3066ddc --- /dev/null +++ b/plugins/arm/v7/opdefs/A88215_strexh.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STREXH + +@id 208 + +@desc { + + Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) + + @syntax { + + @subid 652 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm strexh reg_D reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax { + + @subid 653 + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm strexh reg_D reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88216_strh.d b/plugins/arm/v7/opdefs/A88216_strh.d new file mode 100644 index 0000000..5376406 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88216_strh.d @@ -0,0 +1,157 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRH (immediate, Thumb) + +@id 209 + +@desc { + + Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) + + @syntax { + + @subid 654 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 655 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh.w reg_T maccess + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 656 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + + @syntax { + + @subid 657 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + + @syntax { + + @subid 658 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88217_strh.d b/plugins/arm/v7/opdefs/A88217_strh.d new file mode 100644 index 0000000..b3f7763 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88217_strh.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRH (immediate, ARM) + +@id 210 + +@desc { + + Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax { + + @subid 659 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 660 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 661 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88218_strh.d b/plugins/arm/v7/opdefs/A88218_strh.d new file mode 100644 index 0000000..7a5a23b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88218_strh.d @@ -0,0 +1,176 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRH (register) + +@id 211 + +@desc { + + Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 662 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 663 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm strh.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax { + + @subid 664 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 665 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 666 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88219_strht.d b/plugins/arm/v7/opdefs/A88219_strht.d new file mode 100644 index 0000000..5ed4f1b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88219_strht.d @@ -0,0 +1,114 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRHT + +@id 212 + +@desc { + + Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 667 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strht reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax { + + @subid 668 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strht reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax { + + @subid 669 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strht reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8821_bic.d b/plugins/arm/v7/opdefs/A8821_bic.d new file mode 100644 index 0000000..59d4bb0 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8821_bic.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BIC (immediate) + +@id 20 + +@desc { + + Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 74 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm bic ?reg_D reg_N const + + } + + @syntax { + + @subid 75 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm bics ?reg_D reg_N const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 76 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm bic ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 77 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm bics ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88220_strt.d b/plugins/arm/v7/opdefs/A88220_strt.d new file mode 100644 index 0000000..feb9927 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88220_strt.d @@ -0,0 +1,115 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STRT + +@id 213 + +@desc { + + Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 670 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strt reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 671 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 672 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88221_sub.d b/plugins/arm/v7/opdefs/A88221_sub.d new file mode 100644 index 0000000..415c99e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88221_sub.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUB (immediate, Thumb) + +@id 214 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) + + @syntax { + + @subid 673 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) + + } + + @asm sub ?reg_D reg_N imm32 + + } + +} + +@encoding (t2) { + + @half 0 0 1 1 1 Rdn(3) imm8(8) + + @syntax { + + @subid 674 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm sub ?reg_D reg_N imm32 + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 675 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_N imm32 + + } + + @syntax { + + @subid 676 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_N imm32 + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 677 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm subw ?reg_D reg_N imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88222_sub.d b/plugins/arm/v7/opdefs/A88222_sub.d new file mode 100644 index 0000000..14489a7 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88222_sub.d @@ -0,0 +1,95 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUB (immediate, ARM) + +@id 215 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 678 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 679 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88223_sub.d b/plugins/arm/v7/opdefs/A88223_sub.d new file mode 100644 index 0000000..585fa60 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88223_sub.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUB (register) + +@id 216 + +@desc { + + This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3) + + @syntax { + + @subid 680 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm sub ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 681 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sub.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 682 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm subs.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 683 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sub ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 684 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm subs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88224_sub.d b/plugins/arm/v7/opdefs/A88224_sub.d new file mode 100644 index 0000000..bf7cee4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88224_sub.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUB (register-shifted register) + +@id 217 + +@desc { + + This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 685 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sub ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 686 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm subs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88225_sub.d b/plugins/arm/v7/opdefs/A88225_sub.d new file mode 100644 index 0000000..c8b95d4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88225_sub.d @@ -0,0 +1,189 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUB (SP minus immediate) + +@id 218 + +@desc { + + This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 0 0 1 imm7(7) + + @syntax { + + @subid 687 + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) + + } + + @asm sub ?reg_D reg_SP imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 688 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_SP imm32 + + } + + @syntax { + + @subid 689 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_SP imm32 + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 690 + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm subw ?reg_D reg_SP imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) + + @syntax { + + @subid 691 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 692 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88226_sub.d b/plugins/arm/v7/opdefs/A88226_sub.d new file mode 100644 index 0000000..3f42232 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88226_sub.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUB (SP minus register) + +@id 219 + +@desc { + + This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 693 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sub ?reg_D reg_SP reg_M ?shift + + } + + @syntax { + + @subid 694 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm subs ?reg_D reg_SP reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 695 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sub ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 696 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm subs ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88228_svc.d b/plugins/arm/v7/opdefs/A88228_svc.d new file mode 100644 index 0000000..c74f818 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88228_svc.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SVC (previously SWI) + +@id 221 + +@desc { + + Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. + +} + +@encoding (t1) { + + @half 1 1 0 1 1 1 1 1 imm8(8) + + @syntax { + + @subid 697 + + @conv { + + imm32 = ZeroExtend(imm8, 32) + + } + + @asm svc imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 1 1 1 1 imm24(24) + + @syntax { + + @subid 698 + + @conv { + + imm32 = ZeroExtend(imm24, 32) + + } + + @asm svc imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88229_swp.d b/plugins/arm/v7/opdefs/A88229_swp.d new file mode 100644 index 0000000..6d8261a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88229_swp.d @@ -0,0 +1,97 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SWP, SWPB + +@id 222 + +@desc { + + SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register . The value of register is then stored to the memory address given by the value of , and the original loaded value is written to register . If the same register is specified for and , this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register . The value of the least significant byte of register is stored to the memory address given by , the original loaded value is zero-extended to a 32-bit word, and the word is written to register . If the same register is specified for and , this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — — LDREXB/STREXB in preference to SWPB. • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 B(1) 0 0 Rn(4) Rt(4) 0 0 0 0 1 0 0 1 Rt2(4) + + @syntax { + + @subid 699 + + @assert { + + B == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm swp reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 700 + + @assert { + + B == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm swpb reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8822_bic.d b/plugins/arm/v7/opdefs/A8822_bic.d new file mode 100644 index 0000000..f4746b9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8822_bic.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BIC (register) + +@id 21 + +@desc { + + Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3) + + @syntax { + + @subid 78 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm bic ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 79 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm bic.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 80 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm bics.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 81 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm bic ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 82 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm bics ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88230_sxtab.d b/plugins/arm/v7/opdefs/A88230_sxtab.d new file mode 100644 index 0000000..138c0a5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88230_sxtab.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SXTAB + +@id 223 + +@desc { + + Signed Extend and Add Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 1 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 701 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 702 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88231_sxtab16.d b/plugins/arm/v7/opdefs/A88231_sxtab16.d new file mode 100644 index 0000000..6fac4ba --- /dev/null +++ b/plugins/arm/v7/opdefs/A88231_sxtab16.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SXTAB16 + +@id 224 + +@desc { + + Signed Extend and Add Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 703 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab16 ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 704 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtab16 ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88232_sxtah.d b/plugins/arm/v7/opdefs/A88232_sxtah.d new file mode 100644 index 0000000..d2170b6 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88232_sxtah.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SXTAH + +@id 225 + +@desc { + + Signed Extend and Add Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 705 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtah ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 706 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtah ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88233_sxtb.d b/plugins/arm/v7/opdefs/A88233_sxtb.d new file mode 100644 index 0000000..84d7ed4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88233_sxtb.d @@ -0,0 +1,105 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SXTB + +@id 226 + +@desc { + + Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 0 1 Rm(3) Rd(3) + + @syntax { + + @subid 707 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) + + } + + @asm sxtb ?reg_D reg_M ?rotation + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 708 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb.w ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 709 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88234_sxtb16.d b/plugins/arm/v7/opdefs/A88234_sxtb16.d new file mode 100644 index 0000000..5f690be --- /dev/null +++ b/plugins/arm/v7/opdefs/A88234_sxtb16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SXTB16 + +@id 227 + +@desc { + + Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 710 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb16 ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 711 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxtb16 ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88235_sxth.d b/plugins/arm/v7/opdefs/A88235_sxth.d new file mode 100644 index 0000000..c75cdf3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88235_sxth.d @@ -0,0 +1,105 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SXTH + +@id 228 + +@desc { + + Signed Extend Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 0 0 Rm(3) Rd(3) + + @syntax { + + @subid 712 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) + + } + + @asm sxth ?reg_D reg_M ?rotation + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 713 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxth.w ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 714 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm sxth ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88237_teq.d b/plugins/arm/v7/opdefs/A88237_teq.d new file mode 100644 index 0000000..148d76d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88237_teq.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title TEQ (immediate) + +@id 229 + +@desc { + + Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax { + + @subid 715 + + @conv { + + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm teq reg_N const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax { + + @subid 716 + + @conv { + + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm teq reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88238_teq.d b/plugins/arm/v7/opdefs/A88238_teq.d new file mode 100644 index 0000000..2fc99bb --- /dev/null +++ b/plugins/arm/v7/opdefs/A88238_teq.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title TEQ (register) + +@id 230 + +@desc { + + Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax { + + @subid 717 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm teq reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 718 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm teq reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88239_teq.d b/plugins/arm/v7/opdefs/A88239_teq.d new file mode 100644 index 0000000..806328e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88239_teq.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title TEQ (register-shifted register) + +@id 231 + +@desc { + + Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 719 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm teq reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8823_bic.d b/plugins/arm/v7/opdefs/A8823_bic.d new file mode 100644 index 0000000..fb57338 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8823_bic.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BIC (register-shifted register) + +@id 22 + +@desc { + + Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 83 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm bic ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 84 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm bics ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88240_tst.d b/plugins/arm/v7/opdefs/A88240_tst.d new file mode 100644 index 0000000..d1258d4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88240_tst.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title TST (immediate) + +@id 232 + +@desc { + + Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax { + + @subid 720 + + @conv { + + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm tst reg_N const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax { + + @subid 721 + + @conv { + + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm tst reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88241_tst.d b/plugins/arm/v7/opdefs/A88241_tst.d new file mode 100644 index 0000000..98e820e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88241_tst.d @@ -0,0 +1,104 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title TST (register) + +@id 233 + +@desc { + + Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) + + @syntax { + + @subid 722 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm tst reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax { + + @subid 723 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm tst.w reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 724 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm tst reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88242_tst.d b/plugins/arm/v7/opdefs/A88242_tst.d new file mode 100644 index 0000000..ef1c4df --- /dev/null +++ b/plugins/arm/v7/opdefs/A88242_tst.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title TST (register-shifted register) + +@id 234 + +@desc { + + Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 725 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm tst reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88243_uadd16.d b/plugins/arm/v7/opdefs/A88243_uadd16.d new file mode 100644 index 0000000..3a220d2 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88243_uadd16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UADD16 + +@id 235 + +@desc { + + Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax { + + @subid 726 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uadd16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 727 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uadd16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88244_uadd8.d b/plugins/arm/v7/opdefs/A88244_uadd8.d new file mode 100644 index 0000000..a2d4a97 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88244_uadd8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UADD8 + +@id 236 + +@desc { + + Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax { + + @subid 728 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uadd8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax { + + @subid 729 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uadd8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88245_uasx.d b/plugins/arm/v7/opdefs/A88245_uasx.d new file mode 100644 index 0000000..eca3303 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88245_uasx.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UASX + +@id 237 + +@desc { + + Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax { + + @subid 730 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uasx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 731 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uasx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88246_ubfx.d b/plugins/arm/v7/opdefs/A88246_ubfx.d new file mode 100644 index 0000000..cd39cb3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88246_ubfx.d @@ -0,0 +1,87 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UBFX + +@id 238 + +@desc { + + Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) + + @syntax { + + @subid 732 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) + + } + + @asm ubfx reg_D reg_N lsbit width + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) + + @syntax { + + @subid 733 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) + + } + + @asm ubfx reg_D reg_N lsbit width + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88247_udf.d b/plugins/arm/v7/opdefs/A88247_udf.d new file mode 100644 index 0000000..f6aeb3a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88247_udf.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UDF + +@id 239 + +@desc { + + Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. + +} + +@encoding (t1) { + + @half 1 1 0 1 1 1 1 0 imm8(8) + + @syntax { + + @subid 734 + + @conv { + + imm32 = ZeroExtend(imm8, 32) + + } + + @asm udf imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 1 0 imm12(12) + + @syntax { + + @subid 735 + + @conv { + + imm32 = ZeroExtend(imm4:imm12, 32) + + } + + @asm udf.w imm32 + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 0 1 1 1 1 1 1 1 imm12(12) 1 1 1 1 imm4(4) + + @syntax { + + @subid 736 + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) + + } + + @asm udf imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88248_udiv.d b/plugins/arm/v7/opdefs/A88248_udiv.d new file mode 100644 index 0000000..b142ffb --- /dev/null +++ b/plugins/arm/v7/opdefs/A88248_udiv.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UDIV + +@id 240 + +@desc { + + Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) + + @syntax { + + @subid 737 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm udiv ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 0 0 1 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) + + @syntax { + + @subid 738 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm udiv ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88249_uhadd16.d b/plugins/arm/v7/opdefs/A88249_uhadd16.d new file mode 100644 index 0000000..4d220ae --- /dev/null +++ b/plugins/arm/v7/opdefs/A88249_uhadd16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UHADD16 + +@id 241 + +@desc { + + Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 739 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhadd16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 740 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhadd16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8824_bkpt.d b/plugins/arm/v7/opdefs/A8824_bkpt.d new file mode 100644 index 0000000..e9c9f4b --- /dev/null +++ b/plugins/arm/v7/opdefs/A8824_bkpt.d @@ -0,0 +1,73 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BKPT + +@id 23 + +@desc { + + Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 0 imm8(8) + + @syntax { + + @subid 85 + + @conv { + + imm32 = ZeroExtend(imm8, 32) + + } + + @asm bkpt imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 imm12(12) 0 1 1 1 imm4(4) + + @syntax { + + @subid 86 + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) + + } + + @asm bkpt imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88250_uhadd8.d b/plugins/arm/v7/opdefs/A88250_uhadd8.d new file mode 100644 index 0000000..e28cb14 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88250_uhadd8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UHADD8 + +@id 242 + +@desc { + + Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 741 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhadd8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax { + + @subid 742 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhadd8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88251_uhasx.d b/plugins/arm/v7/opdefs/A88251_uhasx.d new file mode 100644 index 0000000..6aa7d7e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88251_uhasx.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UHASX + +@id 243 + +@desc { + + Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 743 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhasx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 744 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhasx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88252_uhsax.d b/plugins/arm/v7/opdefs/A88252_uhsax.d new file mode 100644 index 0000000..6639e6c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88252_uhsax.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UHSAX + +@id 244 + +@desc { + + Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 745 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhsax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @subid 746 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhsax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88253_uhsub16.d b/plugins/arm/v7/opdefs/A88253_uhsub16.d new file mode 100644 index 0000000..c64a424 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88253_uhsub16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UHSUB16 + +@id 245 + +@desc { + + Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 747 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhsub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @subid 748 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhsub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88254_uhsub8.d b/plugins/arm/v7/opdefs/A88254_uhsub8.d new file mode 100644 index 0000000..1e1d7d1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88254_uhsub8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UHSUB8 + +@id 246 + +@desc { + + Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 749 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhsub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @subid 750 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uhsub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88255_umaal.d b/plugins/arm/v7/opdefs/A88255_umaal.d new file mode 100644 index 0000000..69623a2 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88255_umaal.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UMAAL + +@id 247 + +@desc { + + Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 1 1 0 Rm(4) + + @syntax { + + @subid 751 + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umaal reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 752 + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umaal reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88256_umlal.d b/plugins/arm/v7/opdefs/A88256_umlal.d new file mode 100644 index 0000000..64d7cc1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88256_umlal.d @@ -0,0 +1,120 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UMLAL + +@id 248 + +@desc { + + Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 753 + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umlal reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 754 + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umlal reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 755 + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umlals reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88257_umull.d b/plugins/arm/v7/opdefs/A88257_umull.d new file mode 100644 index 0000000..3ded23c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88257_umull.d @@ -0,0 +1,120 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UMULL + +@id 249 + +@desc { + + Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 1 0 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 756 + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umull reg_DLO reg_DHI reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) + + @syntax { + + @subid 757 + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umull reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 758 + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88258_uqadd16.d b/plugins/arm/v7/opdefs/A88258_uqadd16.d new file mode 100644 index 0000000..bc37e8c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88258_uqadd16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UQADD16 + +@id 250 + +@desc { + + Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax { + + @subid 759 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqadd16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 760 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqadd16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88259_uqadd8.d b/plugins/arm/v7/opdefs/A88259_uqadd8.d new file mode 100644 index 0000000..349b1b8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88259_uqadd8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UQADD8 + +@id 251 + +@desc { + + Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax { + + @subid 761 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqadd8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) + + @syntax { + + @subid 762 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqadd8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8825_bl.d b/plugins/arm/v7/opdefs/A8825_bl.d new file mode 100644 index 0000000..221bbc5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8825_bl.d @@ -0,0 +1,151 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BL, BLX (immediate) + +@id 24 + +@desc { + + Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) + + @syntax { + + @subid 87 + + @conv { + + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) + + } + + @asm bl imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_bl_from_thumb + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) + + @syntax { + + @subid 88 + + @conv { + + imm32 = SignExtend(S:J1:J2:imm10H:imm10L:'00', 32, 24) + + } + + @asm blx imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_blx_from_thumb + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 1 1 imm24(24) + + @syntax { + + @subid 89 + + @conv { + + imm32 = SignExtend(imm24:'00', 32, 25) + + } + + @asm bl imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + fetch = help_fetching_with_instruction_bl_from_arm + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 0 1 H(1) imm24(24) + + @syntax { + + @subid 90 + + @conv { + + imm32 = SignExtend(imm24:H:'0', 32, 25) + + } + + @asm blx imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_blx_from_arm + link = handle_call_as_link + post = post_process_branch_and_link_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88260_uqasx.d b/plugins/arm/v7/opdefs/A88260_uqasx.d new file mode 100644 index 0000000..4733d58 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88260_uqasx.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UQASX + +@id 252 + +@desc { + + Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax { + + @subid 763 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqasx ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 764 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqasx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88261_uqsax.d b/plugins/arm/v7/opdefs/A88261_uqsax.d new file mode 100644 index 0000000..92bef77 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88261_uqsax.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UQSAX + +@id 253 + +@desc { + + Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax { + + @subid 765 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqsax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @subid 766 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqsax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88262_uqsub16.d b/plugins/arm/v7/opdefs/A88262_uqsub16.d new file mode 100644 index 0000000..9b9611d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88262_uqsub16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UQSUB16 + +@id 254 + +@desc { + + Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax { + + @subid 767 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqsub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @subid 768 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqsub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88263_uqsub8.d b/plugins/arm/v7/opdefs/A88263_uqsub8.d new file mode 100644 index 0000000..ea041bc --- /dev/null +++ b/plugins/arm/v7/opdefs/A88263_uqsub8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UQSUB8 + +@id 255 + +@desc { + + Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) + + @syntax { + + @subid 769 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqsub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @subid 770 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm uqsub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88264_usad8.d b/plugins/arm/v7/opdefs/A88264_usad8.d new file mode 100644 index 0000000..d804b6f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88264_usad8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USAD8 + +@id 256 + +@desc { + + Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 771 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usad8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) + + @syntax { + + @subid 772 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usad8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88265_usada8.d b/plugins/arm/v7/opdefs/A88265_usada8.d new file mode 100644 index 0000000..faace0c --- /dev/null +++ b/plugins/arm/v7/opdefs/A88265_usada8.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USADA8 + +@id 257 + +@desc { + + Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 773 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm usada8 reg_D reg_N reg_M reg_A + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 0 1 Rn(4) + + @syntax { + + @subid 774 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm usada8 reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88266_usat.d b/plugins/arm/v7/opdefs/A88266_usat.d new file mode 100644 index 0000000..7275113 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88266_usat.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USAT + +@id 258 + +@desc { + + Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) + + @syntax { + + @subid 775 + + @conv { + + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm3:imm2) + + } + + @asm usat reg_D saturate_to reg_N ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) + + @syntax { + + @subid 776 + + @conv { + + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm5) + + } + + @asm usat reg_D saturate_to reg_N ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88267_usat16.d b/plugins/arm/v7/opdefs/A88267_usat16.d new file mode 100644 index 0000000..eaaaa3f --- /dev/null +++ b/plugins/arm/v7/opdefs/A88267_usat16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USAT16 + +@id 259 + +@desc { + + Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) + + @syntax { + + @subid 777 + + @conv { + + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + + } + + @asm usat16 reg_D saturate_to reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) + + @syntax { + + @subid 778 + + @conv { + + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + + } + + @asm usat16 reg_D saturate_to reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88268_usax.d b/plugins/arm/v7/opdefs/A88268_usax.d new file mode 100644 index 0000000..89731f1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88268_usax.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USAX + +@id 260 + +@desc { + + Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax { + + @subid 779 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usax ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) + + @syntax { + + @subid 780 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usax ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88269_usub16.d b/plugins/arm/v7/opdefs/A88269_usub16.d new file mode 100644 index 0000000..192d7bf --- /dev/null +++ b/plugins/arm/v7/opdefs/A88269_usub16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USUB16 + +@id 261 + +@desc { + + Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax { + + @subid 781 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usub16 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) + + @syntax { + + @subid 782 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usub16 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8826_blx.d b/plugins/arm/v7/opdefs/A8826_blx.d new file mode 100644 index 0000000..2c975d3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8826_blx.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BLX (register) + +@id 25 + +@desc { + + Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 1 1 1 1 Rm(4) 0 0 0 + + @syntax { + + @subid 91 + + @conv { + + reg_M = Register(Rm) + + } + + @asm blx reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 Rm(4) + + @syntax { + + @subid 92 + + @conv { + + reg_M = Register(Rm) + + } + + @asm blx reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88270_usub8.d b/plugins/arm/v7/opdefs/A88270_usub8.d new file mode 100644 index 0000000..a2e921e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88270_usub8.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title USUB8 + +@id 262 + +@desc { + + Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) + + @syntax { + + @subid 783 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usub8 ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) + + @syntax { + + @subid 784 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm usub8 ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88271_uxtab.d b/plugins/arm/v7/opdefs/A88271_uxtab.d new file mode 100644 index 0000000..f84b7d4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88271_uxtab.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UXTAB + +@id 263 + +@desc { + + Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 785 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtab ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 786 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtab ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88272_uxtab16.d b/plugins/arm/v7/opdefs/A88272_uxtab16.d new file mode 100644 index 0000000..ac2e47d --- /dev/null +++ b/plugins/arm/v7/opdefs/A88272_uxtab16.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UXTAB16 + +@id 264 + +@desc { + + Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 787 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtab16 ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 788 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtab16 ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88273_uxtah.d b/plugins/arm/v7/opdefs/A88273_uxtah.d new file mode 100644 index 0000000..9a30d32 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88273_uxtah.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UXTAH + +@id 265 + +@desc { + + Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 789 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtah ?reg_D reg_N reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 790 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtah ?reg_D reg_N reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88274_uxtb.d b/plugins/arm/v7/opdefs/A88274_uxtb.d new file mode 100644 index 0000000..d2a46ae --- /dev/null +++ b/plugins/arm/v7/opdefs/A88274_uxtb.d @@ -0,0 +1,105 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UXTB + +@id 266 + +@desc { + + Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 1 1 Rm(3) Rd(3) + + @syntax { + + @subid 791 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) + + } + + @asm uxtb ?reg_D reg_M ?rotation + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 792 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtb.w ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 793 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtb ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88275_uxtb16.d b/plugins/arm/v7/opdefs/A88275_uxtb16.d new file mode 100644 index 0000000..f1b3384 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88275_uxtb16.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UXTB16 + +@id 267 + +@desc { + + Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 794 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtb16 ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 795 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtb16 ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88276_uxth.d b/plugins/arm/v7/opdefs/A88276_uxth.d new file mode 100644 index 0000000..90c3310 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88276_uxth.d @@ -0,0 +1,105 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title UXTH + +@id 268 + +@desc { + + Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) + + @syntax { + + @subid 796 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) + + } + + @asm uxth ?reg_D reg_M ?rotation + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) + + @syntax { + + @subid 797 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxth.w ?reg_D reg_M ?rotation + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) + + @syntax { + + @subid 798 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxth ?reg_D reg_M ?rotation + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8827_bx.d b/plugins/arm/v7/opdefs/A8827_bx.d new file mode 100644 index 0000000..64ad628 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8827_bx.d @@ -0,0 +1,91 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BX + +@id 26 + +@desc { + + Branch and Exchange causes a branch to an address and instruction set specified by a register. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0 + + @syntax { + + @subid 93 + + @conv { + + reg_M = Register(Rm) + + } + + @asm bx reg_M + + } + + @hooks { + + fetch = help_fetching_with_instruction_bx_from_thumb + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 94 + + @conv { + + reg_M = Register(Rm) + + } + + @asm bx reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + fetch = help_fetching_with_instruction_bx_from_thumb + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8828_bxj.d b/plugins/arm/v7/opdefs/A8828_bxj.d new file mode 100644 index 0000000..7c6ddb5 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8828_bxj.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title BXJ + +@id 27 + +@desc { + + Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 95 + + @conv { + + reg_M = Register(Rm) + + } + + @asm bxj reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) + + @syntax { + + @subid 96 + + @conv { + + reg_M = Register(Rm) + + } + + @asm bxj reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8829_cb.d b/plugins/arm/v7/opdefs/A8829_cb.d new file mode 100644 index 0000000..5e004b7 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8829_cb.d @@ -0,0 +1,89 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CBNZ, CBZ + +@id 28 + +@desc { + + Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. + +} + +@encoding (t1) { + + @half 1 0 1 1 op(1) 0 i(1) 1 imm5(5) Rn(3) + + @syntax { + + @subid 97 + + @assert { + + op == 0 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) + + } + + @asm cbz reg_N imm32 + + } + + @syntax { + + @subid 98 + + @assert { + + op == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) + + } + + @asm cbnz reg_N imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_cb_n_z + link = handle_comp_and_branch_if_true_as_link + post = post_process_comp_and_branch_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/A882_adc.d b/plugins/arm/v7/opdefs/A882_adc.d new file mode 100644 index 0000000..aaca002 --- /dev/null +++ b/plugins/arm/v7/opdefs/A882_adc.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADC (register) + +@id 1 + +@desc { + + Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) + + @syntax { + + @subid 4 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm adc ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 5 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm adc.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 6 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm adcs.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 7 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 8 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8830_cdp.d b/plugins/arm/v7/opdefs/A8830_cdp.d new file mode 100644 index 0000000..32fc2f1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8830_cdp.d @@ -0,0 +1,133 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CDP, CDP2 + +@id 29 + +@desc { + + Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax { + + @subid 99 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax { + + @subid 100 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax { + + @subid 101 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) + + @syntax { + + @subid 102 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8832_clrex.d b/plugins/arm/v7/opdefs/A8832_clrex.d new file mode 100644 index 0000000..5edfb58 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8832_clrex.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CLREX + +@id 31 + +@desc { + + Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 + + @syntax { + + @subid 103 + + @asm clrex + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 + + @syntax { + + @subid 104 + + @asm clrex + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8833_clz.d b/plugins/arm/v7/opdefs/A8833_clz.d new file mode 100644 index 0000000..7cbb51c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8833_clz.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CLZ + +@id 32 + +@desc { + + Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 1 0 1 0 1 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) + + @syntax { + + @subid 105 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm clz reg_D reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 1 1 1 1 Rd(4) 1 1 1 1 0 0 0 1 Rm(4) + + @syntax { + + @subid 106 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm clz reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8834_cmn.d b/plugins/arm/v7/opdefs/A8834_cmn.d new file mode 100644 index 0000000..45462c7 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8834_cmn.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CMN (immediate) + +@id 33 + +@desc { + + Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax { + + @subid 107 + + @conv { + + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm cmn reg_N imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax { + + @subid 108 + + @conv { + + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm cmn reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8835_cmn.d b/plugins/arm/v7/opdefs/A8835_cmn.d new file mode 100644 index 0000000..55c281c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8835_cmn.d @@ -0,0 +1,104 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CMN (register) + +@id 34 + +@desc { + + Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) + + @syntax { + + @subid 109 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm cmn reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax { + + @subid 110 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm cmn.w reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 111 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm cmn reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8836_cmn.d b/plugins/arm/v7/opdefs/A8836_cmn.d new file mode 100644 index 0000000..e1052a8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8836_cmn.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CMN (register-shifted register) + +@id 35 + +@desc { + + Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 112 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm cmn reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8837_cmp.d b/plugins/arm/v7/opdefs/A8837_cmp.d new file mode 100644 index 0000000..261467b --- /dev/null +++ b/plugins/arm/v7/opdefs/A8837_cmp.d @@ -0,0 +1,102 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CMP (immediate) + +@id 36 + +@desc { + + Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (t1) { + + @half 0 0 1 0 1 Rn(3) imm8(8) + + @syntax { + + @subid 113 + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm cmp reg_N imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) + + @syntax { + + @subid 114 + + @conv { + + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm cmp.w reg_N imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 1 0 1 Rn(4) 0 0 0 0 imm12(12) + + @syntax { + + @subid 115 + + @conv { + + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm cmp reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8838_cmp.d b/plugins/arm/v7/opdefs/A8838_cmp.d new file mode 100644 index 0000000..401e4ac --- /dev/null +++ b/plugins/arm/v7/opdefs/A8838_cmp.d @@ -0,0 +1,125 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CMP (register) + +@id 37 + +@desc { + + Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3) + + @syntax { + + @subid 116 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm cmp reg_N reg_M + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3) + + @syntax { + + @subid 117 + + @conv { + + reg_N = Register(N:Rn) + reg_M = Register(Rm) + + } + + @asm cmp reg_N reg_M + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax { + + @subid 118 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm cmp.w reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 119 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm cmp reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8839_cmp.d b/plugins/arm/v7/opdefs/A8839_cmp.d new file mode 100644 index 0000000..6bdafb3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8839_cmp.d @@ -0,0 +1,63 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CMP (register-shifted register) + +@id 38 + +@desc { + + Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 120 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm cmp reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A883_adc.d b/plugins/arm/v7/opdefs/A883_adc.d new file mode 100644 index 0000000..0270402 --- /dev/null +++ b/plugins/arm/v7/opdefs/A883_adc.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADC (register-shifted register) + +@id 2 + +@desc { + + Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 9 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adc ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 10 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adcs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88424_wfe.d b/plugins/arm/v7/opdefs/A88424_wfe.d new file mode 100644 index 0000000..6c245a2 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88424_wfe.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title WFE + +@id 349 + +@desc { + + Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs, including events signaled by executing the SEV instruction on any processor in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. In an implementation that includes the Virtualization Extensions, if HCR.TWE is set to 1, execution of a WFE instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWE bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 + + @syntax { + + @subid 1979 + + @asm wfe + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 + + @syntax { + + @subid 1980 + + @asm wfe.w + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 + + @syntax { + + @subid 1981 + + @asm wfe + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88425_wfi.d b/plugins/arm/v7/opdefs/A88425_wfi.d new file mode 100644 index 0000000..ef3c73b --- /dev/null +++ b/plugins/arm/v7/opdefs/A88425_wfi.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title WFI + +@id 350 + +@desc { + + Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 + + @syntax { + + @subid 1982 + + @asm wfi + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 + + @syntax { + + @subid 1983 + + @asm wfi.w + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 + + @syntax { + + @subid 1984 + + @asm wfi + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88426_yield.d b/plugins/arm/v7/opdefs/A88426_yield.d new file mode 100644 index 0000000..f782682 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88426_yield.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title YIELD + +@id 351 + +@desc { + + YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 + + @syntax { + + @subid 1985 + + @asm yield + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 + + @syntax { + + @subid 1986 + + @asm yield.w + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 + + @syntax { + + @subid 1987 + + @asm yield + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8842_dbg.d b/plugins/arm/v7/opdefs/A8842_dbg.d new file mode 100644 index 0000000..d053ca3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8842_dbg.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title DBG + +@id 41 + +@desc { + + Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 option(4) + + @syntax { + + @subid 121 + + @conv { + + direct_option = UInt(option) + + } + + @asm dbg direct_option + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 option(4) + + @syntax { + + @subid 122 + + @conv { + + direct_option = UInt(option) + + } + + @asm dbg direct_option + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8843_dmb.d b/plugins/arm/v7/opdefs/A8843_dmb.d new file mode 100644 index 0000000..b8d9717 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8843_dmb.d @@ -0,0 +1,73 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title DMB + +@id 42 + +@desc { + + Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 option(4) + + @syntax { + + @subid 123 + + @conv { + + direct_option = UInt(option) + + } + + @asm dmb ?direct_option + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 option(4) + + @syntax { + + @subid 124 + + @conv { + + direct_option = UInt(option) + + } + + @asm dmb ?direct_option + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8844_dsb.d b/plugins/arm/v7/opdefs/A8844_dsb.d new file mode 100644 index 0000000..e8ede64 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8844_dsb.d @@ -0,0 +1,73 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title DSB + +@id 43 + +@desc { + + Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 option(4) + + @syntax { + + @subid 125 + + @conv { + + direct_option = UInt(option) + + } + + @asm dsb ?direct_option + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 option(4) + + @syntax { + + @subid 126 + + @conv { + + direct_option = UInt(option) + + } + + @asm dsb ?direct_option + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8846_eor.d b/plugins/arm/v7/opdefs/A8846_eor.d new file mode 100644 index 0000000..dfafa9b --- /dev/null +++ b/plugins/arm/v7/opdefs/A8846_eor.d @@ -0,0 +1,145 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title EOR (immediate) + +@id 45 + +@desc { + + Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 127 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm eor ?reg_D reg_N const + + } + + @syntax { + + @subid 128 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm eors ?reg_D reg_N const + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 129 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eor ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 130 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eors ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8847_eor.d b/plugins/arm/v7/opdefs/A8847_eor.d new file mode 100644 index 0000000..f6e3387 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8847_eor.d @@ -0,0 +1,171 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title EOR (register) + +@id 46 + +@desc { + + Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) + + @syntax { + + @subid 131 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm eor ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 132 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm eor.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 133 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm eors.w ?reg_D reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 134 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm eor ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 135 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm eors ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8848_eor.d b/plugins/arm/v7/opdefs/A8848_eor.d new file mode 100644 index 0000000..94f0e92 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8848_eor.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title EOR (register-shifted register) + +@id 47 + +@desc { + + Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 136 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm eor ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 137 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm eors ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A884_add.d b/plugins/arm/v7/opdefs/A884_add.d new file mode 100644 index 0000000..c35685f --- /dev/null +++ b/plugins/arm/v7/opdefs/A884_add.d @@ -0,0 +1,149 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (immediate, Thumb) + +@id 3 + +@desc { + + This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) + + @syntax { + + @subid 11 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) + + } + + @asm add ?reg_D reg_N imm32 + + } + +} + +@encoding (t2) { + + @half 0 0 1 1 0 Rdn(3) imm8(8) + + @syntax { + + @subid 12 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm add ?reg_D reg_N imm32 + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 13 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm add.w ?reg_D reg_N imm32 + + } + + @syntax { + + @subid 14 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adds.w ?reg_D reg_N imm32 + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 15 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm addw ?reg_D reg_N imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8854_it.d b/plugins/arm/v7/opdefs/A8854_it.d new file mode 100644 index 0000000..5d0fe36 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8854_it.d @@ -0,0 +1,59 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title IT + +@id 48 + +@desc { + + If-Then makes up to four following instructions (the IT block) conditional. The conditions for the instructions in the IT block are the same as, or the inverse of, the condition the IT instruction specifies for the first instruction in the block. The IT instruction itself does not affect the condition flags, but the execution of the instructions in the IT block can change the condition flags. 16-bit instructions in the IT block, other than CMP, CMN and TST, do not set the condition flags. An IT instruction with the AL condition can be used to get this changed behavior without conditional execution. The architecture permits exception return to an instruction in the IT block only if the restoration of the CPSR restores ITSTATE to a state consistent with the conditions specified by the IT instruction. Any other exception return to an instruction in an IT block is UNPREDICTABLE. Any branch to a target instruction in an IT block is not permitted, and if such a branch is made it is UNPREDICTABLE what condition is used when executing that target instruction and any subsequent instruction in the IT block. See also Conditional instructions on page A4-162 and Conditional execution on page A8-288. + +} + +@encoding (t1) { + + @half 1 0 1 1 1 1 1 1 firstcond(4) mask(4) + + @syntax { + + @subid 138 + + @conv { + + it_cond = ITCond(firstcond, mask) + + } + + @asm it it_cond + + } + + @hooks { + + fetch = build_it_instruction_suffix + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8855_ldc.d b/plugins/arm/v7/opdefs/A8855_ldc.d new file mode 100644 index 0000000..958adb1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8855_ldc.d @@ -0,0 +1,461 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDC, LDC2 (immediate) + +@id 49 + +@desc { + + Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 139 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 140 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 141 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 142 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 143 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 144 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 145 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 146 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 147 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 148 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 149 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 150 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 151 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 152 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 153 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldc cp direct_CRd maccess + + } + + @syntax { + + @subid 154 + + @assert { + + P == 0 + W == 0 + U == 1 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8856_ldc.d b/plugins/arm/v7/opdefs/A8856_ldc.d new file mode 100644 index 0000000..3cead5c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8856_ldc.d @@ -0,0 +1,201 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDC, LDC2 (literal) + +@id 50 + +@desc { + + Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 155 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 156 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 157 + + @assert { + + P == 0 + U == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_PC = Register(15) + maccess = MemAccessOffset(reg_PC, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + + @syntax { + + @subid 158 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) + + @syntax { + + @subid 159 + + @assert { + + P == 0 + U == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + reg_PC = Register(15) + maccess = MemAccessOffset(reg_PC, NULL) + option = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd maccess option + + } + + @syntax { + + @subid 160 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + cp = CoProcessor(coproc) + direct_CRd = UInt(CRd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldc cp direct_CRd imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8857_ldm.d b/plugins/arm/v7/opdefs/A8857_ldm.d new file mode 100644 index 0000000..817a2a2 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8857_ldm.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDM/LDMIA/LDMFD (Thumb) + +@id 51 + +@desc { + + Load Multiple Increment After (Load Multiple Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (t1) { + + @half 1 1 0 0 1 Rn(3) register_list(8) + + @syntax { + + @subid 161 + + @conv { + + reg_N = Register(Rn) + wb_reg = UncheckedWrittenBackReg(reg_N) + registers = RegList('00000000':register_list) + + } + + @asm ldm wb_reg registers + + } + + @hooks { + + fetch = apply_write_back_from_registers + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 0 1 0 W(1) 1 Rn(4) P(1) M(1) 0 register_list(13) + + @syntax { + + @subid 162 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(P:M:'0':register_list) + + } + + @asm ldm.w wb_reg registers + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8858_ldm.d b/plugins/arm/v7/opdefs/A8858_ldm.d new file mode 100644 index 0000000..a5670e8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8858_ldm.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDM/LDMIA/LDMFD (ARM) + +@id 52 + +@desc { + + Load Multiple Increment After (Load Multiple Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 1 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 163 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldm wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8859_ldmda.d b/plugins/arm/v7/opdefs/A8859_ldmda.d new file mode 100644 index 0000000..cc8ee05 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8859_ldmda.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDMDA/LDMFA + +@id 53 + +@desc { + + Load Multiple Decrement After (Load Multiple Full Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 0 0 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 164 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldmda wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A885_add.d b/plugins/arm/v7/opdefs/A885_add.d new file mode 100644 index 0000000..87b92a6 --- /dev/null +++ b/plugins/arm/v7/opdefs/A885_add.d @@ -0,0 +1,95 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (immediate, ARM) + +@id 4 + +@desc { + + This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) + + @syntax { + + @subid 16 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm add ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 17 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adds ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8860_ldmdb.d b/plugins/arm/v7/opdefs/A8860_ldmdb.d new file mode 100644 index 0000000..ccc409b --- /dev/null +++ b/plugins/arm/v7/opdefs/A8860_ldmdb.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDMDB/LDMEA + +@id 54 + +@desc { + + Load Multiple Decrement Before (Load Multiple Empty Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the lowest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 1 0 0 W(1) 1 Rn(4) P(1) M(1) 0 register_list(13) + + @syntax { + + @subid 165 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(P:M:'0':register_list) + + } + + @asm ldmdb wb_reg registers + + } + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 0 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 166 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldmdb wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8861_ldmib.d b/plugins/arm/v7/opdefs/A8861_ldmib.d new file mode 100644 index 0000000..3f76523 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8861_ldmib.d @@ -0,0 +1,61 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDMIB/LDMED + +@id 55 + +@desc { + + Load Multiple Increment Before (Load Multiple Empty Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 1 1 0 W(1) 1 Rn(4) register_list(16) + + @syntax { + + @subid 167 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegList(register_list) + + } + + @asm ldmib wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8862_ldr.d b/plugins/arm/v7/opdefs/A8862_ldr.d new file mode 100644 index 0000000..2f8dd08 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8862_ldr.d @@ -0,0 +1,180 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDR (immediate, Thumb) + +@id 56 + +@desc { + + Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) + + @syntax { + + @subid 168 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + +} + +@encoding (t2) { + + @half 1 0 0 1 1 Rt(3) imm8(8) + + @syntax { + + @subid 169 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 170 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr.w reg_T maccess + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 171 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + + @syntax { + + @subid 172 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + + @syntax { + + @subid 173 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8863_ldr.d b/plugins/arm/v7/opdefs/A8863_ldr.d new file mode 100644 index 0000000..9842cc9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8863_ldr.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDR (immediate, ARM) + +@id 57 + +@desc { + + Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 174 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 175 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 176 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8864_ldr.d b/plugins/arm/v7/opdefs/A8864_ldr.d new file mode 100644 index 0000000..c10421f --- /dev/null +++ b/plugins/arm/v7/opdefs/A8864_ldr.d @@ -0,0 +1,123 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDR (literal) + +@id 58 + +@desc { + + Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 0 1 Rt(3) imm8(8) + + @syntax { + + @subid 177 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldr reg_T imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_ldr_literal_from_thumb + post = post_process_ldr_instructions + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 178 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldr.w reg_T imm32 + + } + + @hooks { + + fetch = help_fetching_with_instruction_ldr_literal_from_thumb + post = post_process_ldr_instructions + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 179 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldr reg_T imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @hooks { + + fetch = help_fetching_with_instruction_ldr_literal_from_arm + post = post_process_ldr_instructions + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8865_ldr.d b/plugins/arm/v7/opdefs/A8865_ldr.d new file mode 100644 index 0000000..a810586 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8865_ldr.d @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDR (register, Thumb) + +@id 59 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. + +} + +@encoding (t1) { + + @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 180 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldr reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 181 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldr.w reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8866_ldr.d b/plugins/arm/v7/opdefs/A8866_ldr.d new file mode 100644 index 0000000..6ad2086 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8866_ldr.d @@ -0,0 +1,132 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDR (register, ARM) + +@id 60 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 182 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 183 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 184 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8867_ldrb.d b/plugins/arm/v7/opdefs/A8867_ldrb.d new file mode 100644 index 0000000..0155850 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8867_ldrb.d @@ -0,0 +1,157 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRB (immediate, Thumb) + +@id 61 + +@desc { + + Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) + + @syntax { + + @subid 185 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 186 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb.w reg_T maccess + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 187 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + + @syntax { + + @subid 188 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + + @syntax { + + @subid 189 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8868_ldrb.d b/plugins/arm/v7/opdefs/A8868_ldrb.d new file mode 100644 index 0000000..6c19871 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8868_ldrb.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRB (immediate, ARM) + +@id 62 + +@desc { + + Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 190 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 191 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 192 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8869_ldrb.d b/plugins/arm/v7/opdefs/A8869_ldrb.d new file mode 100644 index 0000000..ca9863d --- /dev/null +++ b/plugins/arm/v7/opdefs/A8869_ldrb.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRB (literal) + +@id 63 + +@desc { + + Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 193 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldrb reg_T imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 194 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldrb reg_T imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A886_add.d b/plugins/arm/v7/opdefs/A886_add.d new file mode 100644 index 0000000..856272e --- /dev/null +++ b/plugins/arm/v7/opdefs/A886_add.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (register, Thumb) + +@id 5 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) + + @syntax { + + @subid 18 + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm add ?reg_D reg_N reg_M + + } + +} + +@encoding (t2) { + + @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) + + @syntax { + + @subid 19 + + @conv { + + reg_D = Register(DN:Rdn) + reg_N = Register(DN:Rdn) + reg_M = Register(Rm) + + } + + @asm add ?reg_D reg_N reg_M + + } + +} + +@encoding (T3) { + + @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @subid 20 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_N reg_M ?shift + + } + + @syntax { + + @subid 21 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm adds.w ?reg_D reg_N reg_M ?shift + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8870_ldrb.d b/plugins/arm/v7/opdefs/A8870_ldrb.d new file mode 100644 index 0000000..c20c8cc --- /dev/null +++ b/plugins/arm/v7/opdefs/A8870_ldrb.d @@ -0,0 +1,179 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRB (register) + +@id 64 + +@desc { + + Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 195 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrb reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 196 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrb.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 197 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 198 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 199 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8871_ldrbt.d b/plugins/arm/v7/opdefs/A8871_ldrbt.d new file mode 100644 index 0000000..5aacaf1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8871_ldrbt.d @@ -0,0 +1,115 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRBT + +@id 65 + +@desc { + + Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 200 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrbt reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 201 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrbt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 1 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 202 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrbt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8872_ldrd.d b/plugins/arm/v7/opdefs/A8872_ldrd.d new file mode 100644 index 0000000..e27a114 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8872_ldrd.d @@ -0,0 +1,213 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRD (immediate) + +@id 66 + +@desc { + + Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) Rt2(4) imm8(8) + + @syntax { + + @subid 203 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + + @syntax { + + @subid 204 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + + @syntax { + + @subid 205 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax { + + @subid 206 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 207 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 208 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8873_ldrd.d b/plugins/arm/v7/opdefs/A8873_ldrd.d new file mode 100644 index 0000000..d3d44c3 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8873_ldrd.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRD (literal) + +@id 67 + +@desc { + + Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) Rt2(4) imm8(8) + + @syntax { + + @subid 209 + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm ldrd reg_T reg_T2 imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 0 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax { + + @subid 210 + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @asm ldrd reg_T reg_T2 imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8874_ldrd.d b/plugins/arm/v7/opdefs/A8874_ldrd.d new file mode 100644 index 0000000..e48844d --- /dev/null +++ b/plugins/arm/v7/opdefs/A8874_ldrd.d @@ -0,0 +1,132 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRD (register) + +@id 68 + +@desc { + + Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) + + @syntax { + + @subid 211 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 212 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 213 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8875_ldrex.d b/plugins/arm/v7/opdefs/A8875_ldrex.d new file mode 100644 index 0000000..39c708c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8875_ldrex.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDREX + +@id 69 + +@desc { + + Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) + + @syntax { + + @subid 214 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrex reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax { + + @subid 215 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrex reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8876_ldrexb.d b/plugins/arm/v7/opdefs/A8876_ldrexb.d new file mode 100644 index 0000000..4a00839 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8876_ldrexb.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDREXB + +@id 70 + +@desc { + + Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 1 1 1 1 + + @syntax { + + @subid 216 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm ldrexb reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax { + + @subid 217 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm ldrexb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8877_ldrexd.d b/plugins/arm/v7/opdefs/A8877_ldrexd.d new file mode 100644 index 0000000..44a6984 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8877_ldrexd.d @@ -0,0 +1,85 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDREXD + +@id 71 + +@desc { + + Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1 + + @syntax { + + @subid 218 + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm ldrexd reg_T reg_T2 maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax { + + @subid 219 + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm ldrexd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8878_ldrexh.d b/plugins/arm/v7/opdefs/A8878_ldrexh.d new file mode 100644 index 0000000..8687ded --- /dev/null +++ b/plugins/arm/v7/opdefs/A8878_ldrexh.d @@ -0,0 +1,83 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDREXH + +@id 72 + +@desc { + + Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 1 1 1 1 + + @syntax { + + @subid 220 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm ldrexh reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 + + @syntax { + + @subid 221 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm ldrexh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8879_ldrh.d b/plugins/arm/v7/opdefs/A8879_ldrh.d new file mode 100644 index 0000000..2fcbd0c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8879_ldrh.d @@ -0,0 +1,157 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRH (immediate, Thumb) + +@id 73 + +@desc { + + Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 1 0 0 0 1 imm5(5) Rn(3) Rt(3) + + @syntax { + + @subid 222 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 1 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 223 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh.w reg_T maccess + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 224 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + + @syntax { + + @subid 225 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + + @syntax { + + @subid 226 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A887_add.d b/plugins/arm/v7/opdefs/A887_add.d new file mode 100644 index 0000000..6105f18 --- /dev/null +++ b/plugins/arm/v7/opdefs/A887_add.d @@ -0,0 +1,97 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (register, ARM) + +@id 6 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 22 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 23 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8880_ldrh.d b/plugins/arm/v7/opdefs/A8880_ldrh.d new file mode 100644 index 0000000..a517a23 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8880_ldrh.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRH (immediate, ARM) + +@id 74 + +@desc { + + Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax { + + @subid 227 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 228 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 229 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8881_ldrh.d b/plugins/arm/v7/opdefs/A8881_ldrh.d new file mode 100644 index 0000000..000974f --- /dev/null +++ b/plugins/arm/v7/opdefs/A8881_ldrh.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRH (literal) + +@id 75 + +@desc { + + Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 230 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldrh reg_T imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax { + + @subid 231 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @asm ldrh reg_T imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8882_ldrh.d b/plugins/arm/v7/opdefs/A8882_ldrh.d new file mode 100644 index 0000000..9697112 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8882_ldrh.d @@ -0,0 +1,176 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRH (register) + +@id 76 + +@desc { + + Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 1 0 1 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 232 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 233 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrh.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax { + + @subid 234 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 235 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 236 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8883_ldrht.d b/plugins/arm/v7/opdefs/A8883_ldrht.d new file mode 100644 index 0000000..e02c949 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8883_ldrht.d @@ -0,0 +1,114 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRHT + +@id 77 + +@desc { + + Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 237 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrht reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax { + + @subid 238 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrht reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax { + + @subid 239 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrht reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8884_ldrsb.d b/plugins/arm/v7/opdefs/A8884_ldrsb.d new file mode 100644 index 0000000..bacfa6a --- /dev/null +++ b/plugins/arm/v7/opdefs/A8884_ldrsb.d @@ -0,0 +1,230 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSB (immediate) + +@id 78 + +@desc { + + Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 0 0 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 240 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 241 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + + @syntax { + + @subid 242 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + + @syntax { + + @subid 243 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax { + + @subid 244 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 245 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 246 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8885_ldrsb.d b/plugins/arm/v7/opdefs/A8885_ldrsb.d new file mode 100644 index 0000000..6ea8617 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8885_ldrsb.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSB (literal) + +@id 79 + +@desc { + + Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 247 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldrsb reg_T imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax { + + @subid 248 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @asm ldrsb reg_T imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8886_ldrsb.d b/plugins/arm/v7/opdefs/A8886_ldrsb.d new file mode 100644 index 0000000..1dbd651 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8886_ldrsb.d @@ -0,0 +1,176 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSB (register) + +@id 80 + +@desc { + + Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 249 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 250 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrsb.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) + + @syntax { + + @subid 251 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 252 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 253 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8887_ldrsbt.d b/plugins/arm/v7/opdefs/A8887_ldrsbt.d new file mode 100644 index 0000000..fc145ac --- /dev/null +++ b/plugins/arm/v7/opdefs/A8887_ldrsbt.d @@ -0,0 +1,114 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSBT + +@id 81 + +@desc { + + Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 254 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsbt reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax { + + @subid 255 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsbt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) + + @syntax { + + @subid 256 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsbt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8888_ldrsh.d b/plugins/arm/v7/opdefs/A8888_ldrsh.d new file mode 100644 index 0000000..b908ec1 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8888_ldrsh.d @@ -0,0 +1,230 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSH (immediate) + +@id 82 + +@desc { + + Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 0 1 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 257 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax { + + @subid 258 + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + + @syntax { + + @subid 259 + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + + @syntax { + + @subid 260 + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax { + + @subid 261 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 262 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 263 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8889_ldrsh.d b/plugins/arm/v7/opdefs/A8889_ldrsh.d new file mode 100644 index 0000000..a3ca43f --- /dev/null +++ b/plugins/arm/v7/opdefs/A8889_ldrsh.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSH (literal) + +@id 83 + +@desc { + + Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 264 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldrsh reg_T imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax { + + @subid 265 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @asm ldrsh reg_T imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A888_add.d b/plugins/arm/v7/opdefs/A888_add.d new file mode 100644 index 0000000..8fd6078 --- /dev/null +++ b/plugins/arm/v7/opdefs/A888_add.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (register-shifted register) + +@id 7 + +@desc { + + Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) + + @syntax { + + @subid 24 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm add ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 25 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adds ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8890_ldrsh.d b/plugins/arm/v7/opdefs/A8890_ldrsh.d new file mode 100644 index 0000000..3efd231 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8890_ldrsh.d @@ -0,0 +1,176 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSH (register) + +@id 84 + +@desc { + + Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (t1) { + + @half 0 1 0 1 1 1 1 Rm(3) Rn(3) Rt(3) + + @syntax { + + @subid 266 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax { + + @subid 267 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrsh.w reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax { + + @subid 268 + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 269 + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 270 + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8891_ldrsht.d b/plugins/arm/v7/opdefs/A8891_ldrsht.d new file mode 100644 index 0000000..ffeb9fd --- /dev/null +++ b/plugins/arm/v7/opdefs/A8891_ldrsht.d @@ -0,0 +1,114 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRSHT + +@id 85 + +@desc { + + Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 271 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsht reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax { + + @subid 272 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsht reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax { + + @subid 273 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsht reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8892_ldrt.d b/plugins/arm/v7/opdefs/A8892_ldrt.d new file mode 100644 index 0000000..86699de --- /dev/null +++ b/plugins/arm/v7/opdefs/A8892_ldrt.d @@ -0,0 +1,115 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDRT + +@id 86 + +@desc { + + Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax { + + @subid 274 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrt reg_T maccess + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) + + @syntax { + + @subid 275 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 276 + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrt reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8894_lsl.d b/plugins/arm/v7/opdefs/A8894_lsl.d new file mode 100644 index 0000000..b8cde63 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8894_lsl.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LSL (immediate) + +@id 88 + +@desc { + + Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) + + @syntax { + + @subid 277 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsl ?reg_D reg_M shift_n + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) + + @syntax { + + @subid 278 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm3:imm2) + + } + + @asm lsl.w ?reg_D reg_M shift_n + + } + + @syntax { + + @subid 279 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm3:imm2) + + } + + @asm lsls.w ?reg_D reg_M shift_n + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) + + @syntax { + + @subid 280 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsl ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 281 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsls ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8895_lsl.d b/plugins/arm/v7/opdefs/A8895_lsl.d new file mode 100644 index 0000000..3cdc75d --- /dev/null +++ b/plugins/arm/v7/opdefs/A8895_lsl.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LSL (register) + +@id 89 + +@desc { + + Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 1 0 Rm(3) Rdn(3) + + @syntax { + + @subid 282 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm lsl ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 283 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsl.w ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 284 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsls.w ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 0 1 Rn(4) + + @syntax { + + @subid 285 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsl ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 286 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsls ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8896_lsr.d b/plugins/arm/v7/opdefs/A8896_lsr.d new file mode 100644 index 0000000..2efcbed --- /dev/null +++ b/plugins/arm/v7/opdefs/A8896_lsr.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LSR (immediate) + +@id 90 + +@desc { + + Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) + + @syntax { + + @subid 287 + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsr ?reg_D reg_M shift_n + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) + + @syntax { + + @subid 288 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm3:imm2) + + } + + @asm lsr.w ?reg_D reg_M shift_n + + } + + @syntax { + + @subid 289 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm3:imm2) + + } + + @asm lsrs.w ?reg_D reg_M shift_n + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) + + @syntax { + + @subid 290 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsr ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 291 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsrs ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8897_lsr.d b/plugins/arm/v7/opdefs/A8897_lsr.d new file mode 100644 index 0000000..6e05dd4 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8897_lsr.d @@ -0,0 +1,167 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LSR (register) + +@id 91 + +@desc { + + Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) + + @syntax { + + @subid 292 + + @conv { + + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) + + } + + @asm lsr ?reg_D reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) + + @syntax { + + @subid 293 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr.w ?reg_D reg_N reg_M + + } + + @syntax { + + @subid 294 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsrs.w ?reg_D reg_N reg_M + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) + + @syntax { + + @subid 295 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 296 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8898_mcr.d b/plugins/arm/v7/opdefs/A8898_mcr.d new file mode 100644 index 0000000..06f5aa2 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8898_mcr.d @@ -0,0 +1,133 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MCR, MCR2 + +@id 92 + +@desc { + + Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 297 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 298 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 299 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) + + @syntax { + + @subid 300 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 + + } + +} + diff --git a/plugins/arm/v7/opdefs/A8899_mcrr.d b/plugins/arm/v7/opdefs/A8899_mcrr.d new file mode 100644 index 0000000..6177a4c --- /dev/null +++ b/plugins/arm/v7/opdefs/A8899_mcrr.d @@ -0,0 +1,129 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MCRR, MCRR2 + +@id 93 + +@desc { + + Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 301 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 302 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 303 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + +@encoding (A2) { + + @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) + + @syntax { + + @subid 304 + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm + + } + +} + diff --git a/plugins/arm/v7/opdefs/A889_add.d b/plugins/arm/v7/opdefs/A889_add.d new file mode 100644 index 0000000..834de50 --- /dev/null +++ b/plugins/arm/v7/opdefs/A889_add.d @@ -0,0 +1,211 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ADD (SP plus immediate) + +@id 8 + +@desc { + + This instruction adds an immediate value to the SP value, and writes the result to the destination register. + +} + +@encoding (t1) { + + @half 1 0 1 0 1 Rd(3) imm8(8) + + @syntax { + + @subid 26 + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm add ?reg_D reg_SP imm32 + + } + +} + +@encoding (t2) { + + @half 1 0 1 1 0 0 0 0 0 imm7(7) + + @syntax { + + @subid 27 + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) + + } + + @asm add ?reg_D reg_SP imm32 + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 28 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm add.w ?reg_D reg_SP imm32 + + } + + @syntax { + + @subid 29 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adds.w ?reg_D reg_SP imm32 + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax { + + @subid 30 + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm addw ?reg_D reg_SP imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) + + @syntax { + + @subid 31 + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm add ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 32 + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm adds ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9310_msr.d b/plugins/arm/v7/opdefs/B9310_msr.d new file mode 100644 index 0000000..79c569a --- /dev/null +++ b/plugins/arm/v7/opdefs/B9310_msr.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MSR (Banked register) + +@id 361 + +@desc { + + Move to Banked or Special register from ARM core register moves the value of an ARM core register to the Banked ARM core register or SPSR of the specified mode, or to ELR_hyp. MSR (Banked register) is UNPREDICTABLE if executed in User mode. The effect of using an MSR (Banked register) instruction with a register argument that is not valid for the current mode is UNPREDICTABLE. For more information see Usage restrictions on the Banked register transfer instructions on page B9-1972. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 0 R(1) Rn(4) 1 0 0 0 m1(4) 0 0 1 m(1) 0 0 0 0 + + @syntax { + + @subid 2012 + + @conv { + + banked_reg = BankedRegister(R, m:m1) + reg_N = Register(Rn) + + } + + @asm msr banked_reg reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 R(1) 1 0 m1(4) 1 1 1 1 0 0 1 m(1) 0 0 0 0 Rn(4) + + @syntax { + + @subid 2013 + + @conv { + + banked_reg = BankedRegister(R, m:m1) + reg_N = Register(Rn) + + } + + @asm msr banked_reg reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9311_msr.d b/plugins/arm/v7/opdefs/B9311_msr.d new file mode 100644 index 0000000..f996e5d --- /dev/null +++ b/plugins/arm/v7/opdefs/B9311_msr.d @@ -0,0 +1,60 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MSR (immediate) + +@id 362 + +@desc { + + Move immediate value to Special register moves selected bits of an immediate value to the CPSR or the SPSR of the current mode. MSR (immediate) is UNPREDICTABLE if: • In Non-debug state, it is attempting to update the CPSR, and that update would change to a mode that is not permitted in the context in which the instruction is executed, see Restrictions on updates to the CPSR.M field on page B9-1970. • In Debug state, it is attempting an update to the CPSR with a value that is not . See Behavior of MRS and MSR instructions that access the CPSR in Debug state on page C5-2097. An MSR (immediate) executed in User mode: • is UNPREDICTABLE if it attempts to update the SPSR • otherwise, does not update any CPSR field that is accessible only at PL1 or higher, Note MSR (immediate) on page A8-498 describes the valid application level uses of the MSR (immediate) instruction. An MSR (immediate) executed in System mode is UNPREDICTABLE if it attempts to update the SPSR. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 0 R(1) 1 0 mask(4) 1 1 1 1 imm12(12) + + @syntax { + + @subid 2014 + + @conv { + + spec_reg = SpecRegFromMask(mask) + imm32 = ARMExpandImm(imm12) + + } + + @asm msr spec_reg imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9312_msr.d b/plugins/arm/v7/opdefs/B9312_msr.d new file mode 100644 index 0000000..76ae378 --- /dev/null +++ b/plugins/arm/v7/opdefs/B9312_msr.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MSR (register) + +@id 363 + +@desc { + + Move to Special register from ARM core register moves the value of an ARM core register to the CPSR or the SPSR of the current mode. MSR (register) is UNPREDICTABLE if: • In Non-debug state, it is attempting to update the CPSR, and that update would change to a mode that is not permitted in the context in which the instruction is executed, see Restrictions on updates to the CPSR.M field on page B9-1970. • In Debug state, it is attempting an update to the CPSR with a value that is not . See Behavior of MRS and MSR instructions that access the CPSR in Debug state on page C5-2097. An MSR (register) executed in User mode: • is UNPREDICTABLE if it attempts to update the SPSR • otherwise, does not update any CPSR field that is accessible only at PL1 or higher, Note MSR (register) on page A8-500 describes the valid application level uses of the MSR (register) instruction. An MSR (register) executed in System mode is UNPREDICTABLE if it attempts to update the SPSR. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 0 0 R(1) Rn(4) 1 0 0 0 mask(4) 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2015 + + @conv { + + spec_reg = SpecRegFromMask(mask) + reg_N = Register(Rn) + + } + + @asm msr spec_reg reg_N + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 R(1) 1 0 mask(4) 1 1 1 1 0 0 0 0 0 0 0 0 Rn(4) + + @syntax { + + @subid 2016 + + @conv { + + spec_reg = SpecRegFromMask(mask) + reg_N = Register(Rn) + + } + + @asm msr spec_reg reg_N + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9313_rfe.d b/plugins/arm/v7/opdefs/B9313_rfe.d new file mode 100644 index 0000000..fae2d56 --- /dev/null +++ b/plugins/arm/v7/opdefs/B9313_rfe.d @@ -0,0 +1,169 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title RFE + +@id 364 + +@desc { + + Return From Exception loads the PC and the CPSR from the word at the specified address and the following word respectively. For information about memory accesses see Memory accesses on page A8-294. RFE is: • UNDEFINED in Hyp mode. • UNPREDICTABLE in: — The cases described in Restrictions on exception return instructions on page B9-1970. Note As identified in Restrictions on exception return instructions on page B9-1970, RFE differs from other exception return instructions in that it can be executed in System mode. — Debug state. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2017 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + + } + + @asm rfedb wb_reg + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 1 1 0 W(1) 1 Rn(4) 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2018 + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + + } + + @asm rfeia wb_reg + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 P(1) U(1) 0 W(1) 1 Rn(4) 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2019 + + @assert { + + P == 0 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + + } + + @asm rfeda wb_reg + + } + + @syntax { + + @subid 2020 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + + } + + @asm rfedb wb_reg + + } + + @syntax { + + @subid 2021 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + + } + + @asm rfeia wb_reg + + } + + @syntax { + + @subid 2022 + + @assert { + + P == 1 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + + } + + @asm rfeib wb_reg + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9314_smc.d b/plugins/arm/v7/opdefs/B9314_smc.d new file mode 100644 index 0000000..cf2bcf2 --- /dev/null +++ b/plugins/arm/v7/opdefs/B9314_smc.d @@ -0,0 +1,79 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SMC (previously SMI) + +@id 365 + +@desc { + + Secure Monitor Call causes a Secure Monitor Call exception. For more information see Secure Monitor Call (SMC) exception on page B1-1210. SMC is available only from software executing at PL1 or higher. It is UNDEFINED in User mode. In an implementation that includes the Virtualization Extensions: • If HCR.TSC is set to 1, execution of an SMC instruction in a Non-secure PL1 mode generates a Hyp Trap exception, regardless of the value of SCR.SCD. For more information see Trapping use of the SMC instruction on page B1-1254. • Otherwise, when SCR.SCD is set to 1, the SMC instruction is: — UNDEFINED in Non-secure state — UNPREDICTABLE if executed in a Secure PL1 mode. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2023 + + @conv { + + direct_imm4 = UInt(imm4) + + } + + @asm smc direct_imm4 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 imm4(4) + + @syntax { + + @subid 2024 + + @conv { + + direct_imm4 = UInt(imm4) + + } + + @asm smc direct_imm4 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9315_srs.d b/plugins/arm/v7/opdefs/B9315_srs.d new file mode 100644 index 0000000..e03935c --- /dev/null +++ b/plugins/arm/v7/opdefs/B9315_srs.d @@ -0,0 +1,77 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SRS (Thumb) + +@id 366 + +@desc { + + Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode. For information about memory accesses see Memory accesses on page A8-294. SRS is: • UNDEFINED in Hyp mode • UNPREDICTABLE if: — it is executed in ThumbEE state — it is executed in User or System mode — it attempts to store the Monitor mode SP when in Non-secure state — NSACR.RFR is set to 1 and it attempts to store the FIQ mode SP when in Non-secure state — it attempts to store the Hyp mode SP. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 0 W(1) 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 mode(5) + + @syntax { + + @subid 2025 + + @conv { + + reg_SP = Register(13) + wb_reg = WrittenBackReg(reg_SP, W) + direct_mode = UInt(mode) + + } + + @asm srsdb wb_reg direct_mode + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 0 1 1 0 W(1) 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 mode(5) + + @syntax { + + @subid 2026 + + @conv { + + reg_SP = Register(13) + wb_reg = WrittenBackReg(reg_SP, W) + direct_mode = UInt(mode) + + } + + @asm srsia wb_reg direct_mode + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9316_srs.d b/plugins/arm/v7/opdefs/B9316_srs.d new file mode 100644 index 0000000..2fbdb5d --- /dev/null +++ b/plugins/arm/v7/opdefs/B9316_srs.d @@ -0,0 +1,131 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SRS (ARM) + +@id 367 + +@desc { + + Store Return State stores the LR and SPSR of the current mode to the stack of a specified mode. For information about memory accesses see Memory accesses on page A8-294. SRS is: • UNDEFINED in Hyp mode • UNPREDICTABLE if: — it is executed in User or System mode — it attempts to store the Monitor mode SP when in Non-secure state — NSACR.RFR is set to 1 and it attempts to store the FIQ mode SP when in Non-secure state — if it attempts to store the Hyp mode SP. + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 P(1) U(1) 1 W(1) 0 1 1 0 1 0 0 0 0 0 1 0 1 0 0 0 mode(5) + + @syntax { + + @subid 2027 + + @assert { + + P == 0 + U == 0 + + } + + @conv { + + reg_SP = Register(13) + wb_reg = WrittenBackReg(reg_SP, W) + direct_mode = UInt(mode) + + } + + @asm srsda wb_reg direct_mode + + } + + @syntax { + + @subid 2028 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_SP = Register(13) + wb_reg = WrittenBackReg(reg_SP, W) + direct_mode = UInt(mode) + + } + + @asm srsdb wb_reg direct_mode + + } + + @syntax { + + @subid 2029 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_SP = Register(13) + wb_reg = WrittenBackReg(reg_SP, W) + direct_mode = UInt(mode) + + } + + @asm srsia wb_reg direct_mode + + } + + @syntax { + + @subid 2030 + + @assert { + + P == 1 + U == 1 + + } + + @conv { + + reg_SP = Register(13) + wb_reg = WrittenBackReg(reg_SP, W) + direct_mode = UInt(mode) + + } + + @asm srsib wb_reg direct_mode + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9317_stm.d b/plugins/arm/v7/opdefs/B9317_stm.d new file mode 100644 index 0000000..552640f --- /dev/null +++ b/plugins/arm/v7/opdefs/B9317_stm.d @@ -0,0 +1,151 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title STM (User registers) + +@id 368 + +@desc { + + In a PL1 mode other than System mode, Store Multiple (user registers) stores multiple User mode registers to consecutive memory locations using an address from a base register. The processor reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register. STM (User registers) is UNDEFINED in Hyp mode, and UNPREDICTABLE in User or System modes. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 P(1) U(1) 1 0 0 Rn(4) register_list(16) + + @syntax { + + @subid 2031 + + @assert { + + P == 0 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegList(register_list) + + } + + @asm stmda reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2032 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegList(register_list) + + } + + @asm stmdb reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2033 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegList(register_list) + + } + + @asm stmia reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2034 + + @assert { + + P == 1 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegList(register_list) + + } + + @asm stmib reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9319_subs.d b/plugins/arm/v7/opdefs/B9319_subs.d new file mode 100644 index 0000000..eaf6eca --- /dev/null +++ b/plugins/arm/v7/opdefs/B9319_subs.d @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUBS PC, LR (Thumb) + +@id 370 + +@desc { + + The SUBS PC, LR, # instruction provides an exception return without the use of the stack. It subtracts the immediate constant from LR, branches to the resulting address, and also copies the SPSR to the CPSR. Note • The instruction SUBS PC, LR, #0 is equivalent to MOVS PC, LR and ERET. • For an implementation that includes the Virtualization Extensions, ERET is the preferred disassembly of the T1 encoding defined in this section. Therefore, a disassembler might report an ERET where the original assembler code used SUBS PC, LR, #0. When executing in Hyp mode: • the encoding for SUBS PC, LR, #0 is the encoding of the ERET instruction, see ERET on page B9-1980 • SUBS PC, LR, # with a nonzero constant is UNDEFINED. SUBS PC, LR, # is UNPREDICTABLE: • in the cases described in Restrictions on exception return instructions on page B9-1970 • if it is executed in Debug state. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 1 imm8(8) + + @syntax { + + @subid 2035 + + @conv { + + reg_PC = Register(15) + reg_LR = Register(14) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm subs reg_PC reg_LR imm32 + + } + +} + diff --git a/plugins/arm/v7/opdefs/B931_cps.d b/plugins/arm/v7/opdefs/B931_cps.d new file mode 100644 index 0000000..e04d320 --- /dev/null +++ b/plugins/arm/v7/opdefs/B931_cps.d @@ -0,0 +1,147 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CPS (Thumb) + +@id 352 + +@desc { + + Change Processor State changes one or more of the CPSR.{A, I, F} interrupt mask bits and the CPSR.M mode field, without changing the other CPSR bits. CPS is treated as NOP if executed in User mode. CPS is UNPREDICTABLE if it is either: • attempting to change to a mode that is not permitted in the context in which it is executed, see Restrictions on updates to the CPSR.M field on page B9-1970 • executed in Debug state. + +} + +@encoding (t1) { + + @half 1 0 1 1 0 1 1 0 0 1 1 im(1) 0 A(1) I(1) F(1) + + @syntax { + + @subid 1988 + + @assert { + + im == 0 + + } + + @conv { + + iflags = IFlagsDefinition(a, i, f) + + } + + @asm cpsie iflags + + } + + @syntax { + + @subid 1989 + + @assert { + + im == 1 + + } + + @conv { + + iflags = IFlagsDefinition(a, i, f) + + } + + @asm cpsid iflags + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 imod(2) M(1) A(1) I(1) F(1) mode(5) + + @syntax { + + @subid 1990 + + @assert { + + M == 0 + imod == 10 + + } + + @conv { + + iflags = IFlagsDefinition(a, i, f) + + } + + @asm cpsie.w iflags + + } + + @syntax { + + @subid 1991 + + @assert { + + M == 0 + imod == 11 + + } + + @conv { + + iflags = IFlagsDefinition(a, i, f) + + } + + @asm cpsid.w iflags + + } + + @syntax { + + @subid 1992 + + @assert { + + M == 1 + + } + + @conv { + + direct_mode = UInt(mode) + + } + + @asm cps.w direct_mode + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9320_subs.d b/plugins/arm/v7/opdefs/B9320_subs.d new file mode 100644 index 0000000..ed14d60 --- /dev/null +++ b/plugins/arm/v7/opdefs/B9320_subs.d @@ -0,0 +1,95 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title SUBS PC, LR and related instructions (ARM) + +@id 371 + +@desc { + + The SUBS PC, LR, # instruction provides an exception return without the use of the stack. It subtracts the immediate constant from LR, branches to the resulting address, and also copies the SPSR to the CPSR. The ARM instruction set contains similar instructions based on other data-processing operations, or with a wider range of operands, or both. ARM deprecates using these other instructions, except for MOVS PC, LR. All of these instructions are: • UNDEFINED in Hyp mode • UNPREDICTABLE: — in the cases described in Restrictions on exception return instructions on page B9-1970 — if executed in Debug state. + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 opcode(4) 1 Rn(4) 1 1 1 1 imm12(12) + + @syntax { + + @subid 2036 + + @conv { + + reg_PC = Register(15) + reg_LR = Register(14) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs reg_PC reg_LR imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 opcode(4) 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 2037 + + @assert { + + opcode == 1111 + + } + + @conv { + + reg_PC = Register(15) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvns reg_PC reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9321_vmrs.d b/plugins/arm/v7/opdefs/B9321_vmrs.d new file mode 100644 index 0000000..4dcb42d --- /dev/null +++ b/plugins/arm/v7/opdefs/B9321_vmrs.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VMRS + +@id 372 + +@desc { + + Move to ARM core register from Advanced SIMD and Floating-point Extension System Register moves the value of an extension system register to an ARM core register. When the specified Floating-point Extension System Register is the FPSCR, a form of the instruction transfers the FPSCR.{N, Z, C, V} condition flags to the APSR.{N, Z, C, V} condition flags. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute a VMRS instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. When these settings permit the execution of floating-point and Advanced SIMD instructions, if the specified Floating-point Extension System Register is not the FPSCR, the instruction is UNDEFINED if executed in User mode. In an implementation that includes the Virtualization Extensions, when HCR.TID0 is set to 1, any VMRS access to FPSID from a Non-secure PL1 mode, that would be permitted if HCR.TID0 was set to 0, generates a Hyp Trap exception. For more information, see ID group 0, Primary device identification registers on page B1-1251. Note • VMRS on page A8-954 describes the valid application level uses of the VMRS instruction • for simplicity, the VMRS pseudocode does not show the possible trap to Hyp mode. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 1 1 1 1 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0 + + @syntax { + + @subid 2038 + + @conv { + + reg_T = Register(Rt) + spec_reg = SpecRegFromReg(reg) + + } + + @asm vmrs reg_T spec_reg + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 1 0 1 1 1 1 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0 + + @syntax { + + @subid 2039 + + @conv { + + reg_T = Register(Rt) + spec_reg = SpecRegFromReg(reg) + + } + + @asm vmrs reg_T spec_reg + + } + +} + diff --git a/plugins/arm/v7/opdefs/B9322_vmsr.d b/plugins/arm/v7/opdefs/B9322_vmsr.d new file mode 100644 index 0000000..8fdc8ab --- /dev/null +++ b/plugins/arm/v7/opdefs/B9322_vmsr.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VMSR + +@id 373 + +@desc { + + Move to Advanced SIMD and Floating-point Extension System Register from ARM core register moves the value of an ARM core register to a Floating-point system register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute a VMSR instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. When these settings permit the execution of floating-point and Advanced SIMD instructions, if the specified Floating-point Extension System Register is not the FPSCR, the instruction is UNDEFINED if executed in User mode. Note VMSR on page A8-956 describes the valid application level uses of the VMSR instruction. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 1 0 1 1 1 0 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0 + + @syntax { + + @subid 2040 + + @conv { + + spec_reg = SpecRegFromReg(reg) + reg_T = Register(Rt) + + } + + @asm vmsr spec_reg reg_T + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 1 0 1 1 1 0 reg(4) Rt(4) 1 0 1 0 0 0 0 1 0 0 0 0 + + @syntax { + + @subid 2041 + + @conv { + + spec_reg = SpecRegFromReg(reg) + reg_T = Register(Rt) + + } + + @asm vmsr spec_reg reg_T + + } + +} + diff --git a/plugins/arm/v7/opdefs/B932_cps.d b/plugins/arm/v7/opdefs/B932_cps.d new file mode 100644 index 0000000..2d93d60 --- /dev/null +++ b/plugins/arm/v7/opdefs/B932_cps.d @@ -0,0 +1,101 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title CPS (ARM) + +@id 353 + +@desc { + + Change Processor State changes one or more of the CPSR.{A, I, F} interrupt mask bits and the CPSR.M mode field, without changing the other CPSR bits. CPS is treated as NOP if executed in User mode. CPS is UNPREDICTABLE if it is either: • attempting to change to a mode that is not permitted in the context in which it is executed, see Restrictions on updates to the CPSR.M field on page B9-1970 • executed in Debug state. + +} + +@encoding (A1) { + + @word 1 1 1 1 0 0 0 1 0 0 0 0 imod(2) M(1) 0 0 0 0 0 0 0 0 A(1) I(1) F(1) 0 mode(5) + + @syntax { + + @subid 1993 + + @assert { + + M == 0 + imod == 10 + + } + + @conv { + + iflags = IFlagsDefinition(a, i, f) + + } + + @asm cpsie iflags + + } + + @syntax { + + @subid 1994 + + @assert { + + M == 0 + imod == 11 + + } + + @conv { + + iflags = IFlagsDefinition(a, i, f) + + } + + @asm cpsid iflags + + } + + @syntax { + + @subid 1995 + + @assert { + + M == 1 + + } + + @conv { + + direct_mode = UInt(mode) + + } + + @asm cps direct_mode + + } + +} + diff --git a/plugins/arm/v7/opdefs/B933_eret.d b/plugins/arm/v7/opdefs/B933_eret.d new file mode 100644 index 0000000..0beb321 --- /dev/null +++ b/plugins/arm/v7/opdefs/B933_eret.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title ERET + +@id 354 + +@desc { + + When executed in Hyp mode, Exception Return loads the PC from ELR_hyp and loads the CPSR from SPSR_hyp. When executed in a Secure or Non-secure PL1 mode, ERET behaves as: MOVS PC, • LR in the ARM instruction set, see SUBS PC, LR and related instructions (ARM) on page B9-2010 • the equivalent SUBS PC, LR, #0 in the Thumb instruction set, see SUBS PC, LR (Thumb) on page B9-2008. ERET is UNPREDICTABLE: • in the cases described in Restrictions on exception return instructions on page B9-1970 • if it is executed in Debug state. Note In an implementation that includes the Virtualization Extensions: • LR, #0 in the Thumb The T1 encoding of ERET is not a new encoding but, is the preferred synonym of SUBS PC, instruction set. See SUBS PC, LR (Thumb) on page B9-2008 for more information. • Because ERET is the preferred encoding, when decoding Thumb instructions, a disassembler will report an ERET where the original assembler code used SUBS PC, LR, #0. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 0 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 1996 + + @asm eret + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 1 0 + + @syntax { + + @subid 1997 + + @asm eret + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B934_hvc.d b/plugins/arm/v7/opdefs/B934_hvc.d new file mode 100644 index 0000000..e7909a9 --- /dev/null +++ b/plugins/arm/v7/opdefs/B934_hvc.d @@ -0,0 +1,73 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title HVC + +@id 355 + +@desc { + + Hypervisor Call causes a Hypervisor Call exception. For more information see Hypervisor Call (HVC) exception on page B1-1211. Non-secure software executing at PL1 can use this instruction to call the hypervisor to request a service. The HVC instruction is: • UNDEFINED in Secure state, and in User mode in Non-secure state • when SCR.HCE is set to 0, UNDEFINED in Non-secure PL1 modes and UNPREDICTABLE in Hyp mode • UNPREDICTABLE in Debug state. On executing an HVC instruction, the HSR reports the exception as a Hypervisor Call exception, using the EC value 0x12, and captures the value of the immediate argument, see Use of the HSR on page B3-1424. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 1 1 1 1 1 1 0 imm4(4) 1 0 0 0 imm12(12) + + @syntax { + + @subid 1998 + + @conv { + + imm16 = UInt(imm4:imm12) + + } + + @asm hvc imm16 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 1 0 0 imm12(12) 0 1 1 1 imm4(4) + + @syntax { + + @subid 1999 + + @conv { + + imm16 = UInt(imm12:imm4) + + } + + @asm hvc imm16 + + } + +} + diff --git a/plugins/arm/v7/opdefs/B935_ldm.d b/plugins/arm/v7/opdefs/B935_ldm.d new file mode 100644 index 0000000..9563920 --- /dev/null +++ b/plugins/arm/v7/opdefs/B935_ldm.d @@ -0,0 +1,155 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDM (exception return) + +@id 356 + +@desc { + + Load Multiple (exception return) loads multiple registers from consecutive memory locations using an address from a base register. The SPSR of the current mode is copied to the CPSR. An address adjusted by the size of the data loaded can optionally be written back to the base register. The registers loaded include the PC. The word loaded for the PC is treated as an address and a branch occurs to that address. LDM (exception return) is: • UNDEFINED in Hyp mode • UNPREDICTABLE in: — the cases described in Restrictions on exception return instructions on page B9-1970 — Debug state. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) 1 register_list(15) + + @syntax { + + @subid 2000 + + @assert { + + P == 0 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegListWithPC(register_list) + + } + + @asm ldmda wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2001 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegListWithPC(register_list) + + } + + @asm ldmdb wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2002 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegListWithPC(register_list) + + } + + @asm ldmia wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2003 + + @assert { + + P == 1 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + registers = RegListWithPC(register_list) + + } + + @asm ldmib wb_reg registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B936_ldm.d b/plugins/arm/v7/opdefs/B936_ldm.d new file mode 100644 index 0000000..331febc --- /dev/null +++ b/plugins/arm/v7/opdefs/B936_ldm.d @@ -0,0 +1,151 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title LDM (User registers) + +@id 357 + +@desc { + + In a PL1 mode other than System mode, Load Multiple (User registers) loads multiple User mode registers from consecutive memory locations using an address from a base register. The registers loaded cannot include the PC. The processor reads the base register value normally, using the current mode to determine the correct Banked version of the register. This instruction cannot writeback to the base register. LDM (user registers) is UNDEFINED in Hyp mode, and UNPREDICTABLE in User and System modes. + +} + +@encoding (A1) { + + @word cond(4) 1 0 0 P(1) U(1) 1 0 1 Rn(4) 0 register_list(15) + + @syntax { + + @subid 2004 + + @assert { + + P == 0 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegListWithoutPC(register_list) + + } + + @asm ldmda reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2005 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegListWithoutPC(register_list) + + } + + @asm ldmdb reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2006 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegListWithoutPC(register_list) + + } + + @asm ldmia reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @subid 2007 + + @assert { + + P == 1 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + registers = RegListWithoutPC(register_list) + + } + + @asm ldmib reg_N registers + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B938_mrs.d b/plugins/arm/v7/opdefs/B938_mrs.d new file mode 100644 index 0000000..259daae --- /dev/null +++ b/plugins/arm/v7/opdefs/B938_mrs.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MRS + +@id 359 + +@desc { + + Move to Register from Special register moves the value from the CPSR or SPSR of the current mode into an ARM core register. An MRS that accesses the SPSR is UNPREDICTABLE if executed in User or System mode. An MRS that is executed in User mode and accesses the CPSR returns an UNKNOWN value for the CPSR.{E, A, I, F, M} fields. Note MRS on page A8-496 describes the valid application level uses of the MRS instruction. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 1 R(1) 1 1 1 1 1 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2008 + + @conv { + + reg_D = Register(Rd) + spec_reg = SpecRegCSPSR(R) + + } + + @asm mrs reg_D spec_reg + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 R(1) 0 0 1 1 1 1 Rd(4) 0 0 0 0 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2009 + + @conv { + + reg_D = Register(Rd) + spec_reg = SpecRegCSPSR(R) + + } + + @asm mrs reg_D spec_reg + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/B939_mrs.d b/plugins/arm/v7/opdefs/B939_mrs.d new file mode 100644 index 0000000..61db344 --- /dev/null +++ b/plugins/arm/v7/opdefs/B939_mrs.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title MRS (Banked register) + +@id 360 + +@desc { + + Move to Register from Banked or Special register moves the value from the Banked ARM core register or SPSR of the specified mode, or the value of ELR_hyp, to an ARM core register. MRS (Banked register) is UNPREDICTABLE if executed in User mode. The effect of using an MRS (Banked register) instruction with a register argument that is not valid for the current mode is UNPREDICTABLE. For more information see Usage restrictions on the Banked register transfer instructions on page B9-1972. + +} + +@encoding (T1) { + + @word 1 1 1 1 0 0 1 1 1 1 1 R(1) m1(4) 1 0 0 0 Rd(4) 0 0 1 m(1) 0 0 0 0 + + @syntax { + + @subid 2010 + + @conv { + + reg_D = Register(Rd) + banked_reg = BankedRegister(R, m:m1) + + } + + @asm mrs reg_D banked_reg + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 R(1) 0 0 m1(4) Rd(4) 0 0 1 m(1) 0 0 0 0 0 0 0 0 + + @syntax { + + @subid 2011 + + @conv { + + reg_D = Register(Rd) + banked_reg = BankedRegister(R, m:m1) + + } + + @asm mrs reg_D banked_reg + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am index 331ac98..68e6c6f 100644 --- a/plugins/arm/v7/opdefs/Makefile.am +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -22,7 +22,7 @@ D2C_ENCODINGS = \ D2C_ID_PREFIX = AOP7 D2C_ID_COUNT = 500 -D2C_SPECIFIC = +D2C_SPECIFIC = --filename-reuse=2 FIXED_C_INCLUDES = \ @@ -49,267 +49,289 @@ FIXED_H_HOOKS_INCLUDES = \ \n\#include "../../link.h" -# for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done +# for i in $(seq 1 426); do file=A88${i}_*d ; test -f $file && ls $file ; done | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/' +# for i in $(seq 1 22); do file=B93${i}_*d ; test -f $file && ls $file ; done | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/' + ARMV7_DEFS = \ - adc_A881.d \ - adc_A882.d \ - adc_A883.d \ - add_A884.d \ - add_A885.d \ - add_A886.d \ - add_A887.d \ - add_A888.d \ - add_A889.d \ - add_A8810.d \ - add_A8811.d \ - adr_A8812.d \ - and_A8813.d \ - and_A8814.d \ - and_A8815.d \ - asr_A8816.d \ - asr_A8817.d \ - b_A8818.d \ - bfc_A8819.d \ - bfi_A8820.d \ - bic_A8821.d \ - bic_A8822.d \ - bic_A8823.d \ - bkpt_A8824.d \ - bl_A8825.d \ - blx_A8826.d \ - bx_A8827.d \ - bxj_A8828.d \ - cb_A8829.d \ - cdp_A8830.d \ - clrex_A8832.d \ - clz_A8833.d \ - cmn_A8834.d \ - cmn_A8835.d \ - cmn_A8836.d \ - cmp_A8837.d \ - cmp_A8838.d \ - cmp_A8839.d \ - dbg_A8842.d \ - dmb_A8843.d \ - dsb_A8844.d \ - eor_A8846.d \ - eor_A8847.d \ - eor_A8848.d \ - it_A8854.d \ - ldc_A8855.d \ - ldc_A8856.d \ - ldm_A8857.d \ - ldm_A8858.d \ - ldmda_A8859.d \ - ldmdb_A8860.d \ - ldmib_A8861.d \ - ldr_A8862.d \ - ldr_A8863.d \ - ldr_A8864.d \ - ldr_A8865.d \ - ldr_A8866.d \ - ldrb_A8867.d \ - ldrb_A8868.d \ - ldrb_A8869.d \ - ldrb_A8870.d \ - ldrbt_A8871.d \ - ldrd_A8872.d \ - ldrd_A8873.d \ - ldrd_A8874.d \ - ldrex_A8875.d \ - ldrexb_A8876.d \ - ldrexd_A8877.d \ - ldrexh_A8878.d \ - ldrh_A8879.d \ - ldrh_A8880.d \ - ldrh_A8881.d \ - ldrh_A8882.d \ - ldrht_A8883.d \ - ldrsb_A8884.d \ - ldrsb_A8885.d \ - ldrsb_A8886.d \ - ldrsbt_A8887.d \ - ldrsh_A8888.d \ - ldrsh_A8889.d \ - ldrsh_A8890.d \ - ldrsht_A8891.d \ - ldrt_A8892.d \ - lsl_A8894.d \ - lsl_A8895.d \ - lsr_A8896.d \ - lsr_A8897.d \ - mcr_A8898.d \ - mcrr_A8899.d \ - mla_A88100.d \ - mls_A88101.d \ - mov_A88102.d \ - mov_A88103.d \ - mov_A88104.d \ - movt_A88106.d \ - mrc_A88107.d \ - mrrc_A88108.d \ - mrs_A88109.d \ - msr_A88111.d \ - msr_A88112.d \ - mul_A88114.d \ - mvn_A88115.d \ - mvn_A88116.d \ - mvn_A88117.d \ - nop_A88119.d \ - orn_A88120.d \ - orn_A88121.d \ - orr_A88122.d \ - orr_A88123.d \ - orr_A88124.d \ - pkh_A88125.d \ - pld_A88126.d \ - pld_A88127.d \ - pld_A88128.d \ - pli_A88130.d \ - pop_A88131.d \ - pop_A88132.d \ - push_A88133.d \ - qadd_A88134.d \ - qadd16_A88135.d \ - qadd8_A88136.d \ - qasx_A88137.d \ - qdadd_A88138.d \ - qdsub_A88139.d \ - qsax_A88140.d \ - qsub_A88141.d \ - qsub16_A88142.d \ - qsub8_A88143.d \ - rbit_A88144.d \ - rev_A88145.d \ - rev16_A88146.d \ - revsh_A88147.d \ - ror_A88149.d \ - ror_A88150.d \ - rrx_A88151.d \ - rsb_A88152.d \ - rsb_A88153.d \ - rsb_A88154.d \ - rsc_A88155.d \ - rsc_A88156.d \ - rsc_A88157.d \ - sadd16_A88158.d \ - sadd8_A88159.d \ - sasx_A88160.d \ - sbc_A88161.d \ - sbc_A88162.d \ - sbc_A88163.d \ - sbfx_A88164.d \ - sdiv_A88165.d \ - sel_A88166.d \ - setend_A88167.d \ - sev_A88168.d \ - shadd16_A88169.d \ - shadd8_A88170.d \ - shasx_A88171.d \ - shsax_A88172.d \ - shsub16_A88173.d \ - shsub8_A88174.d \ - smla_A88176.d \ - smlad_A88177.d \ - smlal_A88178.d \ - smlal_A88179.d \ - smlald_A88180.d \ - smlaw_A88181.d \ - smlsd_A88182.d \ - smlsld_A88183.d \ - smmla_A88184.d \ - smmls_A88185.d \ - smmul_A88186.d \ - smuad_A88187.d \ - smul_A88188.d \ - smull_A88189.d \ - smulw_A88190.d \ - smusd_A88191.d \ - ssat_A88193.d \ - ssat16_A88194.d \ - ssax_A88195.d \ - ssub16_A88196.d \ - ssub8_A88197.d \ - stc_A88198.d \ - stm_A88199.d \ - stmda_A88200.d \ - stmdb_A88201.d \ - stmib_A88202.d \ - str_A88203.d \ - str_A88204.d \ - str_A88205.d \ - strb_A88206.d \ - strb_A88207.d \ - strb_A88208.d \ - strbt_A88209.d \ - strd_A88210.d \ - strd_A88211.d \ - strex_A88212.d \ - strexb_A88213.d \ - strexd_A88214.d \ - strexh_A88215.d \ - strh_A88216.d \ - strh_A88217.d \ - strh_A88218.d \ - strht_A88219.d \ - strt_A88220.d \ - sub_A88221.d \ - sub_A88222.d \ - sub_A88223.d \ - sub_A88224.d \ - sub_A88225.d \ - sub_A88226.d \ - svc_A88228.d \ - swp_A88229.d \ - sxtab_A88230.d \ - sxtab16_A88231.d \ - sxtah_A88232.d \ - sxtb_A88233.d \ - sxtb16_A88234.d \ - sxth_A88235.d \ - teq_A88237.d \ - teq_A88238.d \ - teq_A88239.d \ - tst_A88240.d \ - tst_A88241.d \ - tst_A88242.d \ - uadd16_A88243.d \ - uadd8_A88244.d \ - uasx_A88245.d \ - ubfx_A88246.d \ - udf_A88247.d \ - udiv_A88248.d \ - uhadd16_A88249.d \ - uhadd8_A88250.d \ - uhasx_A88251.d \ - uhsax_A88252.d \ - uhsub16_A88253.d \ - uhsub8_A88254.d \ - umaal_A88255.d \ - umlal_A88256.d \ - umull_A88257.d \ - uqadd16_A88258.d \ - uqadd8_A88259.d \ - uqasx_A88260.d \ - uqsax_A88261.d \ - uqsub16_A88262.d \ - uqsub8_A88263.d \ - usad8_A88264.d \ - usada8_A88265.d \ - usat_A88266.d \ - usat16_A88267.d \ - usax_A88268.d \ - usub16_A88269.d \ - usub8_A88270.d \ - uxtab_A88271.d \ - uxtab16_A88272.d \ - uxtah_A88273.d \ - uxtb_A88274.d \ - uxtb16_A88275.d \ - uxth_A88276.d \ - wfe_A88424.d \ - wfi_A88425.d \ - yield_A88426.d + A881_adc.d \ + A882_adc.d \ + A883_adc.d \ + A884_add.d \ + A885_add.d \ + A886_add.d \ + A887_add.d \ + A888_add.d \ + A889_add.d \ + A8810_add.d \ + A8811_add.d \ + A8812_adr.d \ + A8813_and.d \ + A8814_and.d \ + A8815_and.d \ + A8816_asr.d \ + A8817_asr.d \ + A8818_b.d \ + A8819_bfc.d \ + A8820_bfi.d \ + A8821_bic.d \ + A8822_bic.d \ + A8823_bic.d \ + A8824_bkpt.d \ + A8825_bl.d \ + A8826_blx.d \ + A8827_bx.d \ + A8828_bxj.d \ + A8829_cb.d \ + A8830_cdp.d \ + A8832_clrex.d \ + A8833_clz.d \ + A8834_cmn.d \ + A8835_cmn.d \ + A8836_cmn.d \ + A8837_cmp.d \ + A8838_cmp.d \ + A8839_cmp.d \ + A8842_dbg.d \ + A8843_dmb.d \ + A8844_dsb.d \ + A8846_eor.d \ + A8847_eor.d \ + A8848_eor.d \ + A8854_it.d \ + A8855_ldc.d \ + A8856_ldc.d \ + A8857_ldm.d \ + A8858_ldm.d \ + A8859_ldmda.d \ + A8860_ldmdb.d \ + A8861_ldmib.d \ + A8862_ldr.d \ + A8863_ldr.d \ + A8864_ldr.d \ + A8865_ldr.d \ + A8866_ldr.d \ + A8867_ldrb.d \ + A8868_ldrb.d \ + A8869_ldrb.d \ + A8870_ldrb.d \ + A8871_ldrbt.d \ + A8872_ldrd.d \ + A8873_ldrd.d \ + A8874_ldrd.d \ + A8875_ldrex.d \ + A8876_ldrexb.d \ + A8877_ldrexd.d \ + A8878_ldrexh.d \ + A8879_ldrh.d \ + A8880_ldrh.d \ + A8881_ldrh.d \ + A8882_ldrh.d \ + A8883_ldrht.d \ + A8884_ldrsb.d \ + A8885_ldrsb.d \ + A8886_ldrsb.d \ + A8887_ldrsbt.d \ + A8888_ldrsh.d \ + A8889_ldrsh.d \ + A8890_ldrsh.d \ + A8891_ldrsht.d \ + A8892_ldrt.d \ + A8894_lsl.d \ + A8895_lsl.d \ + A8896_lsr.d \ + A8897_lsr.d \ + A8898_mcr.d \ + A8899_mcrr.d \ + A88100_mla.d \ + A88101_mls.d \ + A88102_mov.d \ + A88103_mov.d \ + A88104_mov.d \ + A88106_movt.d \ + A88107_mrc.d \ + A88108_mrrc.d \ + A88109_mrs.d \ + A88111_msr.d \ + A88112_msr.d \ + A88114_mul.d \ + A88115_mvn.d \ + A88116_mvn.d \ + A88117_mvn.d \ + A88119_nop.d \ + A88120_orn.d \ + A88121_orn.d \ + A88122_orr.d \ + A88123_orr.d \ + A88124_orr.d \ + A88125_pkh.d \ + A88126_pld.d \ + A88127_pld.d \ + A88128_pld.d \ + A88130_pli.d \ + A88131_pop.d \ + A88132_pop.d \ + A88133_push.d \ + A88134_qadd.d \ + A88135_qadd16.d \ + A88136_qadd8.d \ + A88137_qasx.d \ + A88138_qdadd.d \ + A88139_qdsub.d \ + A88140_qsax.d \ + A88141_qsub.d \ + A88142_qsub16.d \ + A88143_qsub8.d \ + A88144_rbit.d \ + A88145_rev.d \ + A88146_rev16.d \ + A88147_revsh.d \ + A88149_ror.d \ + A88150_ror.d \ + A88151_rrx.d \ + A88152_rsb.d \ + A88153_rsb.d \ + A88154_rsb.d \ + A88155_rsc.d \ + A88156_rsc.d \ + A88157_rsc.d \ + A88158_sadd16.d \ + A88159_sadd8.d \ + A88160_sasx.d \ + A88161_sbc.d \ + A88162_sbc.d \ + A88163_sbc.d \ + A88164_sbfx.d \ + A88165_sdiv.d \ + A88166_sel.d \ + A88167_setend.d \ + A88168_sev.d \ + A88169_shadd16.d \ + A88170_shadd8.d \ + A88171_shasx.d \ + A88172_shsax.d \ + A88173_shsub16.d \ + A88174_shsub8.d \ + A88176_smla.d \ + A88177_smlad.d \ + A88178_smlal.d \ + A88179_smlal.d \ + A88180_smlald.d \ + A88181_smlaw.d \ + A88182_smlsd.d \ + A88183_smlsld.d \ + A88184_smmla.d \ + A88185_smmls.d \ + A88186_smmul.d \ + A88187_smuad.d \ + A88188_smul.d \ + A88189_smull.d \ + A88190_smulw.d \ + A88191_smusd.d \ + A88193_ssat.d \ + A88194_ssat16.d \ + A88195_ssax.d \ + A88196_ssub16.d \ + A88197_ssub8.d \ + A88198_stc.d \ + A88199_stm.d \ + A88200_stmda.d \ + A88201_stmdb.d \ + A88202_stmib.d \ + A88203_str.d \ + A88204_str.d \ + A88205_str.d \ + A88206_strb.d \ + A88207_strb.d \ + A88208_strb.d \ + A88209_strbt.d \ + A88210_strd.d \ + A88211_strd.d \ + A88212_strex.d \ + A88213_strexb.d \ + A88214_strexd.d \ + A88215_strexh.d \ + A88216_strh.d \ + A88217_strh.d \ + A88218_strh.d \ + A88219_strht.d \ + A88220_strt.d \ + A88221_sub.d \ + A88222_sub.d \ + A88223_sub.d \ + A88224_sub.d \ + A88225_sub.d \ + A88226_sub.d \ + A88228_svc.d \ + A88229_swp.d \ + A88230_sxtab.d \ + A88231_sxtab16.d \ + A88232_sxtah.d \ + A88233_sxtb.d \ + A88234_sxtb16.d \ + A88235_sxth.d \ + A88237_teq.d \ + A88238_teq.d \ + A88239_teq.d \ + A88240_tst.d \ + A88241_tst.d \ + A88242_tst.d \ + A88243_uadd16.d \ + A88244_uadd8.d \ + A88245_uasx.d \ + A88246_ubfx.d \ + A88247_udf.d \ + A88248_udiv.d \ + A88249_uhadd16.d \ + A88250_uhadd8.d \ + A88251_uhasx.d \ + A88252_uhsax.d \ + A88253_uhsub16.d \ + A88254_uhsub8.d \ + A88255_umaal.d \ + A88256_umlal.d \ + A88257_umull.d \ + A88258_uqadd16.d \ + A88259_uqadd8.d \ + A88260_uqasx.d \ + A88261_uqsax.d \ + A88262_uqsub16.d \ + A88263_uqsub8.d \ + A88264_usad8.d \ + A88265_usada8.d \ + A88266_usat.d \ + A88267_usat16.d \ + A88268_usax.d \ + A88269_usub16.d \ + A88270_usub8.d \ + A88271_uxtab.d \ + A88272_uxtab16.d \ + A88273_uxtah.d \ + A88274_uxtb.d \ + A88275_uxtb16.d \ + A88276_uxth.d \ + A88424_wfe.d \ + A88425_wfi.d \ + A88426_yield.d \ + B931_cps.d \ + B932_cps.d \ + B933_eret.d \ + B934_hvc.d \ + B935_ldm.d \ + B936_ldm.d \ + B938_mrs.d \ + B939_mrs.d \ + B9310_msr.d \ + B9311_msr.d \ + B9312_msr.d \ + B9313_rfe.d \ + B9314_smc.d \ + B9315_srs.d \ + B9316_srs.d \ + B9317_stm.d \ + B9319_subs.d \ + B9320_subs.d \ + B9321_vmrs.d \ + B9322_vmsr.d # make dist procède répertoire par répertoire. Or le répertoire opcodes utilise diff --git a/plugins/arm/v7/opdefs/adc_A881.d b/plugins/arm/v7/opdefs/adc_A881.d deleted file mode 100644 index d470638..0000000 --- a/plugins/arm/v7/opdefs/adc_A881.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADC (immediate) - -@id 0 - -@desc { - - Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 0 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm adc ?reg_D reg_N imm32 - - } - - @syntax { - - @subid 1 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm adcs ?reg_D reg_N imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 2 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm adc ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 3 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm adcs ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/adc_A882.d b/plugins/arm/v7/opdefs/adc_A882.d deleted file mode 100644 index aaca002..0000000 --- a/plugins/arm/v7/opdefs/adc_A882.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADC (register) - -@id 1 - -@desc { - - Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) - - @syntax { - - @subid 4 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm adc ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 5 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm adc.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 6 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm adcs.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 7 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm adc ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 8 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm adcs ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/adc_A883.d b/plugins/arm/v7/opdefs/adc_A883.d deleted file mode 100644 index 0270402..0000000 --- a/plugins/arm/v7/opdefs/adc_A883.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADC (register-shifted register) - -@id 2 - -@desc { - - Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 9 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm adc ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 10 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm adcs ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A8810.d b/plugins/arm/v7/opdefs/add_A8810.d deleted file mode 100644 index 357dadc..0000000 --- a/plugins/arm/v7/opdefs/add_A8810.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (SP plus register, Thumb) - -@id 9 - -@desc { - - This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) - - @syntax { - - @subid 33 - - @conv { - - reg_D = Register(DM:Rdm) - reg_SP = Register(13) - reg_M = Register(DM:Rdm) - - } - - @asm add ?reg_D reg_SP reg_M - - } - -} - -@encoding (t2) { - - @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 - - @syntax { - - @subid 34 - - @conv { - - reg_D = Register(13) - reg_SP = Register(13) - reg_M = Register(Rm) - - } - - @asm add ?reg_D reg_SP reg_M - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 35 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm add.w ?reg_D reg_SP reg_M ?shift - - } - - @syntax { - - @subid 36 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm adds.w ?reg_D reg_SP reg_M ?shift - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/add_A8811.d deleted file mode 100644 index f5c19aa..0000000 --- a/plugins/arm/v7/opdefs/add_A8811.d +++ /dev/null @@ -1,97 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (SP plus register, ARM) - -@id 10 - -@desc { - - This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 37 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm add ?reg_D reg_SP reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 38 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm adds ?reg_D reg_SP reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A884.d b/plugins/arm/v7/opdefs/add_A884.d deleted file mode 100644 index c35685f..0000000 --- a/plugins/arm/v7/opdefs/add_A884.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (immediate, Thumb) - -@id 3 - -@desc { - - This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) - - @syntax { - - @subid 11 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) - - } - - @asm add ?reg_D reg_N imm32 - - } - -} - -@encoding (t2) { - - @half 0 0 1 1 0 Rdn(3) imm8(8) - - @syntax { - - @subid 12 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) - - } - - @asm add ?reg_D reg_N imm32 - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 13 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm add.w ?reg_D reg_N imm32 - - } - - @syntax { - - @subid 14 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm adds.w ?reg_D reg_N imm32 - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 15 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - - @asm addw ?reg_D reg_N imm32 - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A885.d b/plugins/arm/v7/opdefs/add_A885.d deleted file mode 100644 index 87b92a6..0000000 --- a/plugins/arm/v7/opdefs/add_A885.d +++ /dev/null @@ -1,95 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (immediate, ARM) - -@id 4 - -@desc { - - This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 16 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm add ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 17 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm adds ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A886.d b/plugins/arm/v7/opdefs/add_A886.d deleted file mode 100644 index 856272e..0000000 --- a/plugins/arm/v7/opdefs/add_A886.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (register, Thumb) - -@id 5 - -@desc { - - This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) - - @syntax { - - @subid 18 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm add ?reg_D reg_N reg_M - - } - -} - -@encoding (t2) { - - @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) - - @syntax { - - @subid 19 - - @conv { - - reg_D = Register(DN:Rdn) - reg_N = Register(DN:Rdn) - reg_M = Register(Rm) - - } - - @asm add ?reg_D reg_N reg_M - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 20 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm add.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 21 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm adds.w ?reg_D reg_N reg_M ?shift - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A887.d b/plugins/arm/v7/opdefs/add_A887.d deleted file mode 100644 index 6105f18..0000000 --- a/plugins/arm/v7/opdefs/add_A887.d +++ /dev/null @@ -1,97 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (register, ARM) - -@id 6 - -@desc { - - This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 22 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm add ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 23 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm adds ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A888.d b/plugins/arm/v7/opdefs/add_A888.d deleted file mode 100644 index 8fd6078..0000000 --- a/plugins/arm/v7/opdefs/add_A888.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (register-shifted register) - -@id 7 - -@desc { - - Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 24 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm add ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 25 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm adds ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/add_A889.d b/plugins/arm/v7/opdefs/add_A889.d deleted file mode 100644 index 834de50..0000000 --- a/plugins/arm/v7/opdefs/add_A889.d +++ /dev/null @@ -1,211 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADD (SP plus immediate) - -@id 8 - -@desc { - - This instruction adds an immediate value to the SP value, and writes the result to the destination register. - -} - -@encoding (t1) { - - @half 1 0 1 0 1 Rd(3) imm8(8) - - @syntax { - - @subid 26 - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm add ?reg_D reg_SP imm32 - - } - -} - -@encoding (t2) { - - @half 1 0 1 1 0 0 0 0 0 imm7(7) - - @syntax { - - @subid 27 - - @conv { - - reg_D = Register(13) - reg_SP = Register(13) - imm32 = ZeroExtend(imm7:'00', 32) - - } - - @asm add ?reg_D reg_SP imm32 - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 28 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm add.w ?reg_D reg_SP imm32 - - } - - @syntax { - - @subid 29 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm adds.w ?reg_D reg_SP imm32 - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 30 - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - - @asm addw ?reg_D reg_SP imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) - - @syntax { - - @subid 31 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ARMExpandImm(imm12) - - } - - @asm add ?reg_D reg_SP imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 32 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ARMExpandImm(imm12) - - } - - @asm adds ?reg_D reg_SP imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/adr_A8812.d b/plugins/arm/v7/opdefs/adr_A8812.d deleted file mode 100644 index 1f77eea..0000000 --- a/plugins/arm/v7/opdefs/adr_A8812.d +++ /dev/null @@ -1,150 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ADR - -@id 11 - -@desc { - - This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. - -} - -@encoding (t1) { - - @half 1 0 1 0 0 Rd(3) imm8(8) - - @syntax { - - @subid 39 - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm adr reg_D imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 40 - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - - @asm adr.w reg_D imm32 - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 41 - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - - @asm adr.w reg_D imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - - @syntax { - - @subid 42 - - @conv { - - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) - - } - - @asm adr reg_D imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) - - @syntax { - - @subid 43 - - @conv { - - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) - - } - - @asm adr reg_D imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/and_A8813.d b/plugins/arm/v7/opdefs/and_A8813.d deleted file mode 100644 index 988bdd7..0000000 --- a/plugins/arm/v7/opdefs/and_A8813.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title AND (immediate) - -@id 12 - -@desc { - - This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 44 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm and ?reg_D reg_N const - - } - - @syntax { - - @subid 45 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm ands ?reg_D reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 46 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm and ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 47 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm ands ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/and_A8814.d b/plugins/arm/v7/opdefs/and_A8814.d deleted file mode 100644 index 1a807f9..0000000 --- a/plugins/arm/v7/opdefs/and_A8814.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title AND (register) - -@id 13 - -@desc { - - This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) - - @syntax { - - @subid 48 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm and ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 49 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm and.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 50 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm ands.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 51 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm and ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 52 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm ands ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/and_A8815.d b/plugins/arm/v7/opdefs/and_A8815.d deleted file mode 100644 index 3d890cb..0000000 --- a/plugins/arm/v7/opdefs/and_A8815.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title AND (register-shifted register) - -@id 14 - -@desc { - - This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 53 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm and ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 54 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm ands ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/asr_A8816.d b/plugins/arm/v7/opdefs/asr_A8816.d deleted file mode 100644 index 401c4c5..0000000 --- a/plugins/arm/v7/opdefs/asr_A8816.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ASR (immediate) - -@id 15 - -@desc { - - Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) - - @syntax { - - @subid 55 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('10', imm5) - - } - - @asm asr ?reg_D reg_M shift_n - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) - - @syntax { - - @subid 56 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('10', imm3:imm2) - - } - - @asm asr.w ?reg_D reg_M shift_n - - } - - @syntax { - - @subid 57 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('10', imm3:imm2) - - } - - @asm asrs.w ?reg_D reg_M shift_n - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) - - @syntax { - - @subid 58 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('10', imm5) - - } - - @asm asr ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 59 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('10', imm5) - - } - - @asm asrs ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/asr_A8817.d b/plugins/arm/v7/opdefs/asr_A8817.d deleted file mode 100644 index 0ddeae9..0000000 --- a/plugins/arm/v7/opdefs/asr_A8817.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ASR (register) - -@id 16 - -@desc { - - Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) - - @syntax { - - @subid 60 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm asr ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 61 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm asr.w ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 62 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm asrs.w ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) - - @syntax { - - @subid 63 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm asr ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 64 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm asrs ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/b_A8818.d b/plugins/arm/v7/opdefs/b_A8818.d deleted file mode 100644 index d10b297..0000000 --- a/plugins/arm/v7/opdefs/b_A8818.d +++ /dev/null @@ -1,192 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title B - -@id 17 - -@desc { - - Branch causes a branch to a target address. - -} - -@encoding (t1) { - - @half 1 1 0 1 cond(4) imm8(8) - - @syntax { - - @subid 65 - - @conv { - - imm32 = SignExtend(imm8:'0', 32, 8) - - } - - @asm b imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (t2) { - - @half 1 1 1 0 0 imm11(11) - - @syntax { - - @subid 66 - - @conv { - - imm32 = SignExtend(imm11:'0', 32, 11) - - } - - @asm b imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) - - @syntax { - - @subid 67 - - @conv { - - imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32, 20) - - } - - @asm b imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - check g_armv7_instruction_extend_keyword(".W") - - } - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) - - @syntax { - - @subid 68 - - @conv { - - imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) - - } - - @asm b.w imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_thumb - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 1 0 imm24(24) - - @syntax { - - @subid 69 - - @conv { - - imm32 = SignExtend(imm24:'00', 32, 25) - - } - - @asm b imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - fetch = help_fetching_with_instruction_b_from_arm - link = handle_arm_conditional_branch_as_link - post = post_process_branch_instructions - - } - -} - diff --git a/plugins/arm/v7/opdefs/bfc_A8819.d b/plugins/arm/v7/opdefs/bfc_A8819.d deleted file mode 100644 index f8875e5..0000000 --- a/plugins/arm/v7/opdefs/bfc_A8819.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BFC - -@id 18 - -@desc { - - Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - - @syntax { - - @subid 70 - - @conv { - - reg_D = Register(Rd) - lsbit = UInt(imm3:imm2) - msbit = UInt(msb) - width = BitDiff(msbit, lsbit) - - } - - @asm bfc reg_D lsbit width - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 1 1 1 1 - - @syntax { - - @subid 71 - - @conv { - - reg_D = Register(Rd) - lsbit = UInt(lsb) - msbit = UInt(msb) - width = BitDiff(msbit, lsbit) - - } - - @asm bfc reg_D lsbit width - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/bfi_A8820.d b/plugins/arm/v7/opdefs/bfi_A8820.d deleted file mode 100644 index aa71aa8..0000000 --- a/plugins/arm/v7/opdefs/bfi_A8820.d +++ /dev/null @@ -1,87 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BFI - -@id 19 - -@desc { - - Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 1 1 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - - @syntax { - - @subid 72 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - msbit = UInt(msb) - width = BitDiff(msbit, lsbit) - - } - - @asm bfi reg_D reg_N lsbit width - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 Rn(4) - - @syntax { - - @subid 73 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - msbit = UInt(msb) - width = BitDiff(msbit, lsbit) - - } - - @asm bfi reg_D reg_N lsbit width - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/bic_A8821.d b/plugins/arm/v7/opdefs/bic_A8821.d deleted file mode 100644 index 59d4bb0..0000000 --- a/plugins/arm/v7/opdefs/bic_A8821.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BIC (immediate) - -@id 20 - -@desc { - - Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 74 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm bic ?reg_D reg_N const - - } - - @syntax { - - @subid 75 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm bics ?reg_D reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 76 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm bic ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 77 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm bics ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/bic_A8822.d b/plugins/arm/v7/opdefs/bic_A8822.d deleted file mode 100644 index f4746b9..0000000 --- a/plugins/arm/v7/opdefs/bic_A8822.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BIC (register) - -@id 21 - -@desc { - - Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3) - - @syntax { - - @subid 78 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm bic ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 79 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm bic.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 80 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm bics.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 81 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm bic ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 82 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm bics ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/bic_A8823.d b/plugins/arm/v7/opdefs/bic_A8823.d deleted file mode 100644 index fb57338..0000000 --- a/plugins/arm/v7/opdefs/bic_A8823.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BIC (register-shifted register) - -@id 22 - -@desc { - - Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 83 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm bic ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 84 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm bics ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/bkpt_A8824.d b/plugins/arm/v7/opdefs/bkpt_A8824.d deleted file mode 100644 index e9c9f4b..0000000 --- a/plugins/arm/v7/opdefs/bkpt_A8824.d +++ /dev/null @@ -1,73 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BKPT - -@id 23 - -@desc { - - Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 0 imm8(8) - - @syntax { - - @subid 85 - - @conv { - - imm32 = ZeroExtend(imm8, 32) - - } - - @asm bkpt imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 imm12(12) 0 1 1 1 imm4(4) - - @syntax { - - @subid 86 - - @conv { - - imm32 = ZeroExtend(imm12:imm4, 32) - - } - - @asm bkpt imm32 - - } - -} - diff --git a/plugins/arm/v7/opdefs/bl_A8825.d b/plugins/arm/v7/opdefs/bl_A8825.d deleted file mode 100644 index 221bbc5..0000000 --- a/plugins/arm/v7/opdefs/bl_A8825.d +++ /dev/null @@ -1,151 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BL, BLX (immediate) - -@id 24 - -@desc { - - Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) - - @syntax { - - @subid 87 - - @conv { - - imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) - - } - - @asm bl imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_bl_from_thumb - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) - - @syntax { - - @subid 88 - - @conv { - - imm32 = SignExtend(S:J1:J2:imm10H:imm10L:'00', 32, 24) - - } - - @asm blx imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_blx_from_thumb - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 1 1 imm24(24) - - @syntax { - - @subid 89 - - @conv { - - imm32 = SignExtend(imm24:'00', 32, 25) - - } - - @asm bl imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - fetch = help_fetching_with_instruction_bl_from_arm - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 0 1 H(1) imm24(24) - - @syntax { - - @subid 90 - - @conv { - - imm32 = SignExtend(imm24:H:'0', 32, 25) - - } - - @asm blx imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_blx_from_arm - link = handle_call_as_link - post = post_process_branch_and_link_instructions - - } - -} - diff --git a/plugins/arm/v7/opdefs/blx_A8826.d b/plugins/arm/v7/opdefs/blx_A8826.d deleted file mode 100644 index 2c975d3..0000000 --- a/plugins/arm/v7/opdefs/blx_A8826.d +++ /dev/null @@ -1,79 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BLX (register) - -@id 25 - -@desc { - - Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 1 1 1 1 Rm(4) 0 0 0 - - @syntax { - - @subid 91 - - @conv { - - reg_M = Register(Rm) - - } - - @asm blx reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 92 - - @conv { - - reg_M = Register(Rm) - - } - - @asm blx reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/bx_A8827.d b/plugins/arm/v7/opdefs/bx_A8827.d deleted file mode 100644 index 64ad628..0000000 --- a/plugins/arm/v7/opdefs/bx_A8827.d +++ /dev/null @@ -1,91 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BX - -@id 26 - -@desc { - - Branch and Exchange causes a branch to an address and instruction set specified by a register. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0 - - @syntax { - - @subid 93 - - @conv { - - reg_M = Register(Rm) - - } - - @asm bx reg_M - - } - - @hooks { - - fetch = help_fetching_with_instruction_bx_from_thumb - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 94 - - @conv { - - reg_M = Register(Rm) - - } - - @asm bx reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - fetch = help_fetching_with_instruction_bx_from_thumb - - } - -} - diff --git a/plugins/arm/v7/opdefs/bxj_A8828.d b/plugins/arm/v7/opdefs/bxj_A8828.d deleted file mode 100644 index 7c6ddb5..0000000 --- a/plugins/arm/v7/opdefs/bxj_A8828.d +++ /dev/null @@ -1,79 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title BXJ - -@id 27 - -@desc { - - Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 95 - - @conv { - - reg_M = Register(Rm) - - } - - @asm bxj reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) - - @syntax { - - @subid 96 - - @conv { - - reg_M = Register(Rm) - - } - - @asm bxj reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cb_A8829.d b/plugins/arm/v7/opdefs/cb_A8829.d deleted file mode 100644 index 5e004b7..0000000 --- a/plugins/arm/v7/opdefs/cb_A8829.d +++ /dev/null @@ -1,89 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CBNZ, CBZ - -@id 28 - -@desc { - - Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. - -} - -@encoding (t1) { - - @half 1 0 1 1 op(1) 0 i(1) 1 imm5(5) Rn(3) - - @syntax { - - @subid 97 - - @assert { - - op == 0 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm5:'0', 32) - - } - - @asm cbz reg_N imm32 - - } - - @syntax { - - @subid 98 - - @assert { - - op == 1 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm5:'0', 32) - - } - - @asm cbnz reg_N imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_cb_n_z - link = handle_comp_and_branch_if_true_as_link - post = post_process_comp_and_branch_instructions - - } - -} - diff --git a/plugins/arm/v7/opdefs/cdp_A8830.d b/plugins/arm/v7/opdefs/cdp_A8830.d deleted file mode 100644 index 32fc2f1..0000000 --- a/plugins/arm/v7/opdefs/cdp_A8830.d +++ /dev/null @@ -1,133 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CDP, CDP2 - -@id 29 - -@desc { - - Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax { - - @subid 99 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - direct_CRd = UInt(CRd) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax { - - @subid 100 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - direct_CRd = UInt(CRd) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax { - - @subid 101 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - direct_CRd = UInt(CRd) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax { - - @subid 102 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - direct_CRd = UInt(CRd) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 - - } - -} - diff --git a/plugins/arm/v7/opdefs/clrex_A8832.d b/plugins/arm/v7/opdefs/clrex_A8832.d deleted file mode 100644 index 5edfb58..0000000 --- a/plugins/arm/v7/opdefs/clrex_A8832.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CLREX - -@id 31 - -@desc { - - Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 - - @syntax { - - @subid 103 - - @asm clrex - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 - - @syntax { - - @subid 104 - - @asm clrex - - } - -} - diff --git a/plugins/arm/v7/opdefs/clz_A8833.d b/plugins/arm/v7/opdefs/clz_A8833.d deleted file mode 100644 index 7cbb51c..0000000 --- a/plugins/arm/v7/opdefs/clz_A8833.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CLZ - -@id 32 - -@desc { - - Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax { - - @subid 105 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm clz reg_D reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 0 1 1 1 1 Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 106 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm clz reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cmn_A8834.d b/plugins/arm/v7/opdefs/cmn_A8834.d deleted file mode 100644 index 45462c7..0000000 --- a/plugins/arm/v7/opdefs/cmn_A8834.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CMN (immediate) - -@id 33 - -@desc { - - Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax { - - @subid 107 - - @conv { - - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm cmn reg_N imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax { - - @subid 108 - - @conv { - - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm cmn reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cmn_A8835.d b/plugins/arm/v7/opdefs/cmn_A8835.d deleted file mode 100644 index 55c281c..0000000 --- a/plugins/arm/v7/opdefs/cmn_A8835.d +++ /dev/null @@ -1,104 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CMN (register) - -@id 34 - -@desc { - - Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) - - @syntax { - - @subid 109 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm cmn reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax { - - @subid 110 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm cmn.w reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 111 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm cmn reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cmn_A8836.d b/plugins/arm/v7/opdefs/cmn_A8836.d deleted file mode 100644 index e1052a8..0000000 --- a/plugins/arm/v7/opdefs/cmn_A8836.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CMN (register-shifted register) - -@id 35 - -@desc { - - Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 112 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm cmn reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cmp_A8837.d b/plugins/arm/v7/opdefs/cmp_A8837.d deleted file mode 100644 index 261467b..0000000 --- a/plugins/arm/v7/opdefs/cmp_A8837.d +++ /dev/null @@ -1,102 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CMP (immediate) - -@id 36 - -@desc { - - Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (t1) { - - @half 0 0 1 0 1 Rn(3) imm8(8) - - @syntax { - - @subid 113 - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - - } - - @asm cmp reg_N imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax { - - @subid 114 - - @conv { - - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm cmp.w reg_N imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 1 0 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax { - - @subid 115 - - @conv { - - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm cmp reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cmp_A8838.d b/plugins/arm/v7/opdefs/cmp_A8838.d deleted file mode 100644 index 401e4ac..0000000 --- a/plugins/arm/v7/opdefs/cmp_A8838.d +++ /dev/null @@ -1,125 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CMP (register) - -@id 37 - -@desc { - - Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3) - - @syntax { - - @subid 116 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm cmp reg_N reg_M - - } - -} - -@encoding (t2) { - - @half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3) - - @syntax { - - @subid 117 - - @conv { - - reg_N = Register(N:Rn) - reg_M = Register(Rm) - - } - - @asm cmp reg_N reg_M - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax { - - @subid 118 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm cmp.w reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 119 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm cmp reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/cmp_A8839.d b/plugins/arm/v7/opdefs/cmp_A8839.d deleted file mode 100644 index 6bdafb3..0000000 --- a/plugins/arm/v7/opdefs/cmp_A8839.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title CMP (register-shifted register) - -@id 38 - -@desc { - - Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 120 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm cmp reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/dbg_A8842.d b/plugins/arm/v7/opdefs/dbg_A8842.d deleted file mode 100644 index d053ca3..0000000 --- a/plugins/arm/v7/opdefs/dbg_A8842.d +++ /dev/null @@ -1,79 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title DBG - -@id 41 - -@desc { - - Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 option(4) - - @syntax { - - @subid 121 - - @conv { - - direct_option = UInt(option) - - } - - @asm dbg direct_option - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 option(4) - - @syntax { - - @subid 122 - - @conv { - - direct_option = UInt(option) - - } - - @asm dbg direct_option - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/dmb_A8843.d b/plugins/arm/v7/opdefs/dmb_A8843.d deleted file mode 100644 index b8d9717..0000000 --- a/plugins/arm/v7/opdefs/dmb_A8843.d +++ /dev/null @@ -1,73 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title DMB - -@id 42 - -@desc { - - Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 option(4) - - @syntax { - - @subid 123 - - @conv { - - direct_option = UInt(option) - - } - - @asm dmb ?direct_option - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 option(4) - - @syntax { - - @subid 124 - - @conv { - - direct_option = UInt(option) - - } - - @asm dmb ?direct_option - - } - -} - diff --git a/plugins/arm/v7/opdefs/dsb_A8844.d b/plugins/arm/v7/opdefs/dsb_A8844.d deleted file mode 100644 index e8ede64..0000000 --- a/plugins/arm/v7/opdefs/dsb_A8844.d +++ /dev/null @@ -1,73 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title DSB - -@id 43 - -@desc { - - Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 option(4) - - @syntax { - - @subid 125 - - @conv { - - direct_option = UInt(option) - - } - - @asm dsb ?direct_option - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 option(4) - - @syntax { - - @subid 126 - - @conv { - - direct_option = UInt(option) - - } - - @asm dsb ?direct_option - - } - -} - diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/eor_A8846.d deleted file mode 100644 index dfafa9b..0000000 --- a/plugins/arm/v7/opdefs/eor_A8846.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title EOR (immediate) - -@id 45 - -@desc { - - Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 127 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm eor ?reg_D reg_N const - - } - - @syntax { - - @subid 128 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm eors ?reg_D reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 129 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm eor ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 130 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm eors ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/eor_A8847.d b/plugins/arm/v7/opdefs/eor_A8847.d deleted file mode 100644 index f6e3387..0000000 --- a/plugins/arm/v7/opdefs/eor_A8847.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title EOR (register) - -@id 46 - -@desc { - - Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) - - @syntax { - - @subid 131 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm eor ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 132 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm eor.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 133 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm eors.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 134 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm eor ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 135 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm eors ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/eor_A8848.d b/plugins/arm/v7/opdefs/eor_A8848.d deleted file mode 100644 index 94f0e92..0000000 --- a/plugins/arm/v7/opdefs/eor_A8848.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title EOR (register-shifted register) - -@id 47 - -@desc { - - Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 136 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm eor ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 137 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm eors ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/it_A8854.d b/plugins/arm/v7/opdefs/it_A8854.d deleted file mode 100644 index 42ee4c9..0000000 --- a/plugins/arm/v7/opdefs/it_A8854.d +++ /dev/null @@ -1,59 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title IT - -@id 53 - -@desc { - - If-Then makes up to four following instructions (the IT block) conditional. The conditions for the instructions in the IT block are the same as, or the inverse of, the condition the IT instruction specifies for the first instruction in the block. The IT instruction itself does not affect the condition flags, but the execution of the instructions in the IT block can change the condition flags. 16-bit instructions in the IT block, other than CMP, CMN and TST, do not set the condition flags. An IT instruction with the AL condition can be used to get this changed behavior without conditional execution. The architecture permits exception return to an instruction in the IT block only if the restoration of the CPSR restores ITSTATE to a state consistent with the conditions specified by the IT instruction. Any other exception return to an instruction in an IT block is UNPREDICTABLE. Any branch to a target instruction in an IT block is not permitted, and if such a branch is made it is UNPREDICTABLE what condition is used when executing that target instruction and any subsequent instruction in the IT block. See also Conditional instructions on page A4-162 and Conditional execution on page A8-288. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 firstcond(4) mask(4) - - @syntax { - - @subid 138 - - @conv { - - it_cond = ITCond(firstcond, mask) - - } - - @asm it it_cond - - } - - @hooks { - - fetch = build_it_instruction_suffix - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldc_A8855.d b/plugins/arm/v7/opdefs/ldc_A8855.d deleted file mode 100644 index 96cf4a5..0000000 --- a/plugins/arm/v7/opdefs/ldc_A8855.d +++ /dev/null @@ -1,461 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDC, LDC2 (immediate) - -@id 54 - -@desc { - - Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 139 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 140 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 141 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 142 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd maccess option - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 143 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 144 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 145 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 146 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd maccess option - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 147 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 148 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 149 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 150 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd maccess option - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 151 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 152 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 153 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldc cp direct_CRd maccess - - } - - @syntax { - - @subid 154 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd maccess option - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldc_A8856.d b/plugins/arm/v7/opdefs/ldc_A8856.d deleted file mode 100644 index 4731ff0..0000000 --- a/plugins/arm/v7/opdefs/ldc_A8856.d +++ /dev/null @@ -1,201 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDC, LDC2 (literal) - -@id 55 - -@desc { - - Load Coprocessor loads memory data from a sequence of consecutive memory addresses to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid LDC and LDC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted LDC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an LDC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the LDC pseudocode does not show this possible trap to Hyp mode. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 155 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 156 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd imm32 - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 157 - - @assert { - - P == 0 - U == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_PC = Register(15) - maccess = MemAccessOffset(reg_PC, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd maccess option - - } - - @syntax { - - @subid 158 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd imm32 - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 1 1 1 1 1 CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 159 - - @assert { - - P == 0 - U == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_PC = Register(15) - maccess = MemAccessOffset(reg_PC, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd maccess option - - } - - @syntax { - - @subid 160 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm ldc cp direct_CRd imm32 - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldm_A8857.d b/plugins/arm/v7/opdefs/ldm_A8857.d deleted file mode 100644 index e7733e0..0000000 --- a/plugins/arm/v7/opdefs/ldm_A8857.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDM/LDMIA/LDMFD (Thumb) - -@id 56 - -@desc { - - Load Multiple Increment After (Load Multiple Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. - -} - -@encoding (t1) { - - @half 1 1 0 0 1 Rn(3) register_list(8) - - @syntax { - - @subid 161 - - @conv { - - reg_N = Register(Rn) - wb_reg = UncheckedWrittenBackReg(reg_N) - registers = RegList('00000000':register_list) - - } - - @asm ldm wb_reg registers - - } - - @hooks { - - fetch = apply_write_back_from_registers - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 0 0 1 0 W(1) 1 Rn(4) P(1) M(1) 0 register_list(13) - - @syntax { - - @subid 162 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(P:M:'0':register_list) - - } - - @asm ldm.w wb_reg registers - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldm_A8858.d b/plugins/arm/v7/opdefs/ldm_A8858.d deleted file mode 100644 index 8b41183..0000000 --- a/plugins/arm/v7/opdefs/ldm_A8858.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDM/LDMIA/LDMFD (ARM) - -@id 57 - -@desc { - - Load Multiple Increment After (Load Multiple Full Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the highest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 0 1 0 W(1) 1 Rn(4) register_list(16) - - @syntax { - - @subid 163 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm ldm wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldmda_A8859.d b/plugins/arm/v7/opdefs/ldmda_A8859.d deleted file mode 100644 index 6eb27d1..0000000 --- a/plugins/arm/v7/opdefs/ldmda_A8859.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDMDA/LDMFA - -@id 58 - -@desc { - - Load Multiple Decrement After (Load Multiple Full Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 0 0 0 W(1) 1 Rn(4) register_list(16) - - @syntax { - - @subid 164 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm ldmda wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldmdb_A8860.d b/plugins/arm/v7/opdefs/ldmdb_A8860.d deleted file mode 100644 index a66d2a4..0000000 --- a/plugins/arm/v7/opdefs/ldmdb_A8860.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDMDB/LDMEA - -@id 59 - -@desc { - - Load Multiple Decrement Before (Load Multiple Empty Ascending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the lowest of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 1 0 0 W(1) 1 Rn(4) P(1) M(1) 0 register_list(13) - - @syntax { - - @subid 165 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(P:M:'0':register_list) - - } - - @asm ldmdb wb_reg registers - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 1 0 0 W(1) 1 Rn(4) register_list(16) - - @syntax { - - @subid 166 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm ldmdb wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldmib_A8861.d b/plugins/arm/v7/opdefs/ldmib_A8861.d deleted file mode 100644 index fa12e8a..0000000 --- a/plugins/arm/v7/opdefs/ldmib_A8861.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDMIB/LDMED - -@id 60 - -@desc { - - Load Multiple Increment Before (Load Multiple Empty Descending) loads multiple registers from consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register. The registers loaded can include the PC, causing a branch to a loaded address. Related system instructions are LDM (User registers) on page B9-1986 and LDM (exception return) on page B9-1984. - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 1 1 0 W(1) 1 Rn(4) register_list(16) - - @syntax { - - @subid 167 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm ldmib wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldr_A8862.d b/plugins/arm/v7/opdefs/ldr_A8862.d deleted file mode 100644 index 9771bae..0000000 --- a/plugins/arm/v7/opdefs/ldr_A8862.d +++ /dev/null @@ -1,180 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDR (immediate, Thumb) - -@id 61 - -@desc { - - Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) - - @syntax { - - @subid 168 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - } - -} - -@encoding (t2) { - - @half 1 0 0 1 1 Rt(3) imm8(8) - - @syntax { - - @subid 169 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(13) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 170 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldr.w reg_T maccess - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 171 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - } - - @syntax { - - @subid 172 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - } - - @syntax { - - @subid 173 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/ldr_A8863.d deleted file mode 100644 index e2a443c..0000000 --- a/plugins/arm/v7/opdefs/ldr_A8863.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDR (immediate, ARM) - -@id 62 - -@desc { - - Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 174 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 175 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 176 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/ldr_A8864.d deleted file mode 100644 index fc19f13..0000000 --- a/plugins/arm/v7/opdefs/ldr_A8864.d +++ /dev/null @@ -1,123 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDR (literal) - -@id 63 - -@desc { - - Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 0 1 Rt(3) imm8(8) - - @syntax { - - @subid 177 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm ldr reg_T imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_ldr_literal_from_thumb - post = post_process_ldr_instructions - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 178 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldr.w reg_T imm32 - - } - - @hooks { - - fetch = help_fetching_with_instruction_ldr_literal_from_thumb - post = post_process_ldr_instructions - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 179 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldr reg_T imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - fetch = help_fetching_with_instruction_ldr_literal_from_arm - post = post_process_ldr_instructions - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/ldr_A8865.d deleted file mode 100644 index 8851ea2..0000000 --- a/plugins/arm/v7/opdefs/ldr_A8865.d +++ /dev/null @@ -1,80 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDR (register, Thumb) - -@id 64 - -@desc { - - Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. - -} - -@encoding (t1) { - - @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 180 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldr reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 181 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldr.w reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d deleted file mode 100644 index e676fec..0000000 --- a/plugins/arm/v7/opdefs/ldr_A8866.d +++ /dev/null @@ -1,132 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDR (register, ARM) - -@id 65 - -@desc { - - Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 182 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 183 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 184 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrb_A8867.d b/plugins/arm/v7/opdefs/ldrb_A8867.d deleted file mode 100644 index a5c1a35..0000000 --- a/plugins/arm/v7/opdefs/ldrb_A8867.d +++ /dev/null @@ -1,157 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRB (immediate, Thumb) - -@id 66 - -@desc { - - Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) - - @syntax { - - @subid 185 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 186 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrb.w reg_T maccess - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 187 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - } - - @syntax { - - @subid 188 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - } - - @syntax { - - @subid 189 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrb_A8868.d b/plugins/arm/v7/opdefs/ldrb_A8868.d deleted file mode 100644 index 67f122c..0000000 --- a/plugins/arm/v7/opdefs/ldrb_A8868.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRB (immediate, ARM) - -@id 67 - -@desc { - - Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 190 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 191 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 192 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrb_A8869.d b/plugins/arm/v7/opdefs/ldrb_A8869.d deleted file mode 100644 index defb999..0000000 --- a/plugins/arm/v7/opdefs/ldrb_A8869.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRB (literal) - -@id 68 - -@desc { - - Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 193 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldrb reg_T imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 194 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldrb reg_T imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrb_A8870.d b/plugins/arm/v7/opdefs/ldrb_A8870.d deleted file mode 100644 index b99d19b..0000000 --- a/plugins/arm/v7/opdefs/ldrb_A8870.d +++ /dev/null @@ -1,179 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRB (register) - -@id 69 - -@desc { - - Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 195 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrb reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 196 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldrb.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 197 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldrb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 198 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldrb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 199 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldrb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrbt_A8871.d b/plugins/arm/v7/opdefs/ldrbt_A8871.d deleted file mode 100644 index fdd9176..0000000 --- a/plugins/arm/v7/opdefs/ldrbt_A8871.d +++ /dev/null @@ -1,115 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRBT - -@id 70 - -@desc { - - Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 200 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrbt reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 201 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrbt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 1 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 202 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldrbt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrd_A8872.d b/plugins/arm/v7/opdefs/ldrd_A8872.d deleted file mode 100644 index 752f956..0000000 --- a/plugins/arm/v7/opdefs/ldrd_A8872.d +++ /dev/null @@ -1,213 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRD (immediate) - -@id 71 - -@desc { - - Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) Rt2(4) imm8(8) - - @syntax { - - @subid 203 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrd reg_T reg_T2 maccess - - } - - @syntax { - - @subid 204 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrd reg_T reg_T2 maccess - - } - - @syntax { - - @subid 205 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrd reg_T reg_T2 maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax { - - @subid 206 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 207 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 208 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrd_A8873.d b/plugins/arm/v7/opdefs/ldrd_A8873.d deleted file mode 100644 index 031fb31..0000000 --- a/plugins/arm/v7/opdefs/ldrd_A8873.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRD (literal) - -@id 72 - -@desc { - - Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) Rt2(4) imm8(8) - - @syntax { - - @subid 209 - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - imm32 = ZeroExtend(imm8:'00', 32) - - } - - @asm ldrd reg_T reg_T2 imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 U(1) 1 0 0 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax { - - @subid 210 - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @asm ldrd reg_T reg_T2 imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrd_A8874.d b/plugins/arm/v7/opdefs/ldrd_A8874.d deleted file mode 100644 index c35f2cc..0000000 --- a/plugins/arm/v7/opdefs/ldrd_A8874.d +++ /dev/null @@ -1,132 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRD (register) - -@id 73 - -@desc { - - Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - - @syntax { - - @subid 211 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 212 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm ldrd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 213 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrex_A8875.d b/plugins/arm/v7/opdefs/ldrex_A8875.d deleted file mode 100644 index af19077..0000000 --- a/plugins/arm/v7/opdefs/ldrex_A8875.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDREX - -@id 74 - -@desc { - - Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) - - @syntax { - - @subid 214 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrex reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax { - - @subid 215 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = Zeros(32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrex reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrexb_A8876.d b/plugins/arm/v7/opdefs/ldrexb_A8876.d deleted file mode 100644 index 39b07b3..0000000 --- a/plugins/arm/v7/opdefs/ldrexb_A8876.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDREXB - -@id 75 - -@desc { - - Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 1 1 1 1 - - @syntax { - - @subid 216 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm ldrexb reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax { - - @subid 217 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm ldrexb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrexd_A8877.d b/plugins/arm/v7/opdefs/ldrexd_A8877.d deleted file mode 100644 index 232f4fa..0000000 --- a/plugins/arm/v7/opdefs/ldrexd_A8877.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDREXD - -@id 76 - -@desc { - - Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1 - - @syntax { - - @subid 218 - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm ldrexd reg_T reg_T2 maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax { - - @subid 219 - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm ldrexd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrexh_A8878.d b/plugins/arm/v7/opdefs/ldrexh_A8878.d deleted file mode 100644 index ac124f5..0000000 --- a/plugins/arm/v7/opdefs/ldrexh_A8878.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDREXH - -@id 77 - -@desc { - - Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 1 1 1 1 - - @syntax { - - @subid 220 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm ldrexh reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - - @syntax { - - @subid 221 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm ldrexh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrh_A8879.d b/plugins/arm/v7/opdefs/ldrh_A8879.d deleted file mode 100644 index 674a7d4..0000000 --- a/plugins/arm/v7/opdefs/ldrh_A8879.d +++ /dev/null @@ -1,157 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRH (immediate, Thumb) - -@id 78 - -@desc { - - Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 1 0 0 0 1 imm5(5) Rn(3) Rt(3) - - @syntax { - - @subid 222 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 1 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 223 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrh.w reg_T maccess - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 224 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - } - - @syntax { - - @subid 225 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - } - - @syntax { - - @subid 226 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrh_A8880.d b/plugins/arm/v7/opdefs/ldrh_A8880.d deleted file mode 100644 index 7f7f1f7..0000000 --- a/plugins/arm/v7/opdefs/ldrh_A8880.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRH (immediate, ARM) - -@id 79 - -@desc { - - Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax { - - @subid 227 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 228 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 229 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrh_A8881.d b/plugins/arm/v7/opdefs/ldrh_A8881.d deleted file mode 100644 index 43346e9..0000000 --- a/plugins/arm/v7/opdefs/ldrh_A8881.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRH (literal) - -@id 80 - -@desc { - - Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 230 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldrh reg_T imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax { - - @subid 231 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @asm ldrh reg_T imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrh_A8882.d b/plugins/arm/v7/opdefs/ldrh_A8882.d deleted file mode 100644 index 6f9fb73..0000000 --- a/plugins/arm/v7/opdefs/ldrh_A8882.d +++ /dev/null @@ -1,176 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRH (register) - -@id 81 - -@desc { - - Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 1 0 1 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 232 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrh reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 233 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldrh.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax { - - @subid 234 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 235 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm ldrh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 236 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrht_A8883.d b/plugins/arm/v7/opdefs/ldrht_A8883.d deleted file mode 100644 index 46bd025..0000000 --- a/plugins/arm/v7/opdefs/ldrht_A8883.d +++ /dev/null @@ -1,114 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRHT - -@id 82 - -@desc { - - Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 237 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrht reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax { - - @subid 238 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrht reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax { - - @subid 239 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrht reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsb_A8884.d b/plugins/arm/v7/opdefs/ldrsb_A8884.d deleted file mode 100644 index 828918f..0000000 --- a/plugins/arm/v7/opdefs/ldrsb_A8884.d +++ /dev/null @@ -1,230 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSB (immediate) - -@id 83 - -@desc { - - Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 1 0 0 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 240 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 241 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - } - - @syntax { - - @subid 242 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - } - - @syntax { - - @subid 243 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax { - - @subid 244 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 245 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 246 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrsb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsb_A8885.d b/plugins/arm/v7/opdefs/ldrsb_A8885.d deleted file mode 100644 index 5d5c1c4..0000000 --- a/plugins/arm/v7/opdefs/ldrsb_A8885.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSB (literal) - -@id 84 - -@desc { - - Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 247 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldrsb reg_T imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax { - - @subid 248 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @asm ldrsb reg_T imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/ldrsb_A8886.d deleted file mode 100644 index 9ce942b..0000000 --- a/plugins/arm/v7/opdefs/ldrsb_A8886.d +++ /dev/null @@ -1,176 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSB (register) - -@id 85 - -@desc { - - Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 249 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrsb reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 250 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldrsb.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - - @syntax { - - @subid 251 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrsb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 252 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm ldrsb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 253 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrsb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsbt_A8887.d b/plugins/arm/v7/opdefs/ldrsbt_A8887.d deleted file mode 100644 index 181739c..0000000 --- a/plugins/arm/v7/opdefs/ldrsbt_A8887.d +++ /dev/null @@ -1,114 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSBT - -@id 86 - -@desc { - - Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 254 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsbt reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - - @syntax { - - @subid 255 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrsbt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - - @syntax { - - @subid 256 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrsbt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsh_A8888.d b/plugins/arm/v7/opdefs/ldrsh_A8888.d deleted file mode 100644 index 3d9c2a3..0000000 --- a/plugins/arm/v7/opdefs/ldrsh_A8888.d +++ /dev/null @@ -1,230 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSH (immediate) - -@id 87 - -@desc { - - Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 1 0 1 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 257 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 258 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - } - - @syntax { - - @subid 259 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - } - - @syntax { - - @subid 260 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax { - - @subid 261 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 262 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 263 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrsh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/ldrsh_A8889.d deleted file mode 100644 index d6a6197..0000000 --- a/plugins/arm/v7/opdefs/ldrsh_A8889.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSH (literal) - -@id 88 - -@desc { - - Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - - @syntax { - - @subid 264 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) - - } - - @asm ldrsh reg_T imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax { - - @subid 265 - - @conv { - - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) - - } - - @asm ldrsh reg_T imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsh_A8890.d b/plugins/arm/v7/opdefs/ldrsh_A8890.d deleted file mode 100644 index 9269ca0..0000000 --- a/plugins/arm/v7/opdefs/ldrsh_A8890.d +++ /dev/null @@ -1,176 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSH (register) - -@id 89 - -@desc { - - Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 1 1 1 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 266 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrsh reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 267 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldrsh.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax { - - @subid 268 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm ldrsh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 269 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm ldrsh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 270 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrsh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrsht_A8891.d b/plugins/arm/v7/opdefs/ldrsht_A8891.d deleted file mode 100644 index b1402f7..0000000 --- a/plugins/arm/v7/opdefs/ldrsht_A8891.d +++ /dev/null @@ -1,114 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRSHT - -@id 90 - -@desc { - - Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 271 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrsht reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax { - - @subid 272 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrsht reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax { - - @subid 273 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm ldrsht reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/ldrt_A8892.d deleted file mode 100644 index 23d1d6f..0000000 --- a/plugins/arm/v7/opdefs/ldrt_A8892.d +++ /dev/null @@ -1,115 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LDRT - -@id 91 - -@desc { - - Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 274 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm ldrt reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 275 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm ldrt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 276 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldrt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/lsl_A8894.d b/plugins/arm/v7/opdefs/lsl_A8894.d deleted file mode 100644 index b4689bb..0000000 --- a/plugins/arm/v7/opdefs/lsl_A8894.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LSL (immediate) - -@id 93 - -@desc { - - Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) - - @syntax { - - @subid 277 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('00', imm5) - - } - - @asm lsl ?reg_D reg_M shift_n - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) - - @syntax { - - @subid 278 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('00', imm3:imm2) - - } - - @asm lsl.w ?reg_D reg_M shift_n - - } - - @syntax { - - @subid 279 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('00', imm3:imm2) - - } - - @asm lsls.w ?reg_D reg_M shift_n - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) - - @syntax { - - @subid 280 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('00', imm5) - - } - - @asm lsl ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 281 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('00', imm5) - - } - - @asm lsls ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/lsl_A8895.d b/plugins/arm/v7/opdefs/lsl_A8895.d deleted file mode 100644 index 59bbb91..0000000 --- a/plugins/arm/v7/opdefs/lsl_A8895.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LSL (register) - -@id 94 - -@desc { - - Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 1 0 Rm(3) Rdn(3) - - @syntax { - - @subid 282 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm lsl ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 283 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsl.w ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 284 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsls.w ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 0 1 Rn(4) - - @syntax { - - @subid 285 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsl ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 286 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsls ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/lsr_A8896.d deleted file mode 100644 index 07f12da..0000000 --- a/plugins/arm/v7/opdefs/lsr_A8896.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LSR (immediate) - -@id 95 - -@desc { - - Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) - - @syntax { - - @subid 287 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('01', imm5) - - } - - @asm lsr ?reg_D reg_M shift_n - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) - - @syntax { - - @subid 288 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('01', imm3:imm2) - - } - - @asm lsr.w ?reg_D reg_M shift_n - - } - - @syntax { - - @subid 289 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('01', imm3:imm2) - - } - - @asm lsrs.w ?reg_D reg_M shift_n - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) - - @syntax { - - @subid 290 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('01', imm5) - - } - - @asm lsr ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 291 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('01', imm5) - - } - - @asm lsrs ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/lsr_A8897.d deleted file mode 100644 index fa0b70f..0000000 --- a/plugins/arm/v7/opdefs/lsr_A8897.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title LSR (register) - -@id 96 - -@desc { - - Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) - - @syntax { - - @subid 292 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm lsr ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 293 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsr.w ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 294 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsrs.w ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) - - @syntax { - - @subid 295 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsr ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 296 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm lsrs ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mcr_A8898.d b/plugins/arm/v7/opdefs/mcr_A8898.d deleted file mode 100644 index 8a2252b..0000000 --- a/plugins/arm/v7/opdefs/mcr_A8898.d +++ /dev/null @@ -1,133 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MCR, MCR2 - -@id 97 - -@desc { - - Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 297 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 298 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 299 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 300 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - diff --git a/plugins/arm/v7/opdefs/mcrr_A8899.d b/plugins/arm/v7/opdefs/mcrr_A8899.d deleted file mode 100644 index b500446..0000000 --- a/plugins/arm/v7/opdefs/mcrr_A8899.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MCRR, MCRR2 - -@id 98 - -@desc { - - Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 301 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 302 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 303 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 304 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/mla_A88100.d deleted file mode 100644 index ec8b92b..0000000 --- a/plugins/arm/v7/opdefs/mla_A88100.d +++ /dev/null @@ -1,120 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MLA - -@id 99 - -@desc { - - Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 305 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm mla reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 306 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm mla reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 307 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm mlas reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mls_A88101.d b/plugins/arm/v7/opdefs/mls_A88101.d deleted file mode 100644 index 083e4e1..0000000 --- a/plugins/arm/v7/opdefs/mls_A88101.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MLS - -@id 100 - -@desc { - - Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 308 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm mls reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 1 0 Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 309 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm mls reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d deleted file mode 100644 index 805bc16..0000000 --- a/plugins/arm/v7/opdefs/mov_A88102.d +++ /dev/null @@ -1,210 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MOV (immediate) - -@id 101 - -@desc { - - Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. - -} - -@encoding (t1) { - - @half 0 0 1 0 0 Rd(3) imm8(8) - - @syntax { - - @subid 310 - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8, 32) - - } - - @asm mov reg_D imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 311 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm mov.w reg_D const - - } - - @syntax { - - @subid 312 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm movs.w reg_D const - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 313 - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) - - } - - @asm movw reg_D imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) - - @syntax { - - @subid 314 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm mov reg_D const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 315 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm movs reg_D const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) - - @syntax { - - @subid 316 - - @conv { - - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:imm12, 32) - - } - - @asm movw reg_D imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/mov_A88103.d deleted file mode 100644 index 9497800..0000000 --- a/plugins/arm/v7/opdefs/mov_A88103.d +++ /dev/null @@ -1,123 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MOV (register, Thumb) - -@id 102 - -@desc { - - Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3) - - @syntax { - - @subid 317 - - @conv { - - reg_D = Register(D:Rd) - reg_M = Register(Rm) - - } - - @asm mov reg_D reg_M - - } - -} - -@encoding (t2) { - - @half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3) - - @syntax { - - @subid 318 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm movs reg_D reg_M - - } - -} - -@encoding (T3) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 319 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm mov.w reg_D reg_M - - } - - @syntax { - - @subid 320 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm movs.w reg_D reg_M - - } - -} - diff --git a/plugins/arm/v7/opdefs/mov_A88104.d b/plugins/arm/v7/opdefs/mov_A88104.d deleted file mode 100644 index 3d7eb99..0000000 --- a/plugins/arm/v7/opdefs/mov_A88104.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MOV (register, ARM) - -@id 103 - -@desc { - - Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 Rm(4) - - @syntax { - - @subid 321 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm mov reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 322 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm movs reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/movt_A88106.d b/plugins/arm/v7/opdefs/movt_A88106.d deleted file mode 100644 index dc024df..0000000 --- a/plugins/arm/v7/opdefs/movt_A88106.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MOVT - -@id 105 - -@desc { - - Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 323 - - @conv { - - reg_D = Register(Rd) - imm16 = UInt(imm4:i:imm3:imm8) - - } - - @asm movt reg_D imm16 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12) - - @syntax { - - @subid 324 - - @conv { - - reg_D = Register(Rd) - imm16 = UInt(imm4:imm12) - - } - - @asm movt reg_D imm16 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mrc_A88107.d b/plugins/arm/v7/opdefs/mrc_A88107.d deleted file mode 100644 index ab3f0a1..0000000 --- a/plugins/arm/v7/opdefs/mrc_A88107.d +++ /dev/null @@ -1,133 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MRC, MRC2 - -@id 106 - -@desc { - - Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 325 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 326 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 327 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax { - - @subid 328 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - direct_CRn = UInt(CRn) - direct_CRm = UInt(CRm) - direct_opc2 = UInt(opc2) - - } - - @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 - - } - -} - diff --git a/plugins/arm/v7/opdefs/mrrc_A88108.d b/plugins/arm/v7/opdefs/mrrc_A88108.d deleted file mode 100644 index ea25147..0000000 --- a/plugins/arm/v7/opdefs/mrrc_A88108.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MRRC, MRRC2 - -@id 107 - -@desc { - - Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 329 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 330 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 331 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax { - - @subid 332 - - @conv { - - cp = CoProcessor(coproc) - direct_opc1 = UInt(opc1) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - direct_CRm = UInt(CRm) - - } - - @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm - - } - -} - diff --git a/plugins/arm/v7/opdefs/mrs_A88109.d b/plugins/arm/v7/opdefs/mrs_A88109.d deleted file mode 100644 index 6ea0208..0000000 --- a/plugins/arm/v7/opdefs/mrs_A88109.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MRS - -@id 108 - -@desc { - - Move to Register from Special register moves the value from the APSR into an ARM core register. For details of system level use of this instruction, see MRS on page B9-1988. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 1 1 0 1 1 1 1 1 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 333 - - @conv { - - reg_D = Register(Rd) - spec_reg = SpecRegAPSR() - - } - - @asm mrs reg_D spec_reg - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 0 1 1 1 1 Rd(4) 0 0 0 0 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 334 - - @conv { - - reg_D = Register(Rd) - spec_reg = SpecRegAPSR() - - } - - @asm mrs reg_D spec_reg - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/msr_A88111.d b/plugins/arm/v7/opdefs/msr_A88111.d deleted file mode 100644 index ccf86df..0000000 --- a/plugins/arm/v7/opdefs/msr_A88111.d +++ /dev/null @@ -1,60 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MSR (immediate) - -@id 110 - -@desc { - - Move immediate value to Special register moves selected bits of an immediate value to the corresponding bits in the APSR. For details of system level use of this instruction, see MSR (immediate) on page B9-1994. - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 mask(2) 0 0 1 1 1 1 imm12(12) - - @syntax { - - @subid 335 - - @conv { - - spec_reg = SpecRegFromMask(mask) - imm32 = ARMExpandImm(imm12) - - } - - @asm msr spec_reg imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/msr_A88112.d b/plugins/arm/v7/opdefs/msr_A88112.d deleted file mode 100644 index 89aedc3..0000000 --- a/plugins/arm/v7/opdefs/msr_A88112.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MSR (register) - -@id 111 - -@desc { - - Move to Special register from ARM core register moves selected bits of an ARM core register to the APSR. For details of system level use of this instruction, see MSR (register) on page B9-1996. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 0 0 Rn(4) 1 0 0 0 mask(2) 0 0 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 336 - - @conv { - - spec_reg = SpecRegFromMask(mask) - reg_N = Register(Rn) - - } - - @asm msr spec_reg reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 mask(2) 0 0 1 1 1 1 0 0 0 0 0 0 0 0 Rn(4) - - @syntax { - - @subid 337 - - @conv { - - spec_reg = SpecRegFromMask(mask) - reg_N = Register(Rn) - - } - - @asm msr spec_reg reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/mul_A88114.d deleted file mode 100644 index 9eb245f..0000000 --- a/plugins/arm/v7/opdefs/mul_A88114.d +++ /dev/null @@ -1,139 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MUL - -@id 113 - -@desc { - - Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) - - @syntax { - - @subid 338 - - @conv { - - reg_D = Register(Rdm) - reg_N = Register(Rn) - reg_M = Register(Rdm) - - } - - @asm mul reg_D reg_N ?reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 339 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm mul reg_D reg_N ?reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 340 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm mul reg_D reg_N ?reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 341 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm muls reg_D reg_N ?reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/mvn_A88115.d deleted file mode 100644 index 23d9525..0000000 --- a/plugins/arm/v7/opdefs/mvn_A88115.d +++ /dev/null @@ -1,141 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MVN (immediate) - -@id 114 - -@desc { - - Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 342 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm mvn reg_D const - - } - - @syntax { - - @subid 343 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm mvns reg_D const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) - - @syntax { - - @subid 344 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm mvn reg_D const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 345 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm mvns reg_D const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d deleted file mode 100644 index db9e070..0000000 --- a/plugins/arm/v7/opdefs/mvn_A88116.d +++ /dev/null @@ -1,166 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MVN (register) - -@id 115 - -@desc { - - Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - - @syntax { - - @subid 346 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm mvn reg_D reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 347 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm mvn.w reg_D reg_M ?shift - - } - - @syntax { - - @subid 348 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm mvns.w reg_D reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 349 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm mvn reg_D reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 350 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm mvns reg_D reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/mvn_A88117.d b/plugins/arm/v7/opdefs/mvn_A88117.d deleted file mode 100644 index 8e88096..0000000 --- a/plugins/arm/v7/opdefs/mvn_A88117.d +++ /dev/null @@ -1,99 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title MVN (register-shifted register) - -@id 116 - -@desc { - - Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 351 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm mvn reg_D reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 352 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm mvns reg_D reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/nop_A88119.d b/plugins/arm/v7/opdefs/nop_A88119.d deleted file mode 100644 index 8efcb03..0000000 --- a/plugins/arm/v7/opdefs/nop_A88119.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title NOP - -@id 118 - -@desc { - - No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 353 - - @asm nop - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 354 - - @asm nop.w - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 355 - - @asm nop - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/orn_A88120.d b/plugins/arm/v7/opdefs/orn_A88120.d deleted file mode 100644 index b90857d..0000000 --- a/plugins/arm/v7/opdefs/orn_A88120.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ORN (immediate) - -@id 119 - -@desc { - - Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 356 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm orn ?reg_D reg_N const - - } - - @syntax { - - @subid 357 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm orns ?reg_D reg_N const - - } - -} - diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/orn_A88121.d deleted file mode 100644 index 4e98abe..0000000 --- a/plugins/arm/v7/opdefs/orn_A88121.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ORN (register) - -@id 120 - -@desc { - - Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 358 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm orn ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 359 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm orns ?reg_D reg_N reg_M ?shift - - } - -} - diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/orr_A88122.d deleted file mode 100644 index 9855ad2..0000000 --- a/plugins/arm/v7/opdefs/orr_A88122.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ORR (immediate) - -@id 121 - -@desc { - - Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 360 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm orr ?reg_D reg_N const - - } - - @syntax { - - @subid 361 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm orrs ?reg_D reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 362 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm orr ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 363 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm orrs ?reg_D reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/orr_A88123.d b/plugins/arm/v7/opdefs/orr_A88123.d deleted file mode 100644 index 0a28002..0000000 --- a/plugins/arm/v7/opdefs/orr_A88123.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ORR (register) - -@id 122 - -@desc { - - Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3) - - @syntax { - - @subid 364 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm orr ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 365 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm orr.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 366 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm orrs.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 367 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm orr ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 368 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm orrs ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/orr_A88124.d b/plugins/arm/v7/opdefs/orr_A88124.d deleted file mode 100644 index adc1d42..0000000 --- a/plugins/arm/v7/opdefs/orr_A88124.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ORR (register-shifted register) - -@id 123 - -@desc { - - Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 369 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm orr ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 370 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm orrs ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/pkh_A88125.d b/plugins/arm/v7/opdefs/pkh_A88125.d deleted file mode 100644 index 1ca6a30..0000000 --- a/plugins/arm/v7/opdefs/pkh_A88125.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title PKH - -@id 124 - -@desc { - - Pack Halfword combines one halfword of its first operand with the other halfword of its shifted second operand. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) tb(1) T(1) Rm(4) - - @syntax { - - @subid 371 - - @assert { - - tb == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(tb:'0', imm3:imm2) - - } - - @asm pkhbt ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 372 - - @assert { - - tb == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(tb:'0', imm3:imm2) - - } - - @asm pkhtb ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) imm5(5) tb(1) 0 1 Rm(4) - - @syntax { - - @subid 373 - - @assert { - - tb == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(tb:'0', imm5) - - } - - @asm pkhbt ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 374 - - @assert { - - tb == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(tb:'0', imm5) - - } - - @asm pkhtb ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/pld_A88126.d b/plugins/arm/v7/opdefs/pld_A88126.d deleted file mode 100644 index 3a82fe4..0000000 --- a/plugins/arm/v7/opdefs/pld_A88126.d +++ /dev/null @@ -1,183 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title PLD, PLDW (immediate) - -@id 125 - -@desc { - - Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. On an architecture variant that includes both the PLD and PLDW instructions, the PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 1 0 W(1) 1 Rn(4) 1 1 1 1 imm12(12) - - @syntax { - - @subid 375 - - @assert { - - W == 0 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm pld maccess - - } - - @syntax { - - @subid 376 - - @assert { - - W == 1 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm pldw maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 1 1 1 1 0 0 imm8(8) - - @syntax { - - @subid 377 - - @assert { - - W == 0 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm pld maccess - - } - - @syntax { - - @subid 378 - - @assert { - - W == 1 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm pldw maccess - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 U(1) R(1) 0 1 Rn(4) 1 1 1 1 imm12(12) - - @syntax { - - @subid 379 - - @assert { - - R == 1 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm pld maccess - - } - - @syntax { - - @subid 380 - - @assert { - - R == 0 - - } - - @conv { - - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm pldw maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/pld_A88127.d b/plugins/arm/v7/opdefs/pld_A88127.d deleted file mode 100644 index e753579..0000000 --- a/plugins/arm/v7/opdefs/pld_A88127.d +++ /dev/null @@ -1,73 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title PLD (literal) - -@id 126 - -@desc { - - Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. The effect of a PLD instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 1 1 1 1 imm12(12) - - @syntax { - - @subid 381 - - @conv { - - imm32 = ZeroExtend(imm12, 32) - - } - - @asm pld imm32 - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 0 1 U(1) 1 0 1 1 1 1 1 1 1 1 1 imm12(12) - - @syntax { - - @subid 382 - - @conv { - - imm32 = ZeroExtend(imm12, 32) - - } - - @asm pld imm32 - - } - -} - diff --git a/plugins/arm/v7/opdefs/pld_A88128.d b/plugins/arm/v7/opdefs/pld_A88128.d deleted file mode 100644 index 5c7eb2d..0000000 --- a/plugins/arm/v7/opdefs/pld_A88128.d +++ /dev/null @@ -1,137 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title PLD, PLDW (register) - -@id 127 - -@desc { - - Preload Data signals the memory system that data memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the data cache. On an architecture variant that includes both the PLD and PLDW instructions, the PLD instruction signals that the likely memory access is a read, and the PLDW instruction signals that it is a write. The effect of a PLD or PLDW instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 W(1) 1 Rn(4) 1 1 1 1 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 383 - - @assert { - - W == 0 - - } - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm pld maccess - - } - - @syntax { - - @subid 384 - - @assert { - - W == 1 - - } - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm pldw maccess - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 1 1 U(1) R(1) 0 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 385 - - @assert { - - R == 1 - - } - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm pld maccess - - } - - @syntax { - - @subid 386 - - @assert { - - R == 0 - - } - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm pldw maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/pli_A88130.d b/plugins/arm/v7/opdefs/pli_A88130.d deleted file mode 100644 index e669ff8..0000000 --- a/plugins/arm/v7/opdefs/pli_A88130.d +++ /dev/null @@ -1,79 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title PLI (register) - -@id 129 - -@desc { - - Preload Instruction signals the memory system that instruction memory accesses from a specified address are likely in the near future. The memory system can respond by taking actions that are expected to speed up the memory accesses when they do occur, such as pre-loading the cache line containing the specified address into the instruction cache. For more information, see Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. The effect of a PLI instruction is IMPLEMENTATION DEFINED. For more information, see Preloading caches on page A3-157 and Behavior of Preload Data (PLD, PLDW) and Preload Instruction (PLI) with caches on page B2-1269. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) 1 1 1 1 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 387 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm pli maccess - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 1 1 0 U(1) 1 0 1 Rn(4) 1 1 1 1 imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 388 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm pli maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/pop_A88131.d b/plugins/arm/v7/opdefs/pop_A88131.d deleted file mode 100644 index 12f1254..0000000 --- a/plugins/arm/v7/opdefs/pop_A88131.d +++ /dev/null @@ -1,111 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title POP (Thumb) - -@id 130 - -@desc { - - Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 0 P(1) register_list(8) - - @syntax { - - @subid 389 - - @conv { - - registers = RegList(P:'0000000':register_list) - - } - - @asm pop registers - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13) - - @syntax { - - @subid 390 - - @conv { - - registers = RegList(P:M:'0':register_list) - - } - - @asm pop.w registers - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0 - - @syntax { - - @subid 391 - - @conv { - - registers = SingleRegList(Rt) - - } - - @asm pop.w registers - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - diff --git a/plugins/arm/v7/opdefs/pop_A88132.d b/plugins/arm/v7/opdefs/pop_A88132.d deleted file mode 100644 index f4e681e..0000000 --- a/plugins/arm/v7/opdefs/pop_A88132.d +++ /dev/null @@ -1,97 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title POP (ARM) - -@id 131 - -@desc { - - Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) - - @syntax { - - @subid 392 - - @conv { - - registers = RegList(register_list) - - } - - @asm pop registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax { - - @subid 393 - - @conv { - - registers = SingleRegList(Rt) - - } - - @asm pop registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @hooks { - - link = handle_armv7_return_from_pop - - } - -} - diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/push_A88133.d deleted file mode 100644 index 6240e66..0000000 --- a/plugins/arm/v7/opdefs/push_A88133.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title PUSH - -@id 132 - -@desc { - - Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 1 0 M(1) register_list(8) - - @syntax { - - @subid 394 - - @conv { - - registers = RegList('0':M:'000000':register_list) - - } - - @asm push registers - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13) - - @syntax { - - @subid 395 - - @conv { - - registers = RegList('0':M:'0':register_list) - - } - - @asm push.w registers - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0 - - @syntax { - - @subid 396 - - @conv { - - registers = SingleRegList(Rt) - - } - - @asm push.w registers - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16) - - @syntax { - - @subid 397 - - @conv { - - registers = RegList(register_list) - - } - - @asm push registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax { - - @subid 398 - - @conv { - - registers = SingleRegList(Rt) - - } - - @asm push registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qadd16_A88135.d b/plugins/arm/v7/opdefs/qadd16_A88135.d deleted file mode 100644 index 4bcaff9..0000000 --- a/plugins/arm/v7/opdefs/qadd16_A88135.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QADD16 - -@id 134 - -@desc { - - Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 401 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qadd16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 402 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qadd16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qadd8_A88136.d b/plugins/arm/v7/opdefs/qadd8_A88136.d deleted file mode 100644 index 7ceda6a..0000000 --- a/plugins/arm/v7/opdefs/qadd8_A88136.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QADD8 - -@id 135 - -@desc { - - Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 403 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qadd8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax { - - @subid 404 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qadd8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qadd_A88134.d b/plugins/arm/v7/opdefs/qadd_A88134.d deleted file mode 100644 index 11d86b1..0000000 --- a/plugins/arm/v7/opdefs/qadd_A88134.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QADD - -@id 133 - -@desc { - - Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax { - - @subid 399 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qadd ?reg_D reg_M reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax { - - @subid 400 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qadd ?reg_D reg_M reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qasx_A88137.d b/plugins/arm/v7/opdefs/qasx_A88137.d deleted file mode 100644 index 4c62bca..0000000 --- a/plugins/arm/v7/opdefs/qasx_A88137.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QASX - -@id 136 - -@desc { - - Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 405 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qasx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 406 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qasx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qdadd_A88138.d b/plugins/arm/v7/opdefs/qdadd_A88138.d deleted file mode 100644 index 8f49b67..0000000 --- a/plugins/arm/v7/opdefs/qdadd_A88138.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QDADD - -@id 137 - -@desc { - - Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - - @syntax { - - @subid 407 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qdadd ?reg_D reg_M reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax { - - @subid 408 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qdadd ?reg_D reg_M reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qdsub_A88139.d b/plugins/arm/v7/opdefs/qdsub_A88139.d deleted file mode 100644 index 2747f27..0000000 --- a/plugins/arm/v7/opdefs/qdsub_A88139.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QDSUB - -@id 138 - -@desc { - - Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - - @syntax { - - @subid 409 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qdsub ?reg_D reg_M reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax { - - @subid 410 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qdsub ?reg_D reg_M reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/qsax_A88140.d deleted file mode 100644 index f8217b2..0000000 --- a/plugins/arm/v7/opdefs/qsax_A88140.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QSAX - -@id 139 - -@desc { - - Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 411 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qsax ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax { - - @subid 412 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qsax ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qsub16_A88142.d b/plugins/arm/v7/opdefs/qsub16_A88142.d deleted file mode 100644 index b971c85..0000000 --- a/plugins/arm/v7/opdefs/qsub16_A88142.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QSUB16 - -@id 141 - -@desc { - - Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 415 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qsub16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax { - - @subid 416 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qsub16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qsub8_A88143.d b/plugins/arm/v7/opdefs/qsub8_A88143.d deleted file mode 100644 index d7f96c7..0000000 --- a/plugins/arm/v7/opdefs/qsub8_A88143.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QSUB8 - -@id 142 - -@desc { - - Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - - @syntax { - - @subid 417 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qsub8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax { - - @subid 418 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm qsub8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/qsub_A88141.d b/plugins/arm/v7/opdefs/qsub_A88141.d deleted file mode 100644 index 89d034b..0000000 --- a/plugins/arm/v7/opdefs/qsub_A88141.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title QSUB - -@id 140 - -@desc { - - Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - - @syntax { - - @subid 413 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qsub ?reg_D reg_M reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - - @syntax { - - @subid 414 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - reg_N = Register(Rn) - - } - - @asm qsub ?reg_D reg_M reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rbit_A88144.d b/plugins/arm/v7/opdefs/rbit_A88144.d deleted file mode 100644 index b5c610c..0000000 --- a/plugins/arm/v7/opdefs/rbit_A88144.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RBIT - -@id 143 - -@desc { - - Reverse Bits reverses the bit order in a 32-bit register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - - @syntax { - - @subid 419 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rbit reg_D reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 420 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rbit reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/rev16_A88146.d deleted file mode 100644 index 49821e5..0000000 --- a/plugins/arm/v7/opdefs/rev16_A88146.d +++ /dev/null @@ -1,102 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title REV16 - -@id 145 - -@desc { - - Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3) - - @syntax { - - @subid 424 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rev16 reg_D reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - - @syntax { - - @subid 425 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rev16.w reg_D reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - - @syntax { - - @subid 426 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rev16 reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rev_A88145.d b/plugins/arm/v7/opdefs/rev_A88145.d deleted file mode 100644 index cb81837..0000000 --- a/plugins/arm/v7/opdefs/rev_A88145.d +++ /dev/null @@ -1,102 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title REV - -@id 144 - -@desc { - - Byte-Reverse Word reverses the byte order in a 32-bit register. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 0 1 0 0 0 Rm(3) Rd(3) - - @syntax { - - @subid 421 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rev reg_D reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax { - - @subid 422 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rev.w reg_D reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 423 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rev reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/revsh_A88147.d b/plugins/arm/v7/opdefs/revsh_A88147.d deleted file mode 100644 index bf04a89..0000000 --- a/plugins/arm/v7/opdefs/revsh_A88147.d +++ /dev/null @@ -1,102 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title REVSH - -@id 146 - -@desc { - - Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 0 1 0 1 1 Rm(3) Rd(3) - - @syntax { - - @subid 427 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm revsh reg_D reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - - @syntax { - - @subid 428 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm revsh.w reg_D reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - - @syntax { - - @subid 429 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm revsh reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ror_A88149.d b/plugins/arm/v7/opdefs/ror_A88149.d deleted file mode 100644 index 98735fd..0000000 --- a/plugins/arm/v7/opdefs/ror_A88149.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ROR (immediate) - -@id 148 - -@desc { - - Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 1 Rm(4) - - @syntax { - - @subid 430 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('11', imm3:imm2) - - } - - @asm ror ?reg_D reg_M shift_n - - } - - @syntax { - - @subid 431 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('11', imm3:imm2) - - } - - @asm rors ?reg_D reg_M shift_n - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 1 0 Rm(4) - - @syntax { - - @subid 432 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('11', imm5) - - } - - @asm ror ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 433 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_n = DecodeImmShiftAmount('11', imm5) - - } - - @asm rors ?reg_D reg_M shift_n - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ror_A88150.d b/plugins/arm/v7/opdefs/ror_A88150.d deleted file mode 100644 index 031f56e..0000000 --- a/plugins/arm/v7/opdefs/ror_A88150.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title ROR (register) - -@id 149 - -@desc { - - Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 1 1 Rm(3) Rdn(3) - - @syntax { - - @subid 434 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm ror ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 435 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ror.w ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 436 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm rors.w ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 1 1 Rn(4) - - @syntax { - - @subid 437 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ror ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 438 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm rors ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/rrx_A88151.d deleted file mode 100644 index 445a5d3..0000000 --- a/plugins/arm/v7/opdefs/rrx_A88151.d +++ /dev/null @@ -1,141 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RRX - -@id 150 - -@desc { - - Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4) - - @syntax { - - @subid 439 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rrx ?reg_D reg_M - - } - - @syntax { - - @subid 440 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rrxs ?reg_D reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4) - - @syntax { - - @subid 441 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rrx ?reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 442 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm rrxs ?reg_D reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/rsb_A88152.d deleted file mode 100644 index 9b5e13e..0000000 --- a/plugins/arm/v7/opdefs/rsb_A88152.d +++ /dev/null @@ -1,167 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RSB (immediate) - -@id 151 - -@desc { - - Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) - - @syntax { - - @subid 443 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = Zeros(32) - - } - - @asm rsb ?reg_D reg_N imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 444 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm rsb.w ?reg_D reg_N imm32 - - } - - @syntax { - - @subid 445 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm rsbs.w ?reg_D reg_N imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 446 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm rsb ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 447 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm rsbs ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rsb_A88153.d b/plugins/arm/v7/opdefs/rsb_A88153.d deleted file mode 100644 index cb8ad6d..0000000 --- a/plugins/arm/v7/opdefs/rsb_A88153.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RSB (register) - -@id 152 - -@desc { - - Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 448 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm rsb ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 449 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm rsbs ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 450 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm rsb ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 451 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm rsbs ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rsb_A88154.d b/plugins/arm/v7/opdefs/rsb_A88154.d deleted file mode 100644 index cfc0a11..0000000 --- a/plugins/arm/v7/opdefs/rsb_A88154.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RSB (register-shifted register) - -@id 153 - -@desc { - - Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 452 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm rsb ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 453 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm rsbs ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rsc_A88155.d b/plugins/arm/v7/opdefs/rsc_A88155.d deleted file mode 100644 index e30a4a1..0000000 --- a/plugins/arm/v7/opdefs/rsc_A88155.d +++ /dev/null @@ -1,95 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RSC (immediate) - -@id 154 - -@desc { - - Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 1 1 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 454 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm rsc ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 455 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm rscs ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rsc_A88156.d b/plugins/arm/v7/opdefs/rsc_A88156.d deleted file mode 100644 index 63d39fb..0000000 --- a/plugins/arm/v7/opdefs/rsc_A88156.d +++ /dev/null @@ -1,97 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RSC (register) - -@id 155 - -@desc { - - Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 456 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm rsc ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 457 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm rscs ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/rsc_A88157.d b/plugins/arm/v7/opdefs/rsc_A88157.d deleted file mode 100644 index 25d1ea2..0000000 --- a/plugins/arm/v7/opdefs/rsc_A88157.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title RSC (register-shifted register) - -@id 156 - -@desc { - - Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 458 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm rsc ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 459 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm rscs ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sadd16_A88158.d b/plugins/arm/v7/opdefs/sadd16_A88158.d deleted file mode 100644 index b181221..0000000 --- a/plugins/arm/v7/opdefs/sadd16_A88158.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SADD16 - -@id 157 - -@desc { - - Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 460 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sadd16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 461 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sadd16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sadd8_A88159.d b/plugins/arm/v7/opdefs/sadd8_A88159.d deleted file mode 100644 index 94a91d7..0000000 --- a/plugins/arm/v7/opdefs/sadd8_A88159.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SADD8 - -@id 158 - -@desc { - - Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 462 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sadd8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax { - - @subid 463 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sadd8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sasx_A88160.d b/plugins/arm/v7/opdefs/sasx_A88160.d deleted file mode 100644 index 30c86be..0000000 --- a/plugins/arm/v7/opdefs/sasx_A88160.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SASX - -@id 159 - -@desc { - - Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 464 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sasx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 465 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sasx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sbc_A88161.d b/plugins/arm/v7/opdefs/sbc_A88161.d deleted file mode 100644 index 8d307fa..0000000 --- a/plugins/arm/v7/opdefs/sbc_A88161.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SBC (immediate) - -@id 160 - -@desc { - - Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 466 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm sbc ?reg_D reg_N imm32 - - } - - @syntax { - - @subid 467 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm sbcs ?reg_D reg_N imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 468 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm sbc ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 469 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm sbcs ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/sbc_A88162.d deleted file mode 100644 index 27f97fc..0000000 --- a/plugins/arm/v7/opdefs/sbc_A88162.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SBC (register) - -@id 161 - -@desc { - - Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) - - @syntax { - - @subid 470 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - reg_M = Register(Rm) - - } - - @asm sbc ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 471 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm sbc.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 472 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm sbcs.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 473 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm sbc ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 474 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm sbcs ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sbc_A88163.d b/plugins/arm/v7/opdefs/sbc_A88163.d deleted file mode 100644 index a7e7c27..0000000 --- a/plugins/arm/v7/opdefs/sbc_A88163.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SBC (register-shifted register) - -@id 162 - -@desc { - - Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 475 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm sbc ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 476 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm sbcs ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sbfx_A88164.d b/plugins/arm/v7/opdefs/sbfx_A88164.d deleted file mode 100644 index 8a3f4de..0000000 --- a/plugins/arm/v7/opdefs/sbfx_A88164.d +++ /dev/null @@ -1,87 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SBFX - -@id 163 - -@desc { - - Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - - @syntax { - - @subid 477 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - widthminus1 = UInt(widthm1) - width = MinusBitDiff(widthminus1, lsbit) - - } - - @asm sbfx reg_D reg_N lsbit width - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 0 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - - @syntax { - - @subid 478 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - widthminus1 = UInt(widthm1) - width = MinusBitDiff(widthminus1, lsbit) - - } - - @asm sbfx reg_D reg_N lsbit width - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/sdiv_A88165.d deleted file mode 100644 index 0e74d6c..0000000 --- a/plugins/arm/v7/opdefs/sdiv_A88165.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SDIV - -@id 164 - -@desc { - - Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - - @syntax { - - @subid 479 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sdiv ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - - @syntax { - - @subid 480 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sdiv ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sel_A88166.d b/plugins/arm/v7/opdefs/sel_A88166.d deleted file mode 100644 index 660dd46..0000000 --- a/plugins/arm/v7/opdefs/sel_A88166.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SEL - -@id 165 - -@desc { - - Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - - @syntax { - - @subid 481 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sel ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - - @syntax { - - @subid 482 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sel ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/setend_A88167.d b/plugins/arm/v7/opdefs/setend_A88167.d deleted file mode 100644 index ac6d59b..0000000 --- a/plugins/arm/v7/opdefs/setend_A88167.d +++ /dev/null @@ -1,73 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SETEND - -@id 166 - -@desc { - - Set Endianness writes a new value to ENDIANSTATE. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 1 1 0 0 1 0 1 E(1) 0 0 0 - - @syntax { - - @subid 483 - - @conv { - - endian_specifier = Endian(E) - - } - - @asm setend endian_specifier - - } - -} - -@encoding (A1) { - - @word 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 E(1) 0 0 0 0 0 0 0 0 0 - - @syntax { - - @subid 484 - - @conv { - - endian_specifier = Endian(E) - - } - - @asm setend endian_specifier - - } - -} - diff --git a/plugins/arm/v7/opdefs/sev_A88168.d b/plugins/arm/v7/opdefs/sev_A88168.d deleted file mode 100644 index 8695ace..0000000 --- a/plugins/arm/v7/opdefs/sev_A88168.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SEV - -@id 167 - -@desc { - - Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 - - @syntax { - - @subid 485 - - @asm sev - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax { - - @subid 486 - - @asm sev.w - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 - - @syntax { - - @subid 487 - - @asm sev - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/shadd16_A88169.d b/plugins/arm/v7/opdefs/shadd16_A88169.d deleted file mode 100644 index 0ecbd43..0000000 --- a/plugins/arm/v7/opdefs/shadd16_A88169.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SHADD16 - -@id 168 - -@desc { - - Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax { - - @subid 488 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shadd16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 489 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shadd16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/shadd8_A88170.d b/plugins/arm/v7/opdefs/shadd8_A88170.d deleted file mode 100644 index c1d358a..0000000 --- a/plugins/arm/v7/opdefs/shadd8_A88170.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SHADD8 - -@id 169 - -@desc { - - Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax { - - @subid 490 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shadd8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax { - - @subid 491 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shadd8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/shasx_A88171.d b/plugins/arm/v7/opdefs/shasx_A88171.d deleted file mode 100644 index b48ef07..0000000 --- a/plugins/arm/v7/opdefs/shasx_A88171.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SHASX - -@id 170 - -@desc { - - Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax { - - @subid 492 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shasx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 493 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shasx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/shsax_A88172.d b/plugins/arm/v7/opdefs/shsax_A88172.d deleted file mode 100644 index f9d0742..0000000 --- a/plugins/arm/v7/opdefs/shsax_A88172.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SHSAX - -@id 171 - -@desc { - - Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax { - - @subid 494 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shsax ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax { - - @subid 495 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shsax ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/shsub16_A88173.d b/plugins/arm/v7/opdefs/shsub16_A88173.d deleted file mode 100644 index 802def4..0000000 --- a/plugins/arm/v7/opdefs/shsub16_A88173.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SHSUB16 - -@id 172 - -@desc { - - Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax { - - @subid 496 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shsub16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax { - - @subid 497 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shsub16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/shsub8_A88174.d b/plugins/arm/v7/opdefs/shsub8_A88174.d deleted file mode 100644 index a4113db..0000000 --- a/plugins/arm/v7/opdefs/shsub8_A88174.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SHSUB8 - -@id 173 - -@desc { - - Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - - @syntax { - - @subid 498 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shsub8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax { - - @subid 499 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm shsub8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smla_A88176.d b/plugins/arm/v7/opdefs/smla_A88176.d deleted file mode 100644 index b167f82..0000000 --- a/plugins/arm/v7/opdefs/smla_A88176.d +++ /dev/null @@ -1,261 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLABB, SMLABT, SMLATB, SMLATT - -@id 175 - -@desc { - - Signed Multiply Accumulate (halfwords) performs a signed multiply accumulate operation. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is added to a 32-bit accumulate value and the result is written to the destination register. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. It is not possible for overflow to occur during the multiplication. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 0 1 Rn(4) Ra(4) Rd(4) 0 0 N(1) M(1) Rm(4) - - @syntax { - - @subid 500 - - @assert { - - N == 1 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlatt reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 501 - - @assert { - - N == 1 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlatb reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 502 - - @assert { - - N == 0 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlabt reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 503 - - @assert { - - N == 0 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlabb reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 1 M(1) N(1) 0 Rn(4) - - @syntax { - - @subid 504 - - @assert { - - N == 1 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlatt reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 505 - - @assert { - - N == 1 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlatb reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 506 - - @assert { - - N == 0 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlabt reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 507 - - @assert { - - N == 0 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlabb reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlad_A88177.d b/plugins/arm/v7/opdefs/smlad_A88177.d deleted file mode 100644 index ff62a60..0000000 --- a/plugins/arm/v7/opdefs/smlad_A88177.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLAD - -@id 176 - -@desc { - - Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - - @syntax { - - @subid 508 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlad reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 509 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smladx reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 M(1) 1 Rn(4) - - @syntax { - - @subid 510 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlad reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 511 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smladx reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/smlal_A88178.d deleted file mode 100644 index 311ae7d..0000000 --- a/plugins/arm/v7/opdefs/smlal_A88178.d +++ /dev/null @@ -1,120 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLAL - -@id 177 - -@desc { - - Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 512 - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlal reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 513 - - @assert { - - S == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlal reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 514 - - @assert { - - S == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlals reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlal_A88179.d b/plugins/arm/v7/opdefs/smlal_A88179.d deleted file mode 100644 index f7ce190..0000000 --- a/plugins/arm/v7/opdefs/smlal_A88179.d +++ /dev/null @@ -1,261 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLALBB, SMLALBT, SMLALTB, SMLALTT - -@id 178 - -@desc { - - Signed Multiply Accumulate Long (halfwords) multiplies two signed 16-bit values to produce a 32-bit value, and accumulates this with a 64-bit value. The multiply acts on two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is sign-extended and accumulated with a 64-bit accumulate value. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 0 N(1) M(1) Rm(4) - - @syntax { - - @subid 515 - - @assert { - - N == 1 - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlaltt reg_DLO reg_DHI reg_N reg_M - - } - - @syntax { - - @subid 516 - - @assert { - - N == 1 - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlaltb reg_DLO reg_DHI reg_N reg_M - - } - - @syntax { - - @subid 517 - - @assert { - - N == 0 - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlalbt reg_DLO reg_DHI reg_N reg_M - - } - - @syntax { - - @subid 518 - - @assert { - - N == 0 - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlalbb reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 M(1) N(1) 0 Rn(4) - - @syntax { - - @subid 519 - - @assert { - - N == 1 - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlaltt reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 520 - - @assert { - - N == 1 - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlaltb reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 521 - - @assert { - - N == 0 - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlalbt reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 522 - - @assert { - - N == 0 - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlalbb reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/smlald_A88180.d deleted file mode 100644 index ed8e718..0000000 --- a/plugins/arm/v7/opdefs/smlald_A88180.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLALD - -@id 179 - -@desc { - - Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - - @syntax { - - @subid 523 - - @assert { - - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlald reg_DLO reg_DHI reg_N reg_M - - } - - @syntax { - - @subid 524 - - @assert { - - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlaldx reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4) - - @syntax { - - @subid 525 - - @assert { - - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlald reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 526 - - @assert { - - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlaldx reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlaw_A88181.d b/plugins/arm/v7/opdefs/smlaw_A88181.d deleted file mode 100644 index d9b8918..0000000 --- a/plugins/arm/v7/opdefs/smlaw_A88181.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLAWB, SMLAWT - -@id 180 - -@desc { - - Signed Multiply Accumulate (word by halfword) performs a signed multiply accumulate operation. The multiply acts on a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are added to a 32-bit accumulate value and the result is written to the destination register. The bottom 16 bits of the 48-bit product are ignored. If overflow occurs during the addition of the accumulate value, the instruction sets the Q flag in the APSR. No overflow can occur during the multiplication. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - - @syntax { - - @subid 527 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlawt reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 528 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlawb reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 Rd(4) Ra(4) Rm(4) 1 M(1) 0 0 Rn(4) - - @syntax { - - @subid 529 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlawt reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 530 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlawb reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/smlsd_A88182.d deleted file mode 100644 index e24eb18..0000000 --- a/plugins/arm/v7/opdefs/smlsd_A88182.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLSD - -@id 181 - -@desc { - - Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - - @syntax { - - @subid 531 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlsd reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 532 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlsdx reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4) - - @syntax { - - @subid 533 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlsd reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 534 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smlsdx reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smlsld_A88183.d b/plugins/arm/v7/opdefs/smlsld_A88183.d deleted file mode 100644 index 2b82705..0000000 --- a/plugins/arm/v7/opdefs/smlsld_A88183.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMLSLD - -@id 182 - -@desc { - - Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 0 1 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - - @syntax { - - @subid 535 - - @assert { - - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlsld reg_DLO reg_DHI reg_N reg_M - - } - - @syntax { - - @subid 536 - - @assert { - - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlsldx reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 1 M(1) 1 Rn(4) - - @syntax { - - @subid 537 - - @assert { - - M == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlsld reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 538 - - @assert { - - M == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smlsldx reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/smmla_A88184.d deleted file mode 100644 index a025895..0000000 --- a/plugins/arm/v7/opdefs/smmla_A88184.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMMLA - -@id 183 - -@desc { - - Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - - @syntax { - - @subid 539 - - @assert { - - R == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmla reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 540 - - @assert { - - R == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmlar reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4) - - @syntax { - - @subid 541 - - @assert { - - R == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmla reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 542 - - @assert { - - R == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmlar reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smmls_A88185.d b/plugins/arm/v7/opdefs/smmls_A88185.d deleted file mode 100644 index 18bd82c..0000000 --- a/plugins/arm/v7/opdefs/smmls_A88185.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMMLS - -@id 184 - -@desc { - - Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - - @syntax { - - @subid 543 - - @assert { - - R == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmls reg_D reg_N reg_M reg_A - - } - - @syntax { - - @subid 544 - - @assert { - - R == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmlsr reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 1 1 R(1) 1 Rn(4) - - @syntax { - - @subid 545 - - @assert { - - R == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmls reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 546 - - @assert { - - R == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm smmlsr reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/smmul_A88186.d deleted file mode 100644 index f1b2579..0000000 --- a/plugins/arm/v7/opdefs/smmul_A88186.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMMUL - -@id 185 - -@desc { - - Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4) - - @syntax { - - @subid 547 - - @assert { - - R == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smmul ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 548 - - @assert { - - R == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smmulr ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4) - - @syntax { - - @subid 549 - - @assert { - - R == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smmul ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 550 - - @assert { - - R == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smmulr ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/smuad_A88187.d deleted file mode 100644 index c5fc1e8..0000000 --- a/plugins/arm/v7/opdefs/smuad_A88187.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMUAD - -@id 186 - -@desc { - - Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) - - @syntax { - - @subid 551 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smuad ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 552 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smuadx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4) - - @syntax { - - @subid 553 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smuad ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 554 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smuadx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smul_A88188.d b/plugins/arm/v7/opdefs/smul_A88188.d deleted file mode 100644 index 18d8631..0000000 --- a/plugins/arm/v7/opdefs/smul_A88188.d +++ /dev/null @@ -1,253 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMULBB, SMULBT, SMULTB, SMULTT - -@id 187 - -@desc { - - Signed Multiply (halfwords) multiplies two signed 16-bit quantities, taken from either the bottom or the top half of their respective source registers. The other halves of these source registers are ignored. The 32-bit product is written to the destination register. No overflow is possible during this instruction. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 N(1) M(1) Rm(4) - - @syntax { - - @subid 555 - - @assert { - - N == 1 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smultt ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 556 - - @assert { - - N == 1 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smultb ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 557 - - @assert { - - N == 0 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulbt ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 558 - - @assert { - - N == 0 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulbb ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 1 1 0 Rd(4) 0 0 0 0 Rm(4) 1 M(1) N(1) 0 Rn(4) - - @syntax { - - @subid 559 - - @assert { - - N == 1 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smultt ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 560 - - @assert { - - N == 1 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smultb ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 561 - - @assert { - - N == 0 - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulbt ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 562 - - @assert { - - N == 0 - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulbb ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/smull_A88189.d deleted file mode 100644 index 1903894..0000000 --- a/plugins/arm/v7/opdefs/smull_A88189.d +++ /dev/null @@ -1,120 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMULL - -@id 188 - -@desc { - - Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 563 - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smull reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 564 - - @assert { - - S == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smull reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 565 - - @assert { - - S == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulls reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smulw_A88190.d b/plugins/arm/v7/opdefs/smulw_A88190.d deleted file mode 100644 index 5b5d5d3..0000000 --- a/plugins/arm/v7/opdefs/smulw_A88190.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMULWB, SMULWT - -@id 189 - -@desc { - - Signed Multiply (word by halfword) multiplies a signed 32-bit quantity and a signed 16-bit quantity. The signed 16-bit quantity is taken from either the bottom or the top half of its source register. The other half of the second source register is ignored. The top 32 bits of the 48-bit product are written to the destination register. The bottom 16 bits of the 48-bit product are ignored. No overflow is possible during this instruction. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) - - @syntax { - - @subid 566 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulwt ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 567 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulwb ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 0 Rd(4) 0 0 0 0 Rm(4) 1 M(1) 1 0 Rn(4) - - @syntax { - - @subid 568 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulwt ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 569 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smulwb ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/smusd_A88191.d b/plugins/arm/v7/opdefs/smusd_A88191.d deleted file mode 100644 index 7ab2e6d..0000000 --- a/plugins/arm/v7/opdefs/smusd_A88191.d +++ /dev/null @@ -1,145 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SMUSD - -@id 190 - -@desc { - - Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It subtracts one of the products from the other, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow cannot occur. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) - - @syntax { - - @subid 570 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smusd ?reg_D reg_N reg_M - - } - - @syntax { - - @subid 571 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smusdx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 1 M(1) 1 Rn(4) - - @syntax { - - @subid 572 - - @assert { - - M == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smusd ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 573 - - @assert { - - M == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm smusdx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ssat16_A88194.d b/plugins/arm/v7/opdefs/ssat16_A88194.d deleted file mode 100644 index 6cae060..0000000 --- a/plugins/arm/v7/opdefs/ssat16_A88194.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SSAT16 - -@id 193 - -@desc { - - Signed Saturate 16 saturates two signed 16-bit values to a selected signed range. The Q flag is set if the operation saturates. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) - - @syntax { - - @subid 576 - - @conv { - - reg_D = Register(Rd) - saturate_to = UIntInc(sat_imm) - reg_N = Register(Rn) - - } - - @asm ssat16 reg_D saturate_to reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) - - @syntax { - - @subid 577 - - @conv { - - reg_D = Register(Rd) - saturate_to = UIntInc(sat_imm) - reg_N = Register(Rn) - - } - - @asm ssat16 reg_D saturate_to reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ssat_A88193.d b/plugins/arm/v7/opdefs/ssat_A88193.d deleted file mode 100644 index 835b80f..0000000 --- a/plugins/arm/v7/opdefs/ssat_A88193.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SSAT - -@id 192 - -@desc { - - Signed Saturate saturates an optionally-shifted signed value to a selectable signed range. The Q flag is set if the operation saturates. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 0 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) - - @syntax { - - @subid 574 - - @conv { - - reg_D = Register(Rd) - saturate_to = UIntInc(sat_imm) - reg_N = Register(Rn) - shift = DecodeImmShift(sh:'0', imm3:imm2) - - } - - @asm ssat reg_D saturate_to reg_N ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) - - @syntax { - - @subid 575 - - @conv { - - reg_D = Register(Rd) - saturate_to = UIntInc(sat_imm) - reg_N = Register(Rn) - shift = DecodeImmShift(sh:'0', imm5) - - } - - @asm ssat reg_D saturate_to reg_N ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ssax_A88195.d b/plugins/arm/v7/opdefs/ssax_A88195.d deleted file mode 100644 index be5e94a..0000000 --- a/plugins/arm/v7/opdefs/ssax_A88195.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SSAX - -@id 194 - -@desc { - - Signed Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 578 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ssax ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax { - - @subid 579 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ssax ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ssub16_A88196.d b/plugins/arm/v7/opdefs/ssub16_A88196.d deleted file mode 100644 index b3a1935..0000000 --- a/plugins/arm/v7/opdefs/ssub16_A88196.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SSUB16 - -@id 195 - -@desc { - - Signed Subtract 16 performs two 16-bit signed integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 580 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ssub16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax { - - @subid 581 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ssub16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ssub8_A88197.d b/plugins/arm/v7/opdefs/ssub8_A88197.d deleted file mode 100644 index b7b9d9c..0000000 --- a/plugins/arm/v7/opdefs/ssub8_A88197.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SSUB8 - -@id 196 - -@desc { - - Signed Subtract 8 performs four 8-bit signed integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 582 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ssub8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax { - - @subid 583 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm ssub8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/stc_A88198.d b/plugins/arm/v7/opdefs/stc_A88198.d deleted file mode 100644 index 88b68ac..0000000 --- a/plugins/arm/v7/opdefs/stc_A88198.d +++ /dev/null @@ -1,461 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STC, STC2 - -@id 197 - -@desc { - - Store Coprocessor stores data from a coprocessor to a sequence of consecutive memory addresses. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the D bit, the CRd field, and in the Unindexed addressing mode only, the imm8 field. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid STC and STC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, the permitted STC access to a system control register can be trapped to Hyp mode, meaning that an attempt to execute an STC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Trapping general CP14 accesses to debug registers on page B1-1260. Note For simplicity, the STC pseudocode does not show this possible trap to Hyp mode. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 584 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 585 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 586 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 587 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm stc cp direct_CRd maccess option - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 588 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 589 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 590 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 591 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm stc cp direct_CRd maccess option - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 592 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 593 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 594 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 595 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm stc cp direct_CRd maccess option - - } - -} - -@encoding (A2) { - - @word 1 1 1 1 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) CRd(4) coproc(4) imm8(8) - - @syntax { - - @subid 596 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 597 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 598 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm stc cp direct_CRd maccess - - } - - @syntax { - - @subid 599 - - @assert { - - P == 0 - W == 0 - U == 1 - - } - - @conv { - - cp = CoProcessor(coproc) - direct_CRd = UInt(CRd) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - option = ZeroExtend(imm8:'00', 32) - - } - - @asm stc cp direct_CRd maccess option - - } - -} - diff --git a/plugins/arm/v7/opdefs/stm_A88199.d b/plugins/arm/v7/opdefs/stm_A88199.d deleted file mode 100644 index 0b519e6..0000000 --- a/plugins/arm/v7/opdefs/stm_A88199.d +++ /dev/null @@ -1,111 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STM (STMIA, STMEA) - -@id 198 - -@desc { - - Store Multiple Increment After (Store Multiple Empty Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start at this address, and the address just above the last of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. - -} - -@encoding (t1) { - - @half 1 1 0 0 0 Rn(3) register_list(8) - - @syntax { - - @subid 600 - - @conv { - - reg_N = Register(Rn) - wb_reg = UncheckedWrittenBackReg(reg_N) - registers = RegList('00000000':register_list) - - } - - @asm stm wb_reg registers - - } - - @hooks { - - fetch = apply_write_back - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 0 0 1 0 W(1) 0 Rn(4) 0 M(1) 0 register_list(13) - - @syntax { - - @subid 601 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList('0':M:'0':register_list) - - } - - @asm stm.w wb_reg registers - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 0 1 0 W(1) 0 Rn(4) register_list(16) - - @syntax { - - @subid 602 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm stm wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/stmda_A88200.d b/plugins/arm/v7/opdefs/stmda_A88200.d deleted file mode 100644 index 8515c74..0000000 --- a/plugins/arm/v7/opdefs/stmda_A88200.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STMDA (STMED) - -@id 199 - -@desc { - - Store Multiple Decrement After (Store Multiple Empty Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end at this address, and the address just below the lowest of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 0 0 0 W(1) 0 Rn(4) register_list(16) - - @syntax { - - @subid 603 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm stmda wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/stmdb_A88201.d b/plugins/arm/v7/opdefs/stmdb_A88201.d deleted file mode 100644 index 52d7bfb..0000000 --- a/plugins/arm/v7/opdefs/stmdb_A88201.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STMDB (STMFD) - -@id 200 - -@desc { - - Store Multiple Decrement Before (Store Multiple Full Descending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations end just below this address, and the address of the first of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 1 0 0 W(1) 0 Rn(4) 0 M(1) 0 register_list(13) - - @syntax { - - @subid 604 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList('0':M:'0':register_list) - - } - - @asm stmdb wb_reg registers - - } - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 1 0 0 W(1) 0 Rn(4) register_list(16) - - @syntax { - - @subid 605 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm stmdb wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/stmib_A88202.d b/plugins/arm/v7/opdefs/stmib_A88202.d deleted file mode 100644 index 9ce1840..0000000 --- a/plugins/arm/v7/opdefs/stmib_A88202.d +++ /dev/null @@ -1,61 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STMIB (STMFA) - -@id 201 - -@desc { - - Store Multiple Increment Before (Store Multiple Full Ascending) stores multiple registers to consecutive memory locations using an address from a base register. The consecutive memory locations start just above this address, and the address of the last of those locations can optionally be written back to the base register. For details of related system instructions see STM (User registers) on page B9-2006. - -} - -@encoding (A1) { - - @word cond(4) 1 0 0 1 1 0 W(1) 0 Rn(4) register_list(16) - - @syntax { - - @subid 606 - - @conv { - - reg_N = Register(Rn) - wb_reg = WrittenBackReg(reg_N, W) - registers = RegList(register_list) - - } - - @asm stmib wb_reg registers - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/str_A88203.d deleted file mode 100644 index 591641b..0000000 --- a/plugins/arm/v7/opdefs/str_A88203.d +++ /dev/null @@ -1,180 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STR (immediate, Thumb) - -@id 202 - -@desc { - - Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) - - @syntax { - - @subid 607 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm str reg_T maccess - - } - -} - -@encoding (t2) { - - @half 1 0 0 1 0 Rt(3) imm8(8) - - @syntax { - - @subid 608 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(13) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm str reg_T maccess - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 609 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm str.w reg_T maccess - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 610 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm str reg_T maccess - - } - - @syntax { - - @subid 611 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm str reg_T maccess - - } - - @syntax { - - @subid 612 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm str reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/str_A88204.d b/plugins/arm/v7/opdefs/str_A88204.d deleted file mode 100644 index 6182de8..0000000 --- a/plugins/arm/v7/opdefs/str_A88204.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STR (immediate, ARM) - -@id 203 - -@desc { - - Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 613 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm str reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 614 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm str reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 615 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm str reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/str_A88205.d deleted file mode 100644 index cbc9f78..0000000 --- a/plugins/arm/v7/opdefs/str_A88205.d +++ /dev/null @@ -1,179 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STR (register) - -@id 204 - -@desc { - - Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 616 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm str reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 617 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm str.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 618 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm str reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 619 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) - - } - - @asm str reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 620 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm str reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strb_A88206.d b/plugins/arm/v7/opdefs/strb_A88206.d deleted file mode 100644 index cb7b74a..0000000 --- a/plugins/arm/v7/opdefs/strb_A88206.d +++ /dev/null @@ -1,157 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRB (immediate, Thumb) - -@id 205 - -@desc { - - Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 1 1 0 imm5(5) Rn(3) Rt(3) - - @syntax { - - @subid 621 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strb reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 0 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 622 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strb.w reg_T maccess - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 623 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strb reg_T maccess - - } - - @syntax { - - @subid 624 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm strb reg_T maccess - - } - - @syntax { - - @subid 625 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strb reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/strb_A88207.d b/plugins/arm/v7/opdefs/strb_A88207.d deleted file mode 100644 index 3ee78b9..0000000 --- a/plugins/arm/v7/opdefs/strb_A88207.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRB (immediate, ARM) - -@id 206 - -@desc { - - Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 626 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 627 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm strb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 628 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strb_A88208.d b/plugins/arm/v7/opdefs/strb_A88208.d deleted file mode 100644 index 8ecc962..0000000 --- a/plugins/arm/v7/opdefs/strb_A88208.d +++ /dev/null @@ -1,179 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRB (register) - -@id 207 - -@desc { - - Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 629 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm strb reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 630 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm strb.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 631 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm strb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 632 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) - - } - - @asm strb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 633 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm strb reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strbt_A88209.d b/plugins/arm/v7/opdefs/strbt_A88209.d deleted file mode 100644 index ac91408..0000000 --- a/plugins/arm/v7/opdefs/strbt_A88209.d +++ /dev/null @@ -1,115 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRBT - -@id 208 - -@desc { - - Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 634 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strbt reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 635 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strbt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 636 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm strbt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strd_A88210.d b/plugins/arm/v7/opdefs/strd_A88210.d deleted file mode 100644 index 83e7af7..0000000 --- a/plugins/arm/v7/opdefs/strd_A88210.d +++ /dev/null @@ -1,213 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRD (immediate) - -@id 209 - -@desc { - - Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) - - @syntax { - - @subid 637 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strd reg_T reg_T2 maccess - - } - - @syntax { - - @subid 638 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm strd reg_T reg_T2 maccess - - } - - @syntax { - - @subid 639 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strd reg_T reg_T2 maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - - @syntax { - - @subid 640 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 641 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 642 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/strd_A88211.d deleted file mode 100644 index 817d2f1..0000000 --- a/plugins/arm/v7/opdefs/strd_A88211.d +++ /dev/null @@ -1,132 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRD (register) - -@id 210 - -@desc { - - Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax { - - @subid 643 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 644 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 645 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/strex_A88212.d deleted file mode 100644 index 8a3ab87..0000000 --- a/plugins/arm/v7/opdefs/strex_A88212.d +++ /dev/null @@ -1,87 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STREX - -@id 211 - -@desc { - - Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) - - @syntax { - - @subid 646 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strex reg_D reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax { - - @subid 647 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = Zeros(32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strex reg_D reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strexb_A88213.d b/plugins/arm/v7/opdefs/strexb_A88213.d deleted file mode 100644 index 45ec2f2..0000000 --- a/plugins/arm/v7/opdefs/strexb_A88213.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STREXB - -@id 212 - -@desc { - - Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) - - @syntax { - - @subid 648 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm strexb reg_D reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax { - - @subid 649 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm strexb reg_D reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strexd_A88214.d b/plugins/arm/v7/opdefs/strexd_A88214.d deleted file mode 100644 index ec1f4f6..0000000 --- a/plugins/arm/v7/opdefs/strexd_A88214.d +++ /dev/null @@ -1,87 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STREXD - -@id 213 - -@desc { - - Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) - - @syntax { - - @subid 650 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm strexd reg_D reg_T reg_T2 maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax { - - @subid 651 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm strexd reg_D reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strexh_A88215.d b/plugins/arm/v7/opdefs/strexh_A88215.d deleted file mode 100644 index 6ca68ce..0000000 --- a/plugins/arm/v7/opdefs/strexh_A88215.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STREXH - -@id 214 - -@desc { - - Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) - - @syntax { - - @subid 652 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm strexh reg_D reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - - @syntax { - - @subid 653 - - @conv { - - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm strexh reg_D reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strh_A88216.d b/plugins/arm/v7/opdefs/strh_A88216.d deleted file mode 100644 index fadbcbe..0000000 --- a/plugins/arm/v7/opdefs/strh_A88216.d +++ /dev/null @@ -1,157 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRH (immediate, Thumb) - -@id 215 - -@desc { - - Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) - - @syntax { - - @subid 654 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strh reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 655 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strh.w reg_T maccess - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - - @syntax { - - @subid 656 - - @assert { - - P == 1 - W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strh reg_T maccess - - } - - @syntax { - - @subid 657 - - @assert { - - P == 1 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm strh reg_T maccess - - } - - @syntax { - - @subid 658 - - @assert { - - P == 0 - W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strh reg_T maccess - - } - -} - diff --git a/plugins/arm/v7/opdefs/strh_A88217.d b/plugins/arm/v7/opdefs/strh_A88217.d deleted file mode 100644 index 76fc365..0000000 --- a/plugins/arm/v7/opdefs/strh_A88217.d +++ /dev/null @@ -1,129 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRH (immediate, ARM) - -@id 216 - -@desc { - - Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax { - - @subid 659 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 660 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPreIndexed(reg_N, imm32) - - } - - @asm strh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 661 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/strh_A88218.d deleted file mode 100644 index 0d222a8..0000000 --- a/plugins/arm/v7/opdefs/strh_A88218.d +++ /dev/null @@ -1,176 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRH (register) - -@id 217 - -@desc { - - Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (t1) { - - @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) - - @syntax { - - @subid 662 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm strh reg_T maccess - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - - @syntax { - - @subid 663 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = FixedShift(SRType_LSL, imm2) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm strh.w reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax { - - @subid 664 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm strh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 665 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm strh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 666 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm strh reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strht_A88219.d b/plugins/arm/v7/opdefs/strht_A88219.d deleted file mode 100644 index a15db3a..0000000 --- a/plugins/arm/v7/opdefs/strht_A88219.d +++ /dev/null @@ -1,114 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRHT - -@id 218 - -@desc { - - Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 667 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strht reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - - @syntax { - - @subid 668 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strht reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - - @syntax { - - @subid 669 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm strht reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/strt_A88220.d b/plugins/arm/v7/opdefs/strt_A88220.d deleted file mode 100644 index 0750a0d..0000000 --- a/plugins/arm/v7/opdefs/strt_A88220.d +++ /dev/null @@ -1,115 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title STRT - -@id 219 - -@desc { - - Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - - @syntax { - - @subid 670 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - maccess = MemAccessOffset(reg_N, imm32) - - } - - @asm strt reg_T maccess - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) - - @syntax { - - @subid 671 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - maccess = MemAccessPostIndexed(reg_N, imm32) - - } - - @asm strt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - -@encoding (A2) { - - @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 672 - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm strt reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/sub_A88221.d deleted file mode 100644 index 30ccb68..0000000 --- a/plugins/arm/v7/opdefs/sub_A88221.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SUB (immediate, Thumb) - -@id 220 - -@desc { - - This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) - - @syntax { - - @subid 673 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) - - } - - @asm sub ?reg_D reg_N imm32 - - } - -} - -@encoding (t2) { - - @half 0 0 1 1 1 Rdn(3) imm8(8) - - @syntax { - - @subid 674 - - @conv { - - reg_D = Register(Rdn) - reg_N = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) - - } - - @asm sub ?reg_D reg_N imm32 - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 675 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm sub.w ?reg_D reg_N imm32 - - } - - @syntax { - - @subid 676 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm subs.w ?reg_D reg_N imm32 - - } - -} - -@encoding (T4) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 677 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - - @asm subw ?reg_D reg_N imm32 - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/sub_A88222.d deleted file mode 100644 index 74bb4e0..0000000 --- a/plugins/arm/v7/opdefs/sub_A88222.d +++ /dev/null @@ -1,95 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SUB (immediate, ARM) - -@id 221 - -@desc { - - This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) - - @syntax { - - @subid 678 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm sub ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 679 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) - - } - - @asm subs ?reg_D reg_N imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88223.d b/plugins/arm/v7/opdefs/sub_A88223.d deleted file mode 100644 index 1498889..0000000 --- a/plugins/arm/v7/opdefs/sub_A88223.d +++ /dev/null @@ -1,171 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SUB (register) - -@id 222 - -@desc { - - This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3) - - @syntax { - - @subid 680 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm sub ?reg_D reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 681 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm sub.w ?reg_D reg_N reg_M ?shift - - } - - @syntax { - - @subid 682 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm subs.w ?reg_D reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 683 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm sub ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 684 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm subs ?reg_D reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/plugins/arm/v7/opdefs/sub_A88224.d deleted file mode 100644 index e52e818..0000000 --- a/plugins/arm/v7/opdefs/sub_A88224.d +++ /dev/null @@ -1,101 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SUB (register-shifted register) - -@id 223 - -@desc { - - This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 685 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm sub ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 686 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm subs ?reg_D reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/sub_A88225.d deleted file mode 100644 index 3248f19..0000000 --- a/plugins/arm/v7/opdefs/sub_A88225.d +++ /dev/null @@ -1,189 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SUB (SP minus immediate) - -@id 224 - -@desc { - - This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 0 0 0 1 imm7(7) - - @syntax { - - @subid 687 - - @conv { - - reg_D = Register(13) - reg_SP = Register(13) - imm32 = ZeroExtend(imm7:'00', 32) - - } - - @asm sub ?reg_D reg_SP imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 688 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm sub.w ?reg_D reg_SP imm32 - - } - - @syntax { - - @subid 689 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ThumbExpandImm(i:imm3:imm8) - - } - - @asm subs.w ?reg_D reg_SP imm32 - - } - -} - -@encoding (T3) { - - @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - - @syntax { - - @subid 690 - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ZeroExtend(i:imm3:imm8, 32) - - } - - @asm subw ?reg_D reg_SP imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) - - @syntax { - - @subid 691 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ARMExpandImm(imm12) - - } - - @asm sub ?reg_D reg_SP imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 692 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - imm32 = ARMExpandImm(imm12) - - } - - @asm subs ?reg_D reg_SP imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d deleted file mode 100644 index cdbd277..0000000 --- a/plugins/arm/v7/opdefs/sub_A88226.d +++ /dev/null @@ -1,149 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SUB (SP minus register) - -@id 225 - -@desc { - - This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 693 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm sub ?reg_D reg_SP reg_M ?shift - - } - - @syntax { - - @subid 694 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm subs ?reg_D reg_SP reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 695 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm sub ?reg_D reg_SP reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 696 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_SP = Register(13) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm subs ?reg_D reg_SP reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/svc_A88228.d deleted file mode 100644 index d9f709e..0000000 --- a/plugins/arm/v7/opdefs/svc_A88228.d +++ /dev/null @@ -1,79 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SVC (previously SWI) - -@id 227 - -@desc { - - Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. - -} - -@encoding (t1) { - - @half 1 1 0 1 1 1 1 1 imm8(8) - - @syntax { - - @subid 697 - - @conv { - - imm32 = ZeroExtend(imm8, 32) - - } - - @asm svc imm32 - - } - -} - -@encoding (A1) { - - @word cond(4) 1 1 1 1 imm24(24) - - @syntax { - - @subid 698 - - @conv { - - imm32 = ZeroExtend(imm24, 32) - - } - - @asm svc imm32 - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/swp_A88229.d b/plugins/arm/v7/opdefs/swp_A88229.d deleted file mode 100644 index 09a8110..0000000 --- a/plugins/arm/v7/opdefs/swp_A88229.d +++ /dev/null @@ -1,97 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SWP, SWPB - -@id 228 - -@desc { - - SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register . The value of register is then stored to the memory address given by the value of , and the original loaded value is written to register . If the same register is specified for and , this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register . The value of the least significant byte of register is stored to the memory address given by , the original loaded value is zero-extended to a 32-bit word, and the word is written to register . If the same register is specified for and , this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — — LDREXB/STREXB in preference to SWPB. • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 B(1) 0 0 Rn(4) Rt(4) 0 0 0 0 1 0 0 1 Rt2(4) - - @syntax { - - @subid 699 - - @assert { - - B == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm swp reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 700 - - @assert { - - B == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - maccess = MemAccessOffset(reg_N, NULL) - - } - - @asm swpb reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sxtab16_A88231.d b/plugins/arm/v7/opdefs/sxtab16_A88231.d deleted file mode 100644 index f60a624..0000000 --- a/plugins/arm/v7/opdefs/sxtab16_A88231.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SXTAB16 - -@id 230 - -@desc { - - Signed Extend and Add Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 703 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtab16 ?reg_D reg_N reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 704 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtab16 ?reg_D reg_N reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sxtab_A88230.d b/plugins/arm/v7/opdefs/sxtab_A88230.d deleted file mode 100644 index ccd1859..0000000 --- a/plugins/arm/v7/opdefs/sxtab_A88230.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SXTAB - -@id 229 - -@desc { - - Signed Extend and Add Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 1 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 701 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtab ?reg_D reg_N reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 702 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtab ?reg_D reg_N reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sxtah_A88232.d b/plugins/arm/v7/opdefs/sxtah_A88232.d deleted file mode 100644 index e1d4135..0000000 --- a/plugins/arm/v7/opdefs/sxtah_A88232.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SXTAH - -@id 231 - -@desc { - - Signed Extend and Add Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 705 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtah ?reg_D reg_N reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 706 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtah ?reg_D reg_N reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sxtb16_A88234.d b/plugins/arm/v7/opdefs/sxtb16_A88234.d deleted file mode 100644 index fe9fb17..0000000 --- a/plugins/arm/v7/opdefs/sxtb16_A88234.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SXTB16 - -@id 233 - -@desc { - - Signed Extend Byte 16 extracts two 8-bit values from a register, sign-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 710 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtb16 ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 711 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtb16 ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sxtb_A88233.d b/plugins/arm/v7/opdefs/sxtb_A88233.d deleted file mode 100644 index 99b43c0..0000000 --- a/plugins/arm/v7/opdefs/sxtb_A88233.d +++ /dev/null @@ -1,105 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SXTB - -@id 232 - -@desc { - - Signed Extend Byte extracts an 8-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 0 1 0 0 1 Rm(3) Rd(3) - - @syntax { - - @subid 707 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(0) - - } - - @asm sxtb ?reg_D reg_M ?rotation - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 0 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 708 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtb.w ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 709 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxtb ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/sxth_A88235.d b/plugins/arm/v7/opdefs/sxth_A88235.d deleted file mode 100644 index 76e09d2..0000000 --- a/plugins/arm/v7/opdefs/sxth_A88235.d +++ /dev/null @@ -1,105 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title SXTH - -@id 234 - -@desc { - - Signed Extend Halfword extracts a 16-bit value from a register, sign-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 0 1 0 0 0 Rm(3) Rd(3) - - @syntax { - - @subid 712 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(0) - - } - - @asm sxth ?reg_D reg_M ?rotation - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 713 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxth.w ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 714 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm sxth ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/teq_A88237.d b/plugins/arm/v7/opdefs/teq_A88237.d deleted file mode 100644 index 9972918..0000000 --- a/plugins/arm/v7/opdefs/teq_A88237.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title TEQ (immediate) - -@id 236 - -@desc { - - Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax { - - @subid 715 - - @conv { - - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm teq reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax { - - @subid 716 - - @conv { - - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm teq reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/teq_A88238.d deleted file mode 100644 index def4bc4..0000000 --- a/plugins/arm/v7/opdefs/teq_A88238.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title TEQ (register) - -@id 237 - -@desc { - - Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax { - - @subid 717 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm teq reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 718 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm teq reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/teq_A88239.d deleted file mode 100644 index 3c6ab33..0000000 --- a/plugins/arm/v7/opdefs/teq_A88239.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title TEQ (register-shifted register) - -@id 238 - -@desc { - - Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 719 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm teq reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/tst_A88240.d deleted file mode 100644 index 125febc..0000000 --- a/plugins/arm/v7/opdefs/tst_A88240.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title TST (immediate) - -@id 239 - -@desc { - - Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - - @syntax { - - @subid 720 - - @conv { - - reg_N = Register(Rn) - const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - - } - - @asm tst reg_N const - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) - - @syntax { - - @subid 721 - - @conv { - - reg_N = Register(Rn) - const = ARMExpandImm_C(imm12, APSR_C) - - } - - @asm tst reg_N const - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/tst_A88241.d b/plugins/arm/v7/opdefs/tst_A88241.d deleted file mode 100644 index 1be33f8..0000000 --- a/plugins/arm/v7/opdefs/tst_A88241.d +++ /dev/null @@ -1,104 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title TST (register) - -@id 240 - -@desc { - - Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) - - @syntax { - - @subid 722 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm tst reg_N reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - - @syntax { - - @subid 723 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm tst.w reg_N reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 724 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm tst reg_N reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/tst_A88242.d deleted file mode 100644 index 04bfdd2..0000000 --- a/plugins/arm/v7/opdefs/tst_A88242.d +++ /dev/null @@ -1,63 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title TST (register-shifted register) - -@id 241 - -@desc { - - Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - - @syntax { - - @subid 725 - - @conv { - - reg_N = Register(Rn) - reg_M = Register(Rm) - shift_t = UInt(type) - reg_S = Register(Rs) - shift = BuildRegShift(shift_t, reg_S) - - } - - @asm tst reg_N reg_M shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uadd16_A88243.d b/plugins/arm/v7/opdefs/uadd16_A88243.d deleted file mode 100644 index ba9ad7a..0000000 --- a/plugins/arm/v7/opdefs/uadd16_A88243.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UADD16 - -@id 242 - -@desc { - - Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax { - - @subid 726 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uadd16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 727 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uadd16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uadd8_A88244.d b/plugins/arm/v7/opdefs/uadd8_A88244.d deleted file mode 100644 index bf8e18d..0000000 --- a/plugins/arm/v7/opdefs/uadd8_A88244.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UADD8 - -@id 243 - -@desc { - - Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax { - - @subid 728 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uadd8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax { - - @subid 729 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uadd8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uasx_A88245.d b/plugins/arm/v7/opdefs/uasx_A88245.d deleted file mode 100644 index b802f43..0000000 --- a/plugins/arm/v7/opdefs/uasx_A88245.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UASX - -@id 244 - -@desc { - - Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax { - - @subid 730 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uasx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 731 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uasx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/ubfx_A88246.d deleted file mode 100644 index 3fe25c7..0000000 --- a/plugins/arm/v7/opdefs/ubfx_A88246.d +++ /dev/null @@ -1,87 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UBFX - -@id 245 - -@desc { - - Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - - @syntax { - - @subid 732 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - widthminus1 = UInt(widthm1) - width = MinusBitDiff(widthminus1, lsbit) - - } - - @asm ubfx reg_D reg_N lsbit width - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - - @syntax { - - @subid 733 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - widthminus1 = UInt(widthm1) - width = MinusBitDiff(widthminus1, lsbit) - - } - - @asm ubfx reg_D reg_N lsbit width - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/udf_A88247.d b/plugins/arm/v7/opdefs/udf_A88247.d deleted file mode 100644 index 500e714..0000000 --- a/plugins/arm/v7/opdefs/udf_A88247.d +++ /dev/null @@ -1,93 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UDF - -@id 246 - -@desc { - - Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. - -} - -@encoding (t1) { - - @half 1 1 0 1 1 1 1 0 imm8(8) - - @syntax { - - @subid 734 - - @conv { - - imm32 = ZeroExtend(imm8, 32) - - } - - @asm udf imm32 - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 1 0 imm12(12) - - @syntax { - - @subid 735 - - @conv { - - imm32 = ZeroExtend(imm4:imm12, 32) - - } - - @asm udf.w imm32 - - } - -} - -@encoding (A1) { - - @word 1 1 1 0 0 1 1 1 1 1 1 1 imm12(12) 1 1 1 1 imm4(4) - - @syntax { - - @subid 736 - - @conv { - - imm32 = ZeroExtend(imm12:imm4, 32) - - } - - @asm udf imm32 - - } - -} - diff --git a/plugins/arm/v7/opdefs/udiv_A88248.d b/plugins/arm/v7/opdefs/udiv_A88248.d deleted file mode 100644 index 27ef02b..0000000 --- a/plugins/arm/v7/opdefs/udiv_A88248.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UDIV - -@id 247 - -@desc { - - Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - - @syntax { - - @subid 737 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm udiv ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 0 0 1 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - - @syntax { - - @subid 738 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm udiv ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uhadd16_A88249.d b/plugins/arm/v7/opdefs/uhadd16_A88249.d deleted file mode 100644 index 379b0e9..0000000 --- a/plugins/arm/v7/opdefs/uhadd16_A88249.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UHADD16 - -@id 248 - -@desc { - - Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 739 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhadd16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 740 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhadd16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uhadd8_A88250.d b/plugins/arm/v7/opdefs/uhadd8_A88250.d deleted file mode 100644 index 1f4a626..0000000 --- a/plugins/arm/v7/opdefs/uhadd8_A88250.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UHADD8 - -@id 249 - -@desc { - - Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 741 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhadd8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax { - - @subid 742 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhadd8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uhasx_A88251.d b/plugins/arm/v7/opdefs/uhasx_A88251.d deleted file mode 100644 index 148d120..0000000 --- a/plugins/arm/v7/opdefs/uhasx_A88251.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UHASX - -@id 250 - -@desc { - - Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 743 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhasx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 744 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhasx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uhsax_A88252.d b/plugins/arm/v7/opdefs/uhsax_A88252.d deleted file mode 100644 index eb7dd83..0000000 --- a/plugins/arm/v7/opdefs/uhsax_A88252.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UHSAX - -@id 251 - -@desc { - - Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 745 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhsax ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax { - - @subid 746 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhsax ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uhsub16_A88253.d b/plugins/arm/v7/opdefs/uhsub16_A88253.d deleted file mode 100644 index f526389..0000000 --- a/plugins/arm/v7/opdefs/uhsub16_A88253.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UHSUB16 - -@id 252 - -@desc { - - Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 747 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhsub16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax { - - @subid 748 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhsub16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uhsub8_A88254.d b/plugins/arm/v7/opdefs/uhsub8_A88254.d deleted file mode 100644 index a2d27ac..0000000 --- a/plugins/arm/v7/opdefs/uhsub8_A88254.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UHSUB8 - -@id 253 - -@desc { - - Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 749 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhsub8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax { - - @subid 750 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uhsub8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/umaal_A88255.d b/plugins/arm/v7/opdefs/umaal_A88255.d deleted file mode 100644 index 6e5f7e9..0000000 --- a/plugins/arm/v7/opdefs/umaal_A88255.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UMAAL - -@id 254 - -@desc { - - Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 1 1 0 Rm(4) - - @syntax { - - @subid 751 - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umaal reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 752 - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umaal reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/umlal_A88256.d b/plugins/arm/v7/opdefs/umlal_A88256.d deleted file mode 100644 index 0eccc37..0000000 --- a/plugins/arm/v7/opdefs/umlal_A88256.d +++ /dev/null @@ -1,120 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UMLAL - -@id 255 - -@desc { - - Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 753 - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umlal reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 754 - - @assert { - - S == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umlal reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 755 - - @assert { - - S == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umlals reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/umull_A88257.d b/plugins/arm/v7/opdefs/umull_A88257.d deleted file mode 100644 index b016016..0000000 --- a/plugins/arm/v7/opdefs/umull_A88257.d +++ /dev/null @@ -1,120 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UMULL - -@id 256 - -@desc { - - Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 1 0 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 756 - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umull reg_DLO reg_DHI reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 1 0 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - - @syntax { - - @subid 757 - - @assert { - - S == 0 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umull reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 758 - - @assert { - - S == 1 - - } - - @conv { - - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm umulls reg_DLO reg_DHI reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uqadd16_A88258.d b/plugins/arm/v7/opdefs/uqadd16_A88258.d deleted file mode 100644 index ed4c130..0000000 --- a/plugins/arm/v7/opdefs/uqadd16_A88258.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UQADD16 - -@id 257 - -@desc { - - Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax { - - @subid 759 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqadd16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - - @syntax { - - @subid 760 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqadd16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uqadd8_A88259.d b/plugins/arm/v7/opdefs/uqadd8_A88259.d deleted file mode 100644 index ca6054d..0000000 --- a/plugins/arm/v7/opdefs/uqadd8_A88259.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UQADD8 - -@id 258 - -@desc { - - Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax { - - @subid 761 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqadd8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - - @syntax { - - @subid 762 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqadd8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/uqasx_A88260.d deleted file mode 100644 index 12930a2..0000000 --- a/plugins/arm/v7/opdefs/uqasx_A88260.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UQASX - -@id 259 - -@desc { - - Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax { - - @subid 763 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqasx ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - - @syntax { - - @subid 764 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqasx ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uqsax_A88261.d b/plugins/arm/v7/opdefs/uqsax_A88261.d deleted file mode 100644 index d39f0f4..0000000 --- a/plugins/arm/v7/opdefs/uqsax_A88261.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UQSAX - -@id 260 - -@desc { - - Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax { - - @subid 765 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqsax ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax { - - @subid 766 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqsax ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uqsub16_A88262.d b/plugins/arm/v7/opdefs/uqsub16_A88262.d deleted file mode 100644 index cd77b0a..0000000 --- a/plugins/arm/v7/opdefs/uqsub16_A88262.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UQSUB16 - -@id 261 - -@desc { - - Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax { - - @subid 767 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqsub16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax { - - @subid 768 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqsub16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uqsub8_A88263.d b/plugins/arm/v7/opdefs/uqsub8_A88263.d deleted file mode 100644 index aa42724..0000000 --- a/plugins/arm/v7/opdefs/uqsub8_A88263.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UQSUB8 - -@id 262 - -@desc { - - Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - - @syntax { - - @subid 769 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqsub8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax { - - @subid 770 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm uqsub8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usad8_A88264.d b/plugins/arm/v7/opdefs/usad8_A88264.d deleted file mode 100644 index 286ba2c..0000000 --- a/plugins/arm/v7/opdefs/usad8_A88264.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USAD8 - -@id 263 - -@desc { - - Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 771 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usad8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - - @syntax { - - @subid 772 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usad8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usada8_A88265.d b/plugins/arm/v7/opdefs/usada8_A88265.d deleted file mode 100644 index bce78eb..0000000 --- a/plugins/arm/v7/opdefs/usada8_A88265.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USADA8 - -@id 264 - -@desc { - - Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - - @syntax { - - @subid 773 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm usada8 reg_D reg_N reg_M reg_A - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 0 1 Rn(4) - - @syntax { - - @subid 774 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - - } - - @asm usada8 reg_D reg_N reg_M reg_A - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usat16_A88267.d b/plugins/arm/v7/opdefs/usat16_A88267.d deleted file mode 100644 index d36f52f..0000000 --- a/plugins/arm/v7/opdefs/usat16_A88267.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USAT16 - -@id 266 - -@desc { - - Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) - - @syntax { - - @subid 777 - - @conv { - - reg_D = Register(Rd) - saturate_to = UInt(sat_imm) - reg_N = Register(Rn) - - } - - @asm usat16 reg_D saturate_to reg_N - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) - - @syntax { - - @subid 778 - - @conv { - - reg_D = Register(Rd) - saturate_to = UInt(sat_imm) - reg_N = Register(Rn) - - } - - @asm usat16 reg_D saturate_to reg_N - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usat_A88266.d b/plugins/arm/v7/opdefs/usat_A88266.d deleted file mode 100644 index d2a2819..0000000 --- a/plugins/arm/v7/opdefs/usat_A88266.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USAT - -@id 265 - -@desc { - - Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. - -} - -@encoding (T1) { - - @word 1 1 1 1 0 0 1 1 1 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) - - @syntax { - - @subid 775 - - @conv { - - reg_D = Register(Rd) - saturate_to = UInt(sat_imm) - reg_N = Register(Rn) - shift = DecodeImmShift(sh:'0', imm3:imm2) - - } - - @asm usat reg_D saturate_to reg_N ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) - - @syntax { - - @subid 776 - - @conv { - - reg_D = Register(Rd) - saturate_to = UInt(sat_imm) - reg_N = Register(Rn) - shift = DecodeImmShift(sh:'0', imm5) - - } - - @asm usat reg_D saturate_to reg_N ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usax_A88268.d b/plugins/arm/v7/opdefs/usax_A88268.d deleted file mode 100644 index d85083c..0000000 --- a/plugins/arm/v7/opdefs/usax_A88268.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USAX - -@id 267 - -@desc { - - Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax { - - @subid 779 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usax ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - - @syntax { - - @subid 780 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usax ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usub16_A88269.d b/plugins/arm/v7/opdefs/usub16_A88269.d deleted file mode 100644 index 6a9a2f5..0000000 --- a/plugins/arm/v7/opdefs/usub16_A88269.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USUB16 - -@id 268 - -@desc { - - Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax { - - @subid 781 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usub16 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - - @syntax { - - @subid 782 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usub16 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/usub8_A88270.d b/plugins/arm/v7/opdefs/usub8_A88270.d deleted file mode 100644 index 2987469..0000000 --- a/plugins/arm/v7/opdefs/usub8_A88270.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title USUB8 - -@id 269 - -@desc { - - Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - - @syntax { - - @subid 783 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usub8 ?reg_D reg_N reg_M - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - - @syntax { - - @subid 784 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - - } - - @asm usub8 ?reg_D reg_N reg_M - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uxtab16_A88272.d b/plugins/arm/v7/opdefs/uxtab16_A88272.d deleted file mode 100644 index 0cbc980..0000000 --- a/plugins/arm/v7/opdefs/uxtab16_A88272.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UXTAB16 - -@id 271 - -@desc { - - Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 787 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtab16 ?reg_D reg_N reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 788 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtab16 ?reg_D reg_N reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uxtab_A88271.d b/plugins/arm/v7/opdefs/uxtab_A88271.d deleted file mode 100644 index 104d379..0000000 --- a/plugins/arm/v7/opdefs/uxtab_A88271.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UXTAB - -@id 270 - -@desc { - - Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 785 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtab ?reg_D reg_N reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 786 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtab ?reg_D reg_N reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uxtah_A88273.d b/plugins/arm/v7/opdefs/uxtah_A88273.d deleted file mode 100644 index 9e454ac..0000000 --- a/plugins/arm/v7/opdefs/uxtah_A88273.d +++ /dev/null @@ -1,85 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UXTAH - -@id 272 - -@desc { - - Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 789 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtah ?reg_D reg_N reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 790 - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtah ?reg_D reg_N reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uxtb16_A88275.d b/plugins/arm/v7/opdefs/uxtb16_A88275.d deleted file mode 100644 index 5d67eb8..0000000 --- a/plugins/arm/v7/opdefs/uxtb16_A88275.d +++ /dev/null @@ -1,83 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UXTB16 - -@id 274 - -@desc { - - Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. - -} - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 794 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtb16 ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 795 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtb16 ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uxtb_A88274.d b/plugins/arm/v7/opdefs/uxtb_A88274.d deleted file mode 100644 index 0ac40b6..0000000 --- a/plugins/arm/v7/opdefs/uxtb_A88274.d +++ /dev/null @@ -1,105 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UXTB - -@id 273 - -@desc { - - Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 0 1 0 1 1 Rm(3) Rd(3) - - @syntax { - - @subid 791 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(0) - - } - - @asm uxtb ?reg_D reg_M ?rotation - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 792 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtb.w ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 793 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxtb ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/uxth_A88276.d deleted file mode 100644 index 3ebf512..0000000 --- a/plugins/arm/v7/opdefs/uxth_A88276.d +++ /dev/null @@ -1,105 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title UXTH - -@id 275 - -@desc { - - Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. - -} - -@encoding (t1) { - - @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) - - @syntax { - - @subid 796 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(0) - - } - - @asm uxth ?reg_D reg_M ?rotation - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax { - - @subid 797 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxth.w ?reg_D reg_M ?rotation - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax { - - @subid 798 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @asm uxth ?reg_D reg_M ?rotation - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/wfe_A88424.d b/plugins/arm/v7/opdefs/wfe_A88424.d deleted file mode 100644 index dc0f72e..0000000 --- a/plugins/arm/v7/opdefs/wfe_A88424.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title WFE - -@id 423 - -@desc { - - Wait For Event is a hint instruction that permits the processor to enter a low-power state until one of a number of events occurs, including events signaled by executing the SEV instruction on any processor in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. In an implementation that includes the Virtualization Extensions, if HCR.TWE is set to 1, execution of a WFE instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWE bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 1 0 0 0 0 0 - - @syntax { - - @subid 1979 - - @asm wfe - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 - - @syntax { - - @subid 1980 - - @asm wfe.w - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 0 - - @syntax { - - @subid 1981 - - @asm wfe - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/wfi_A88425.d b/plugins/arm/v7/opdefs/wfi_A88425.d deleted file mode 100644 index 961c293..0000000 --- a/plugins/arm/v7/opdefs/wfi_A88425.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title WFI - -@id 424 - -@desc { - - Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 - - @syntax { - - @subid 1982 - - @asm wfi - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 - - @syntax { - - @subid 1983 - - @asm wfi.w - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 - - @syntax { - - @subid 1984 - - @asm wfi - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/opdefs/yield_A88426.d b/plugins/arm/v7/opdefs/yield_A88426.d deleted file mode 100644 index 66e8f39..0000000 --- a/plugins/arm/v7/opdefs/yield_A88426.d +++ /dev/null @@ -1,81 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see . - */ - - -@title YIELD - -@id 425 - -@desc { - - YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. - -} - -@encoding (t1) { - - @half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 - - @syntax { - - @subid 1985 - - @asm yield - - } - -} - -@encoding (T2) { - - @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - - @syntax { - - @subid 1986 - - @asm yield.w - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 - - @syntax { - - @subid 1987 - - @asm yield - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - diff --git a/plugins/arm/v7/operands/Makefile.am b/plugins/arm/v7/operands/Makefile.am index d19db29..ac08569 100644 --- a/plugins/arm/v7/operands/Makefile.am +++ b/plugins/arm/v7/operands/Makefile.am @@ -3,6 +3,7 @@ noinst_LTLIBRARIES = libarmv7operands.la libarmv7operands_la_SOURCES = \ estate.h estate.c \ + iflags.h iflags.c \ it.h it.c \ limitation.h limitation.c \ maccess.h maccess.c \ diff --git a/plugins/arm/v7/operands/iflags.c b/plugins/arm/v7/operands/iflags.c new file mode 100644 index 0000000..e7b1b41 --- /dev/null +++ b/plugins/arm/v7/operands/iflags.c @@ -0,0 +1,337 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * iflags.c - opérandes précisant un masque d'interruption ARMv7 + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +#include "iflags.h" + + +#include + + + +/* Définition d'un opérande précisant un masque d'interruption ARMv7 (instance) */ +struct _GArmV7IFlagsOperand +{ + GArchOperand parent; /* Instance parente */ + + bool abort_bit; /* Interruption d'arrêt async. */ + bool irq_bit; /* Interruption IRQ */ + bool fiq_bit; /* Interruption FIQ */ + +}; + + +/* Définition d'un opérande précisant un masque d'interruption ARMv7 (classe) */ +struct _GArmV7IFlagsOperandClass +{ + GArchOperandClass parent; /* Classe parente */ + +}; + + +/* Initialise la classe des opérandes de masque d'interruption. */ +static void g_armv7_iflags_operand_class_init(GArmV7IFlagsOperandClass *); + +/* Initialise une instance d'opérande de masque d'interruption. */ +static void g_armv7_iflags_operand_init(GArmV7IFlagsOperand *); + +/* Supprime toutes les références externes. */ +static void g_armv7_iflags_operand_dispose(GArmV7IFlagsOperand *); + +/* Procède à la libération totale de la mémoire. */ +static void g_armv7_iflags_operand_finalize(GArmV7IFlagsOperand *); + +/* Traduit un opérande en version humainement lisible. */ +static void g_armv7_iflags_operand_print(const GArmV7IFlagsOperand *, GBufferLine *, AsmSyntax); + + + +/* --------------------- TRANSPOSITIONS VIA CACHE DES OPERANDES --------------------- */ + + +/* Charge un opérande depuis une mémoire tampon. */ +static bool g_armv7_iflags_operand_unserialize(GArmV7IFlagsOperand *, GAsmStorage *, GBinFormat *, packed_buffer *); + +/* Sauvegarde un opérande dans une mémoire tampon. */ +static bool g_armv7_iflags_operand_serialize(const GArmV7IFlagsOperand *, GAsmStorage *, packed_buffer *); + + + +/* Indique le type défini par la GLib pour un opérande de masque d'interruption ARMv7. */ +G_DEFINE_TYPE(GArmV7IFlagsOperand, g_armv7_iflags_operand, G_TYPE_ARCH_OPERAND); + + +/****************************************************************************** +* * +* Paramètres : klass = classe à initialiser. * +* * +* Description : Initialise la classe des opérandes de masque d'interruption. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_iflags_operand_class_init(GArmV7IFlagsOperandClass *klass) +{ + GObjectClass *object; /* Autre version de la classe */ + GArchOperandClass *operand; /* Version de classe parente */ + + object = G_OBJECT_CLASS(klass); + + object->dispose = (GObjectFinalizeFunc/* ! */)g_armv7_iflags_operand_dispose; + object->finalize = (GObjectFinalizeFunc)g_armv7_iflags_operand_finalize; + + operand = G_ARCH_OPERAND_CLASS(klass); + + operand->print = (operand_print_fc)g_armv7_iflags_operand_print; + + operand->unserialize = (unserialize_operand_fc)g_armv7_iflags_operand_unserialize; + operand->serialize = (serialize_operand_fc)g_armv7_iflags_operand_serialize; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance à initialiser. * +* * +* Description : Initialise une instance d'opérande de masque d'interruption. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_iflags_operand_init(GArmV7IFlagsOperand *operand) +{ + operand->abort_bit = false; + operand->irq_bit = false; + operand->fiq_bit = false; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance d'objet GLib à traiter. * +* * +* Description : Supprime toutes les références externes. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_iflags_operand_dispose(GArmV7IFlagsOperand *operand) +{ + G_OBJECT_CLASS(g_armv7_iflags_operand_parent_class)->dispose(G_OBJECT(operand)); + +} + + +/****************************************************************************** +* * +* Paramètres : operand = instance d'objet GLib à traiter. * +* * +* Description : Procède à la libération totale de la mémoire. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_iflags_operand_finalize(GArmV7IFlagsOperand *operand) +{ + G_OBJECT_CLASS(g_armv7_iflags_operand_parent_class)->finalize(G_OBJECT(operand)); + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande à traiter. * +* line = ligne tampon où imprimer l'opérande donné. * +* syntax = type de représentation demandée. * +* * +* Description : Traduit un opérande en version humainement lisible. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_armv7_iflags_operand_print(const GArmV7IFlagsOperand *operand, GBufferLine *line, AsmSyntax syntax) +{ + if (operand->abort_bit) + g_buffer_line_append_text(line, BLC_ASSEMBLY, "A", 1, RTT_REGISTER, NULL); + + if (operand->irq_bit) + g_buffer_line_append_text(line, BLC_ASSEMBLY, "I", 1, RTT_REGISTER, NULL); + + if (operand->fiq_bit) + g_buffer_line_append_text(line, BLC_ASSEMBLY, "F", 1, RTT_REGISTER, NULL); + +} + + +/****************************************************************************** +* * +* Paramètres : a = bit d'arrêt asynchrone. * +* i = bit d'interruption IRQ. * +* f = bit d'interruption FIQ. * +* * +* Description : Crée un opérande de masque d'interruption ARMv7. * +* * +* Retour : Opérande mis en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArchOperand *g_armv7_iflags_operand_new(bool a, bool i, bool f) +{ + GArmV7IFlagsOperand *result; /* Structure à retourner */ + + result = g_object_new(G_TYPE_ARMV7_IFLAGS_OPERAND, NULL); + + result->abort_bit = a; + result->irq_bit = i; + result->fiq_bit = f; + + return G_ARCH_OPERAND(result); + +} + + +/* ---------------------------------------------------------------------------------- */ +/* TRANSPOSITIONS VIA CACHE DES OPERANDES */ +/* ---------------------------------------------------------------------------------- */ + + +/****************************************************************************** +* * +* Paramètres : operand = opérande d'assemblage à constituer. * +* storage = mécanisme de sauvegarde à manipuler. * +* format = format binaire chargé associé à l'architecture. * +* pbuf = zone tampon à remplir. * +* * +* Description : Charge un opérande depuis une mémoire tampon. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool g_armv7_iflags_operand_unserialize(GArmV7IFlagsOperand *operand, GAsmStorage *storage, GBinFormat *format, packed_buffer *pbuf) +{ + bool result; /* Bilan à retourner */ + GArchOperandClass *parent; /* Classe parente à consulter */ + uint8_t boolean; /* Valeur booléenne */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_iflags_operand_parent_class); + + result = parent->unserialize(G_ARCH_OPERAND(operand), storage, format, pbuf); + + if (result) + { + result = extract_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + + if (result) + operand->abort_bit = (boolean == 1 ? true : false); + + } + + if (result) + { + result = extract_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + + if (result) + operand->irq_bit = (boolean == 1 ? true : false); + + } + + if (result) + { + result = extract_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + + if (result) + operand->fiq_bit = (boolean == 1 ? true : false); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande d'assemblage à consulter. * +* storage = mécanisme de sauvegarde à manipuler. * +* pbuf = zone tampon à remplir. * +* * +* Description : Sauvegarde un opérande dans une mémoire tampon. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool g_armv7_iflags_operand_serialize(const GArmV7IFlagsOperand *operand, GAsmStorage *storage, packed_buffer *pbuf) +{ + bool result; /* Bilan à retourner */ + GArchOperandClass *parent; /* Classe parente à consulter */ + uint8_t boolean; /* Valeur booléenne */ + + parent = G_ARCH_OPERAND_CLASS(g_armv7_iflags_operand_parent_class); + + result = parent->serialize(G_ARCH_OPERAND(operand), storage, pbuf); + + if (result) + { + boolean = (operand->abort_bit ? 1 : 0); + result = extend_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + } + + if (result) + { + boolean = (operand->irq_bit ? 1 : 0); + result = extend_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + } + + if (result) + { + boolean = (operand->fiq_bit ? 1 : 0); + result = extend_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + } + + return result; + +} diff --git a/plugins/arm/v7/operands/iflags.h b/plugins/arm/v7/operands/iflags.h new file mode 100644 index 0000000..c0155a1 --- /dev/null +++ b/plugins/arm/v7/operands/iflags.h @@ -0,0 +1,59 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * iflags.h - prototypes pour les opérandes précisant un masque d'interruption ARMv7 + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +#ifndef _PLUGINS_ARM_V7_OPERANDS_IFLAGS_H +#define _PLUGINS_ARM_V7_OPERANDS_IFLAGS_H + + +#include +#include + + +#include + + + +#define G_TYPE_ARMV7_IFLAGS_OPERAND g_armv7_iflags_operand_get_type() +#define G_ARMV7_IFLAGS_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), G_TYPE_ARMV7_IFLAGS_OPERAND, GArmV7IFlagsOperand)) +#define G_IS_ARMV7_IFLAGS_OPERAND(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), G_TYPE_ARMV7_IFLAGS_OPERAND)) +#define G_ARMV7_IFLAGS_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_ARMV7_IFLAGS_OPERAND, GArmV7IFlagsOperandClass)) +#define G_IS_ARMV7_IFLAGS_OPERAND_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_ARMV7_IFLAGS_OPERAND)) +#define G_ARMV7_IFLAGS_OPERAND_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_ARMV7_IFLAGS_OPERAND, GArmV7IFlagsOperandClass)) + + +/* Définition d'un opérande précisant un masque d'interruption ARMv7 (instance) */ +typedef struct _GArmV7IFlagsOperand GArmV7IFlagsOperand; + +/* Définition d'un opérande précisant un masque d'interruption ARMv7 (classe) */ +typedef struct _GArmV7IFlagsOperandClass GArmV7IFlagsOperandClass; + + +/* Indique le type défini par la GLib pour un opérande de masque d'interruption ARMv7. */ +GType g_armv7_iflags_operand_get_type(void); + +/* Crée un opérande de masque d'interruption ARMv7. */ +GArchOperand *g_armv7_iflags_operand_new(bool, bool, bool); + + + +#endif /* _PLUGINS_ARM_V7_OPERANDS_IFLAGS_H */ diff --git a/plugins/arm/v7/operands/reglist.c b/plugins/arm/v7/operands/reglist.c index 0f87424..53b24a4 100644 --- a/plugins/arm/v7/operands/reglist.c +++ b/plugins/arm/v7/operands/reglist.c @@ -378,6 +378,34 @@ GArmV7Register *g_armv7_reglist_operand_get_register(const GArmV7RegListOperand } +/****************************************************************************** +* * +* Paramètres : operand = liste de registres à consulter. * +* reg = registre à rechercher. * +* * +* Description : Indique si un registre est présent dans une liste. * +* * +* Retour : Bilan de l'analyse. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool g_armv7_reglist_operand_has_register(const GArmV7RegListOperand *operand, const GArmV7Register *reg) +{ + bool result; /* Bilan à faire remonter */ + size_t i; /* Boucle de parcours */ + + result = false; + + for (i = 0; i < operand->count && !result; i++) + result = (g_arch_register_compare(G_ARCH_REGISTER(operand->registers[i]), G_ARCH_REGISTER(reg)) == 0); + + return result; + +} + + /* ---------------------------------------------------------------------------------- */ /* TRANSPOSITIONS VIA CACHE DES OPERANDES */ diff --git a/plugins/arm/v7/operands/reglist.h b/plugins/arm/v7/operands/reglist.h index a8adc47..2d1bfa9 100644 --- a/plugins/arm/v7/operands/reglist.h +++ b/plugins/arm/v7/operands/reglist.h @@ -66,6 +66,9 @@ size_t g_armv7_reglist_count_registers(const GArmV7RegListOperand *); /* Founit un élément donné d'une liste de registres ARM. */ GArmV7Register *g_armv7_reglist_operand_get_register(const GArmV7RegListOperand *, size_t ); +/* Indique si un registre est présent dans une liste. */ +bool g_armv7_reglist_operand_has_register(const GArmV7RegListOperand *, const GArmV7Register *); + #endif /* _PLUGINS_ARM_V7_OPERANDS_REGLIST_H */ diff --git a/plugins/arm/v7/simd.c b/plugins/arm/v7/simd.c index 79ddcf2..a565011 100644 --- a/plugins/arm/v7/simd.c +++ b/plugins/arm/v7/simd.c @@ -139,7 +139,7 @@ GArchInstruction *process_armv7_simd_advanced_simd_data_processing_instructions( result = process_armv7_simd_two_registers_and_a_scalar(raw, arm); else if (u == b0 && (a & b10110) == b10110 && (c & b0001) == b0000) - result = armv7_read_simd_instr_vext(raw, arm); + result = armv7_read_simd_instr_a8_vext(raw, arm); else if (u == b1 && (a & b10110) == b10110) { @@ -147,10 +147,10 @@ GArchInstruction *process_armv7_simd_advanced_simd_data_processing_instructions( result = process_armv7_simd_two_registers_miscellaneous(raw, arm); else if ((b & b1100) == b1000 && (c & b0001) == b0000) - result = armv7_read_simd_instr_vtbl_vtbx(raw, arm); + result = armv7_read_simd_instr_a8_vtbl_vtbx(raw, arm); else if (b == b1100 && (c & b1001) == b0000) - result = armv7_read_simd_instr_vdup_scalar(raw, arm); + result = armv7_read_simd_instr_a8_vdup_scalar(raw, arm); } @@ -214,17 +214,17 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u if (a == b0000) { if (b == b0) - result = armv7_read_simd_instr_vhadd_vhsub(raw, arm); + result = armv7_read_simd_instr_a8_vhadd_vhsub(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqadd(raw, arm); + result = armv7_read_simd_instr_a8_vqadd(raw, arm); } else if (a == b0001) { if (b == b0) - result = armv7_read_simd_instr_vrhadd(raw, arm); + result = armv7_read_simd_instr_a8_vrhadd(raw, arm); else/* if (b == b1)*/ { @@ -232,20 +232,20 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u switch (c) { case b00: - result = armv7_read_simd_instr_vand_register(raw, arm); + result = armv7_read_simd_instr_a8_vand_register(raw, arm); break; case b01: - result = armv7_read_simd_instr_vbic_register(raw, arm); + result = armv7_read_simd_instr_a8_vbic_register(raw, arm); break; case b10: /* Cf. vmov_register aussi */ - result = armv7_read_simd_instr_vorr_register(raw, arm); + result = armv7_read_simd_instr_a8_vorr_register(raw, arm); break; case b11: - result = armv7_read_simd_instr_vorn_register(raw, arm); + result = armv7_read_simd_instr_a8_vorn_register(raw, arm); break; } @@ -254,19 +254,19 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u switch (c) { case b00: - result = armv7_read_simd_instr_veor(raw, arm); + result = armv7_read_simd_instr_a8_veor(raw, arm); break; case b01: - result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm); + result = armv7_read_simd_instr_a8_vbif_vbit_vbsl(raw, arm); break; case b10: - result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm); + result = armv7_read_simd_instr_a8_vbif_vbit_vbsl(raw, arm); break; case b11: - result = armv7_read_simd_instr_vbif_vbit_vbsl(raw, arm); + result = armv7_read_simd_instr_a8_vbif_vbit_vbsl(raw, arm); break; } @@ -278,53 +278,53 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u else if (a == b0010) { if (b == b0) - result = armv7_read_simd_instr_vhadd_vhsub(raw, arm); + result = armv7_read_simd_instr_a8_vhadd_vhsub(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqsub(raw, arm); + result = armv7_read_simd_instr_a8_vqsub(raw, arm); } else if (a == b0011) { if (b == b0) - result = armv7_read_simd_instr_vcgt_register(raw, arm); + result = armv7_read_simd_instr_a8_vcgt_register(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vcge_register(raw, arm); + result = armv7_read_simd_instr_a8_vcge_register(raw, arm); } else if (a == b0100) { if (b == b0) - result = armv7_read_simd_instr_vshl_register(raw, arm); + result = armv7_read_simd_instr_a8_vshl_register(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqshl_register(raw, arm); + result = armv7_read_simd_instr_a8_vqshl_register(raw, arm); } else if (a == b0101) { if (b == b0) - result = armv7_read_simd_instr_vrshl(raw, arm); + result = armv7_read_simd_instr_a8_vrshl(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vqrshl(raw, arm); + result = armv7_read_simd_instr_a8_vqrshl(raw, arm); } else if (a == b0110) - result = armv7_read_simd_instr_vmax_vmin_integer(raw, arm); + result = armv7_read_simd_instr_a8_vmax_vmin_integer(raw, arm); else if (a == b0111) { if (b == b0) - result = armv7_read_simd_instr_vabd_vabdl_integer(raw, arm); + result = armv7_read_simd_instr_a8_vabd_vabdl_integer(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vaba_vabal(raw, arm); + result = armv7_read_simd_instr_a8_vaba_vabal(raw, arm); } @@ -333,20 +333,20 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u if (b == b0) { if (u == b0) - result = armv7_read_simd_instr_vadd_integer(raw, arm); + result = armv7_read_simd_instr_a8_vadd_integer(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vsub_integer(raw, arm); + result = armv7_read_simd_instr_a8_vsub_integer(raw, arm); } else/* if (b == b1)*/ { if (u == b0) - result = armv7_read_simd_instr_vtst(raw, arm); + result = armv7_read_simd_instr_a8_vtst(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vceq_register(raw, arm); + result = armv7_read_simd_instr_a8_vceq_register(raw, arm); } @@ -355,32 +355,32 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u else if (a == b1001) { if (b == b0) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(raw, arm); + result = armv7_read_simd_instr_a8_vmla_vmlal_vmls_vmlsl_integer(raw, arm); else/* if (b == b1)*/ - result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm); + result = armv7_read_simd_instr_a8_vmul_vmull_integer_and_polynomial(raw, arm); } else if (a == b1010) - result = armv7_read_simd_instr_vpmax_vpmin_integer(raw, arm); + result = armv7_read_simd_instr_a8_vpmax_vpmin_integer(raw, arm); else if (a == b1011) { if (b == b0) { if (u == b0) - result = armv7_read_simd_instr_vqdmulh(raw, arm); + result = armv7_read_simd_instr_a8_vqdmulh(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vqrdmulh(raw, arm); + result = armv7_read_simd_instr_a8_vqrdmulh(raw, arm); } else/* if (b == b1)*/ { if (u == b0) - result = armv7_read_simd_instr_vpadd_integer(raw, arm); + result = armv7_read_simd_instr_a8_vpadd_integer(raw, arm); } @@ -389,7 +389,7 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u else if (a == b1100) { if (b == b1 && u == b0) - result = armv7_read_simd_instr_vfma_vfms(raw, arm); + result = armv7_read_simd_instr_a8_vfma_vfms(raw, arm); } @@ -400,20 +400,20 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u if (u == b0) { if ((c & b10) == b00) - result = armv7_read_simd_instr_vadd_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vadd_floating_point(raw, arm); else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vsub_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vsub_floating_point(raw, arm); } else/* if (u == b1)*/ { if ((c & b10) == b00) - result = armv7_read_simd_instr_vpadd_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vpadd_floating_point(raw, arm); else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vabd_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vabd_floating_point(raw, arm); } @@ -422,12 +422,12 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u else/* if (b == b1)*/ { if (u == b0) - result = armv7_read_simd_instr_vmla_vmls_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vmla_vmls_floating_point(raw, arm); else/* if (u == b1)*/ { if ((c & b10) == b00) - result = armv7_read_simd_instr_vmul_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vmul_floating_point(raw, arm); } @@ -442,17 +442,17 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u if (u == b0) { if ((c & b10) == b00) - result = armv7_read_simd_instr_vceq_register(raw, arm); + result = armv7_read_simd_instr_a8_vceq_register(raw, arm); } else/* if (u == b1)*/ { if ((c & b10) == b00) - result = armv7_read_simd_instr_vcge_register(raw, arm); + result = armv7_read_simd_instr_a8_vcge_register(raw, arm); else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vcgt_register(raw, arm); + result = armv7_read_simd_instr_a8_vcgt_register(raw, arm); } @@ -461,7 +461,7 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u else/* if (b == b1)*/ { if (u == b1) - result = armv7_read_simd_instr_vacge_vacgt_vacle_vaclt(raw, arm); + result = armv7_read_simd_instr_a8_vacge_vacgt_vacle_vaclt(raw, arm); } @@ -472,10 +472,10 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u if (b == b0) { if (u == b0) - result = armv7_read_simd_instr_vmax_vmin_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vmax_vmin_floating_point(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vpmax_vpmin_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vpmax_vpmin_floating_point(raw, arm); } @@ -484,10 +484,10 @@ static GArchInstruction *process_armv7_simd_three_registers_of_the_same_length(u if (u == b0) { if ((c & b10) == b00) - result = armv7_read_simd_instr_vrecps(raw, arm); + result = armv7_read_simd_instr_a8_vrecps(raw, arm); else/* if ((c & b10) == b10)*/ - result = armv7_read_simd_instr_vrsqrts(raw, arm); + result = armv7_read_simd_instr_a8_vrsqrts(raw, arm); } @@ -547,59 +547,59 @@ static GArchInstruction *process_armv7_simd_three_registers_of_different_lengths } if ((a & b1110) == b0000) - result = armv7_read_simd_instr_vaddl_vaddw(raw, arm); + result = armv7_read_simd_instr_a8_vaddl_vaddw(raw, arm); else if ((a & b1110) == b0010) - result = armv7_read_simd_instr_vsubl_vsubw(raw, arm); + result = armv7_read_simd_instr_a8_vsubl_vsubw(raw, arm); else if (a == b0100) { if (u == b0) - result = armv7_read_simd_instr_vaddhn(raw, arm); + result = armv7_read_simd_instr_a8_vaddhn(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vraddhn(raw, arm); + result = armv7_read_simd_instr_a8_vraddhn(raw, arm); } else if (a == b0101) - result = armv7_read_simd_instr_vaba_vabal(raw, arm); + result = armv7_read_simd_instr_a8_vaba_vabal(raw, arm); else if (a == b0110) { if (u == b0) - result = armv7_read_simd_instr_vsubhn(raw, arm); + result = armv7_read_simd_instr_a8_vsubhn(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vrsubhn(raw, arm); + result = armv7_read_simd_instr_a8_vrsubhn(raw, arm); } else if (a == b0111) - result = armv7_read_simd_instr_vabd_vabdl_integer(raw, arm); + result = armv7_read_simd_instr_a8_vabd_vabdl_integer(raw, arm); else if ((a & b1101) == b1000) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_integer(raw, arm); + result = armv7_read_simd_instr_a8_vmla_vmlal_vmls_vmlsl_integer(raw, arm); else if ((a & b1101) == b1001) { if (u == b0) - result = armv7_read_simd_instr_vqdmlal_vqdmlsl(raw, arm); + result = armv7_read_simd_instr_a8_vqdmlal_vqdmlsl(raw, arm); } else if (a == b1100) - result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm); + result = armv7_read_simd_instr_a8_vmul_vmull_integer_and_polynomial(raw, arm); else if (a == b1101) { if (u == b0) - result = armv7_read_simd_instr_vqdmull(raw, arm); + result = armv7_read_simd_instr_a8_vqdmull(raw, arm); } else if (a == b1110) - result = armv7_read_simd_instr_vmul_vmull_integer_and_polynomial(raw, arm); + result = armv7_read_simd_instr_a8_vmul_vmull_integer_and_polynomial(raw, arm); return result; @@ -653,28 +653,28 @@ static GArchInstruction *process_armv7_simd_two_registers_and_a_scalar(uint32_t } if ((a & b1010) == b0000) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm); + result = armv7_read_simd_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm); else if ((a & b1010) == b0010) - result = armv7_read_simd_instr_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm); + result = armv7_read_simd_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(raw, arm); else if ((a & b1011) == b0011 && u == b0) - result = armv7_read_simd_instr_vqdmlal_vqdmlsl(raw, arm); + result = armv7_read_simd_instr_a8_vqdmlal_vqdmlsl(raw, arm); else if ((a & b1110) == b1000) - result = armv7_read_simd_instr_vmul_vmull_by_scalar(raw, arm); + result = armv7_read_simd_instr_a8_vmul_vmull_by_scalar(raw, arm); else if (a == b1010) - result = armv7_read_simd_instr_vmul_vmull_by_scalar(raw, arm); + result = armv7_read_simd_instr_a8_vmul_vmull_by_scalar(raw, arm); else if (a == b1011 && u == b0) - result = armv7_read_simd_instr_vqdmull(raw, arm); + result = armv7_read_simd_instr_a8_vqdmull(raw, arm); else if (a == b1100) - result = armv7_read_simd_instr_vqdmulh(raw, arm); + result = armv7_read_simd_instr_a8_vqdmulh(raw, arm); else if (a == b1101) - result = armv7_read_simd_instr_vqrdmulh(raw, arm); + result = armv7_read_simd_instr_a8_vqrdmulh(raw, arm); return result; @@ -734,51 +734,51 @@ static GArchInstruction *process_armv7_simd_two_registers_and_a_shift_amount(uin } if (a == b0000) - result = armv7_read_simd_instr_vshr(raw, arm); + result = armv7_read_simd_instr_a8_vshr(raw, arm); else if (a == b0001) - result = armv7_read_simd_instr_vsra(raw, arm); + result = armv7_read_simd_instr_a8_vsra(raw, arm); else if (a == b0010) - result = armv7_read_simd_instr_vrshr(raw, arm); + result = armv7_read_simd_instr_a8_vrshr(raw, arm); else if (a == b0011) - result = armv7_read_simd_instr_vrsra(raw, arm); + result = armv7_read_simd_instr_a8_vrsra(raw, arm); else if (a == b0100 && u == b1) - result = armv7_read_simd_instr_vsri(raw, arm); + result = armv7_read_simd_instr_a8_vsri(raw, arm); else if (a == b0101) { if (u == b0) - result = armv7_read_simd_instr_vshl_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vshl_immediate(raw, arm); else/* if (u == b1)*/ - result = armv7_read_simd_instr_vsli(raw, arm); + result = armv7_read_simd_instr_a8_vsli(raw, arm); } else if ((a & b1110) == b0110) - result = armv7_read_simd_instr_vqshl_vqshlu_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vqshl_vqshlu_immediate(raw, arm); else if (a == b1000) { if (u == b0) { if (b == b0 && l == b0) - result = armv7_read_simd_instr_vshrn(raw, arm); + result = armv7_read_simd_instr_a8_vshrn(raw, arm); else if (b == b1 && l == b0) - result = armv7_read_simd_instr_vrshrn(raw, arm); + result = armv7_read_simd_instr_a8_vrshrn(raw, arm); } else/* if (u == b1)*/ { if (b == b0 && l == b0) - result = armv7_read_simd_instr_vqshrn_vqshrun(raw, arm); + result = armv7_read_simd_instr_a8_vqshrn_vqshrun(raw, arm); else if (b == b1 && l == b0) - result = armv7_read_simd_instr_vqrshrn_vqrshrun(raw, arm); + result = armv7_read_simd_instr_a8_vqrshrn_vqrshrun(raw, arm); } @@ -787,25 +787,25 @@ static GArchInstruction *process_armv7_simd_two_registers_and_a_shift_amount(uin else if (a == b1001) { if (b == b0 && l == b0) - result = armv7_read_simd_instr_vqshrn_vqshrun(raw, arm); + result = armv7_read_simd_instr_a8_vqshrn_vqshrun(raw, arm); else if (b == b1 && l == b0) - result = armv7_read_simd_instr_vqrshrn_vqrshrun(raw, arm); + result = armv7_read_simd_instr_a8_vqrshrn_vqrshrun(raw, arm); } else if (a == b1010 && b == b0 && l == b0) { - result = armv7_read_simd_instr_vshll(raw, arm); + result = armv7_read_simd_instr_a8_vshll(raw, arm); /* ??? */ if (result == NULL) - result = armv7_read_simd_instr_vmovl(raw, arm); + result = armv7_read_simd_instr_a8_vmovl(raw, arm); } else if ((a & b1110) == b1110 && l == b0) - result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_advanced_simd(raw, arm); + result = armv7_read_simd_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(raw, arm); return result; @@ -853,62 +853,62 @@ static GArchInstruction *process_armv7_simd_two_registers_miscellaneous(uint32_t if (a == b00) { if ((b & b11110) == b00000) - result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm); + result = armv7_read_simd_instr_a8_vrev16_vrev32_vrev64(raw, arm); else if ((b & b11110) == b00010) - result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm); + result = armv7_read_simd_instr_a8_vrev16_vrev32_vrev64(raw, arm); else if ((b & b11110) == b00100) - result = armv7_read_simd_instr_vrev16_vrev32_vrev64(raw, arm); + result = armv7_read_simd_instr_a8_vrev16_vrev32_vrev64(raw, arm); else if ((b & b11100) == b01000) - result = armv7_read_simd_instr_vpaddl(raw, arm); + result = armv7_read_simd_instr_a8_vpaddl(raw, arm); else if ((b & b11110) == b10000) - result = armv7_read_simd_instr_vcls(raw, arm); + result = armv7_read_simd_instr_a8_vcls(raw, arm); else if ((b & b11110) == b10010) - result = armv7_read_simd_instr_vclz(raw, arm); + result = armv7_read_simd_instr_a8_vclz(raw, arm); else if ((b & b11110) == b10100) - result = armv7_read_simd_instr_vcnt(raw, arm); + result = armv7_read_simd_instr_a8_vcnt(raw, arm); else if ((b & b11110) == b10110) - result = armv7_read_simd_instr_vmvn_register(raw, arm); + result = armv7_read_simd_instr_a8_vmvn_register(raw, arm); else if ((b & b11100) == b11000) - result = armv7_read_simd_instr_vpadal(raw, arm); + result = armv7_read_simd_instr_a8_vpadal(raw, arm); else if ((b & b11110) == b11100) - result = armv7_read_simd_instr_vqabs(raw, arm); + result = armv7_read_simd_instr_a8_vqabs(raw, arm); else if ((b & b11110) == b11110) - result = armv7_read_simd_instr_vqneg(raw, arm); + result = armv7_read_simd_instr_a8_vqneg(raw, arm); } else if (a == b01) { if ((b & b01110) == b00000) - result = armv7_read_simd_instr_vcgt_immediate_0(raw, arm); + result = armv7_read_simd_instr_a8_vcgt_immediate_0(raw, arm); else if ((b & b01110) == b00010) - result = armv7_read_simd_instr_vcge_immediate_0(raw, arm); + result = armv7_read_simd_instr_a8_vcge_immediate_0(raw, arm); else if ((b & b01110) == b00100) - result = armv7_read_simd_instr_vceq_immediate_0(raw, arm); + result = armv7_read_simd_instr_a8_vceq_immediate_0(raw, arm); else if ((b & b01110) == b00110) - result = armv7_read_simd_instr_vcle_immediate_0(raw, arm); + result = armv7_read_simd_instr_a8_vcle_immediate_0(raw, arm); else if ((b & b01110) == b01000) - result = armv7_read_simd_instr_vclt_immediate_0(raw, arm); + result = armv7_read_simd_instr_a8_vclt_immediate_0(raw, arm); else if ((b & b01110) == b01100) - result = armv7_read_simd_instr_vabs(raw, arm); + result = armv7_read_simd_instr_a8_vabs(raw, arm); else if ((b & b01110) == b01110) - result = armv7_read_simd_instr_vneg(raw, arm); + result = armv7_read_simd_instr_a8_vneg(raw, arm); } @@ -958,41 +958,41 @@ static GArchInstruction *process_armv7_simd_one_register_and_a_modified_immediat if (op == b0) { if ((cmode & b1001) == b0000) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmov_immediate(raw, arm); else if ((cmode & b1001) == b0001) - result = armv7_read_simd_instr_vorr_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vorr_immediate(raw, arm); else if ((cmode & b1101) == b1000) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmov_immediate(raw, arm); else if ((cmode & b1101) == b1001) - result = armv7_read_simd_instr_vorr_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vorr_immediate(raw, arm); else if ((cmode & b1100) == b1100) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmov_immediate(raw, arm); } else/* if (op == b1)*/ { if ((cmode & b1001) == b0000) - result = armv7_read_simd_instr_vmvn_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmvn_immediate(raw, arm); else if ((cmode & b1001) == b0001) - result = armv7_read_simd_instr_vbic_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vbic_immediate(raw, arm); else if ((cmode & b1101) == b1000) - result = armv7_read_simd_instr_vmvn_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmvn_immediate(raw, arm); else if ((cmode & b1101) == b1001) - result = armv7_read_simd_instr_vbic_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vbic_immediate(raw, arm); else if ((cmode & b1110) == b1100) - result = armv7_read_simd_instr_vmvn_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmvn_immediate(raw, arm); else if (cmode == b1110) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmov_immediate(raw, arm); else if (cmode == b1111) result = g_undef_instruction_new(IBS_UNDEFINED); @@ -1046,89 +1046,89 @@ GArchInstruction *process_armv7_simd_floating_point_data_processing_instructions if ((opc1 & b1011) == b0000) - result = armv7_read_simd_instr_vmla_vmls_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vmla_vmls_floating_point(raw, arm); else if ((opc1 & b1011) == b0001) - result = armv7_read_simd_instr_vnmla_vnmls_vnmul(raw, arm); + result = armv7_read_simd_instr_a8_vnmla_vnmls_vnmul(raw, arm); else if ((opc1 & b1011) == b0010) { if ((opc3 & b01) == b01) - result = armv7_read_simd_instr_vnmla_vnmls_vnmul(raw, arm); + result = armv7_read_simd_instr_a8_vnmla_vnmls_vnmul(raw, arm); else/* if ((opc3 & b01) == b00)*/ - result = armv7_read_simd_instr_vmul_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vmul_floating_point(raw, arm); } else if ((opc1 & b1011) == b0011) { if ((opc3 & b01) == b00) - result = armv7_read_simd_instr_vadd_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vadd_floating_point(raw, arm); else/* if ((opc3 & b01) == b01)*/ - result = armv7_read_simd_instr_vsub_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vsub_floating_point(raw, arm); } else if ((opc1 & b1011) == b1000) { if ((opc3 & b01) == b00) - result = armv7_read_simd_instr_vdiv(raw, arm); + result = armv7_read_simd_instr_a8_vdiv(raw, arm); } else if ((opc1 & b1011) == b1001) - result = armv7_read_simd_instr_vfnma_vfnms(raw, arm); + result = armv7_read_simd_instr_a8_vfnma_vfnms(raw, arm); else if ((opc1 & b1011) == b1010) - result = armv7_read_simd_instr_vfma_vfms(raw, arm); + result = armv7_read_simd_instr_a8_vfma_vfms(raw, arm); else if ((opc1 & b1011) == b1011) { if ((opc3 & b01) == b00) - result = armv7_read_simd_instr_vmov_immediate(raw, arm); + result = armv7_read_simd_instr_a8_vmov_immediate(raw, arm); else if (opc2 == b0000) { if (opc3 == b01) - result = armv7_read_simd_instr_vmov_register(raw, arm); + result = armv7_read_simd_instr_a8_vmov_register(raw, arm); else if (opc3 == b11) - result = armv7_read_simd_instr_vabs(raw, arm); + result = armv7_read_simd_instr_a8_vabs(raw, arm); } else if (opc2 == b0001) { if (opc3 == b01) - result = armv7_read_simd_instr_vneg(raw, arm); + result = armv7_read_simd_instr_a8_vneg(raw, arm); else if (opc3 == b11) - result = armv7_read_simd_instr_vsqrt(raw, arm); + result = armv7_read_simd_instr_a8_vsqrt(raw, arm); } else if ((opc2 & b1110) == b0010 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvtb_vcvtt(raw, arm); + result = armv7_read_simd_instr_a8_vcvtb_vcvtt(raw, arm); else if ((opc2 & b1110) == b0100 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcmp_vcmpe(raw, arm); + result = armv7_read_simd_instr_a8_vcmp_vcmpe(raw, arm); else if (opc2 == b0111 && opc3 == b11) - result = armv7_read_simd_instr_vcvt_between_double_precision_and_single_precision(raw, arm); + result = armv7_read_simd_instr_a8_vcvt_between_double_precision_and_single_precision(raw, arm); else if (opc2 == b1000 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm); else if ((opc2 & b1110) == b1010 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm); else if ((opc2 & b1110) == b1100 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vcvt_vcvtr_between_floating_point_and_integer_floating_point(raw, arm); else if ((opc2 & b1110) == b1110 && (opc3 & b01) == b01) - result = armv7_read_simd_instr_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm); + result = armv7_read_simd_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(raw, arm); } @@ -1179,42 +1179,42 @@ GArchInstruction *process_armv7_simd_extension_register_load_store_instructions( result = process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(raw, arm); else if ((opcode & b11011) == b01000) - result = armv7_read_simd_instr_vstm(raw, arm); + result = armv7_read_simd_instr_a8_vstm(raw, arm); else if ((opcode & b11011) == b01010) - result = armv7_read_simd_instr_vstm(raw, arm); + result = armv7_read_simd_instr_a8_vstm(raw, arm); else if ((opcode & b10011) == b10000) - result = armv7_read_simd_instr_vstr(raw, arm); + result = armv7_read_simd_instr_a8_vstr(raw, arm); else if ((opcode & b11011) == b10010) { if (rn != b1101) - result = armv7_read_simd_instr_vstm(raw, arm); + result = armv7_read_simd_instr_a8_vstm(raw, arm); else/* if (rn == b1101)*/ - result = armv7_read_simd_instr_vpush(raw, arm); + result = armv7_read_simd_instr_a8_vpush(raw, arm); } else if ((opcode & b11011) == b01001) - result = armv7_read_simd_instr_vldm(raw, arm); + result = armv7_read_simd_instr_a8_vldm(raw, arm); else if ((opcode & b11011) == b01011) { if (rn != 1101) - result = armv7_read_simd_instr_vldm(raw, arm); + result = armv7_read_simd_instr_a8_vldm(raw, arm); else/* if (rn == 1101)*/ - result = armv7_read_simd_instr_vpop(raw, arm); + result = armv7_read_simd_instr_a8_vpop(raw, arm); } else if ((opcode & b10011) == b10001) - result = armv7_read_simd_instr_vldr(raw, arm); + result = armv7_read_simd_instr_a8_vldr(raw, arm); else if ((opcode & b11011) == b10011) - result = armv7_read_simd_instr_vldm(raw, arm); + result = armv7_read_simd_instr_a8_vldm(raw, arm); return result; @@ -1266,53 +1266,53 @@ GArchInstruction *process_armv7_simd_advanced_simd_element_or_structure_load_sto if (a == b0) { if (b == b0010) - result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm); + result = armv7_read_simd_instr_a8_vst1_multiple_single_elements(raw, arm); else if ((b & b1110) == b0110) - result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm); + result = armv7_read_simd_instr_a8_vst1_multiple_single_elements(raw, arm); else if (b == b1010) - result = armv7_read_simd_instr_vst1_multiple_single_elements(raw, arm); + result = armv7_read_simd_instr_a8_vst1_multiple_single_elements(raw, arm); else if (b == b0011) - result = armv7_read_simd_instr_vst2_multiple_2_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vst2_multiple_2_element_structures(raw, arm); else if ((b & b1110) == b1000) - result = armv7_read_simd_instr_vst2_multiple_2_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vst2_multiple_2_element_structures(raw, arm); else if ((b & b1110) == b0100) - result = armv7_read_simd_instr_vst3_multiple_3_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vst3_multiple_3_element_structures(raw, arm); else if ((b & b1110) == b0000) - result = armv7_read_simd_instr_vst4_multiple_4_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vst4_multiple_4_element_structures(raw, arm); } else/* if (a == b1)*/ { if ((b & b1011) == b0000) - result = armv7_read_simd_instr_vst1_single_element_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst1_single_element_from_one_lane(raw, arm); else if (b == b1000) - result = armv7_read_simd_instr_vst1_single_element_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst1_single_element_from_one_lane(raw, arm); else if ((b & b1011) == b0001) - result = armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst2_single_2_element_structure_from_one_lane(raw, arm); else if (b == b1001) - result = armv7_read_simd_instr_vst2_single_2_element_structure_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst2_single_2_element_structure_from_one_lane(raw, arm); else if ((b & b1011) == b0010) - result = armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst3_single_3_element_structure_from_one_lane(raw, arm); else if (b == b1010) - result = armv7_read_simd_instr_vst3_single_3_element_structure_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst3_single_3_element_structure_from_one_lane(raw, arm); else if ((b & b1011) == b0011) - result = armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst4_single_4_element_structure_from_one_lane(raw, arm); else if (b == b1011) - result = armv7_read_simd_instr_vst4_single_4_element_structure_from_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vst4_single_4_element_structure_from_one_lane(raw, arm); } @@ -1323,65 +1323,65 @@ GArchInstruction *process_armv7_simd_advanced_simd_element_or_structure_load_sto if (a == b0) { if (b == b0010) - result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm); + result = armv7_read_simd_instr_a8_vld1_multiple_single_elements(raw, arm); else if ((b & b1110) == b0110) - result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm); + result = armv7_read_simd_instr_a8_vld1_multiple_single_elements(raw, arm); else if (b == b1010) - result = armv7_read_simd_instr_vld1_multiple_single_elements(raw, arm); + result = armv7_read_simd_instr_a8_vld1_multiple_single_elements(raw, arm); else if (b == b0011) - result = armv7_read_simd_instr_vld2_multiple_2_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vld2_multiple_2_element_structures(raw, arm); else if ((b & b1110) == b1000) - result = armv7_read_simd_instr_vld2_multiple_2_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vld2_multiple_2_element_structures(raw, arm); else if ((b & b1110) == b0100) - result = armv7_read_simd_instr_vld3_multiple_3_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vld3_multiple_3_element_structures(raw, arm); else if ((b & b1110) == b0000) - result = armv7_read_simd_instr_vld4_multiple_4_element_structures(raw, arm); + result = armv7_read_simd_instr_a8_vld4_multiple_4_element_structures(raw, arm); } else/* if (a == b1)*/ { if ((b & b1011) == b0000) - result = armv7_read_simd_instr_vld1_single_element_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld1_single_element_to_one_lane(raw, arm); else if (b == b1000) - result = armv7_read_simd_instr_vld1_single_element_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld1_single_element_to_one_lane(raw, arm); else if (b == b1100) - result = armv7_read_simd_instr_vld1_single_element_to_all_lanes(raw, arm); + result = armv7_read_simd_instr_a8_vld1_single_element_to_all_lanes(raw, arm); else if ((b & b1011) == b0001) - result = armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld2_single_2_element_structure_to_one_lane(raw, arm); else if (b == b1001) - result = armv7_read_simd_instr_vld2_single_2_element_structure_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld2_single_2_element_structure_to_one_lane(raw, arm); else if (b == b1101) - result = armv7_read_simd_instr_vld2_single_2_element_structure_to_all_lanes(raw, arm); + result = armv7_read_simd_instr_a8_vld2_single_2_element_structure_to_all_lanes(raw, arm); else if ((b & b1011) == b0010) - result = armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld3_single_3_element_structure_to_one_lane(raw, arm); else if (b == b1010) - result = armv7_read_simd_instr_vld3_single_3_element_structure_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld3_single_3_element_structure_to_one_lane(raw, arm); else if (b == b1110) - result = armv7_read_simd_instr_vld3_single_3_element_structure_to_all_lanes(raw, arm); + result = armv7_read_simd_instr_a8_vld3_single_3_element_structure_to_all_lanes(raw, arm); else if ((b & b1011) == b0011) - result = armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld4_single_4_element_structure_to_one_lane(raw, arm); else if (b == b1011) - result = armv7_read_simd_instr_vld4_single_4_element_structure_to_one_lane(raw, arm); + result = armv7_read_simd_instr_a8_vld4_single_4_element_structure_to_one_lane(raw, arm); else if (b == b1111) - result = armv7_read_simd_instr_vld4_single_4_element_structure_to_all_lanes(raw, arm); + result = armv7_read_simd_instr_a8_vld4_single_4_element_structure_to_all_lanes(raw, arm); } @@ -1439,14 +1439,14 @@ GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_a if (c == b0) { if (a == b000) - result = armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(raw, arm); + result = armv7_read_simd_instr_a8_vmov_between_arm_core_register_and_single_precision_register(raw, arm); else if (a == b111) { - result = armv7_read_simd_instr_vmsr(raw, arm); + result = armv7_read_simd_instr_a8_vmsr(raw, arm); /* B9 ? */ if (result == NULL /* ! */) - result = armv7_read_simd_instr_vmsr_b9(raw, arm); + result = armv7_read_simd_instr_b9_vmsr(raw, arm); } @@ -1455,10 +1455,10 @@ GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_a else/* if (c == b1)*/ { if ((a & b100) == b000) - result = armv7_read_simd_instr_vmov_arm_core_register_to_scalar(raw, arm); + result = armv7_read_simd_instr_a8_vmov_arm_core_register_to_scalar(raw, arm); else if (/*(a & b100) == b000) && */(b & b10) == b00) - result = armv7_read_simd_instr_vdup_arm_core_register(raw, arm); + result = armv7_read_simd_instr_a8_vdup_arm_core_register(raw, arm); } @@ -1469,21 +1469,21 @@ GArchInstruction *process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_a if (c == b0) { if (a == b000) - result = armv7_read_simd_instr_vmov_between_arm_core_register_and_single_precision_register(raw, arm); + result = armv7_read_simd_instr_a8_vmov_between_arm_core_register_and_single_precision_register(raw, arm); else if (a == b111) { - result = armv7_read_simd_instr_vmrs(raw, arm); + result = armv7_read_simd_instr_a8_vmrs(raw, arm); /* B9 ? */ if (result == NULL /* ! */) - result = armv7_read_simd_instr_vmrs_b9(raw, arm); + result = armv7_read_simd_instr_b9_vmrs(raw, arm); } } else/* if (c == b1)*/ - result = armv7_read_simd_instr_vmov_scalar_to_arm_core_register(raw, arm); + result = armv7_read_simd_instr_a8_vmov_scalar_to_arm_core_register(raw, arm); } @@ -1531,10 +1531,10 @@ GArchInstruction *process_armv7_simd_64_bit_transfers_between_arm_core_and_exten op = (raw >> 4) & b1111; if (c == b0 && (op & b1101) == 0001) - result = armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_two_single_precision_registers(raw, arm); + result = armv7_read_simd_instr_a8_vmov_between_two_arm_core_registers_and_two_single_precision_registers(raw, arm); else if (c == b1 && (op & b1101) == 0001) - result = armv7_read_simd_instr_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(raw, arm); + result = armv7_read_simd_instr_a8_vmov_between_two_arm_core_registers_and_a_doubleword_extension_register(raw, arm); return result; diff --git a/plugins/arm/v7/thumb_16.c b/plugins/arm/v7/thumb_16.c index a97779e..d592a80 100644 --- a/plugins/arm/v7/thumb_16.c +++ b/plugins/arm/v7/thumb_16.c @@ -94,7 +94,7 @@ GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t raw) result = process_armv7_thumb_16_special_data_instructions_and_branch_and_exchange(raw); else if ((opcode & b111110) == b010010) - result = armv7_read_thumb_16_instr_ldr_literal(raw); + result = armv7_read_thumb_16_instr_a8_ldr_literal(raw); else if ((opcode & b111100) == b010100) result = process_armv7_thumb_16_load_store_single_data_item(raw); @@ -106,25 +106,25 @@ GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t raw) result = process_armv7_thumb_16_load_store_single_data_item(raw); else if ((opcode & b111110) == b101000) - result = armv7_read_thumb_16_instr_adr(raw); + result = armv7_read_thumb_16_instr_a8_adr(raw); else if ((opcode & b111110) == b101010) - result = armv7_read_thumb_16_instr_add_sp_plus_immediate(raw); + result = armv7_read_thumb_16_instr_a8_add_sp_plus_immediate(raw); else if ((opcode & b111100) == b101100) result = process_armv7_thumb_16_miscellaneous_16_bit_instructions(raw); else if ((opcode & b111110) == b110000) - result = armv7_read_thumb_16_instr_stm_stmia_stmea(raw); + result = armv7_read_thumb_16_instr_a8_stm_stmia_stmea(raw); else if ((opcode & b111110) == b110010) - result = armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(raw); + result = armv7_read_thumb_16_instr_a8_ldm_ldmia_ldmfd_thumb(raw); else if ((opcode & b111100) == b110100) result = process_armv7_thumb_16_conditional_branch_and_supervisor_call(raw); else if ((opcode & b111110) == b111000) - result = armv7_read_thumb_16_instr_b(raw); + result = armv7_read_thumb_16_instr_a8_b(raw); return result; @@ -160,37 +160,37 @@ static GArchInstruction *process_armv7_thumb_16_shift_immediate_add_subtract_mov opcode = (raw >> 9) & b11111; if ((opcode & b11100) == b00000) - result = armv7_read_thumb_16_instr_lsl_immediate(raw); + result = armv7_read_thumb_16_instr_a8_lsl_immediate(raw); else if ((opcode & b11100) == b00100) - result = armv7_read_thumb_16_instr_lsr_immediate(raw); + result = armv7_read_thumb_16_instr_a8_lsr_immediate(raw); else if ((opcode & b11100) == b01000) - result = armv7_read_thumb_16_instr_asr_immediate(raw); + result = armv7_read_thumb_16_instr_a8_asr_immediate(raw); else if (opcode == b01100) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_add_register_thumb(raw); else if (opcode == b01101) - result = armv7_read_thumb_16_instr_sub_register(raw); + result = armv7_read_thumb_16_instr_a8_sub_register(raw); else if (opcode == b01110) - result = armv7_read_thumb_16_instr_add_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_add_immediate_thumb(raw); else if (opcode == b01111) - result = armv7_read_thumb_16_instr_sub_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_sub_immediate_thumb(raw); else if ((opcode & b11100) == b10000) - result = armv7_read_thumb_16_instr_mov_immediate(raw); + result = armv7_read_thumb_16_instr_a8_mov_immediate(raw); else if ((opcode & b11100) == b10100) - result = armv7_read_thumb_16_instr_cmp_immediate(raw); + result = armv7_read_thumb_16_instr_a8_cmp_immediate(raw); else if ((opcode & b11100) == b11000) - result = armv7_read_thumb_16_instr_add_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_add_immediate_thumb(raw); else if ((opcode & b11100) == b11100) - result = armv7_read_thumb_16_instr_sub_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_sub_immediate_thumb(raw); return result; @@ -228,67 +228,67 @@ static GArchInstruction *process_armv7_thumb_16_data_processing(uint16_t raw) switch (opcode) { case b0000: - result = armv7_read_thumb_16_instr_and_register(raw); + result = armv7_read_thumb_16_instr_a8_and_register(raw); break; case b0001: - result = armv7_read_thumb_16_instr_eor_register(raw); + result = armv7_read_thumb_16_instr_a8_eor_register(raw); break; case b0010: - result = armv7_read_thumb_16_instr_lsl_register(raw); + result = armv7_read_thumb_16_instr_a8_lsl_register(raw); break; case b0011: - result = armv7_read_thumb_16_instr_lsr_register(raw); + result = armv7_read_thumb_16_instr_a8_lsr_register(raw); break; case b0100: - result = armv7_read_thumb_16_instr_asr_register(raw); + result = armv7_read_thumb_16_instr_a8_asr_register(raw); break; case b0101: - result = armv7_read_thumb_16_instr_adc_register(raw); + result = armv7_read_thumb_16_instr_a8_adc_register(raw); break; case b0110: - result = armv7_read_thumb_16_instr_sbc_register(raw); + result = armv7_read_thumb_16_instr_a8_sbc_register(raw); break; case b0111: - result = armv7_read_thumb_16_instr_ror_register(raw); + result = armv7_read_thumb_16_instr_a8_ror_register(raw); break; case b1000: - result = armv7_read_thumb_16_instr_tst_register(raw); + result = armv7_read_thumb_16_instr_a8_tst_register(raw); break; case b1001: - result = armv7_read_thumb_16_instr_rsb_immediate(raw); + result = armv7_read_thumb_16_instr_a8_rsb_immediate(raw); break; case b1010: - result = armv7_read_thumb_16_instr_cmp_register(raw); + result = armv7_read_thumb_16_instr_a8_cmp_register(raw); break; case b1011: - result = armv7_read_thumb_16_instr_cmn_register(raw); + result = armv7_read_thumb_16_instr_a8_cmn_register(raw); break; case b1100: - result = armv7_read_thumb_16_instr_orr_register(raw); + result = armv7_read_thumb_16_instr_a8_orr_register(raw); break; case b1101: - result = armv7_read_thumb_16_instr_mul(raw); + result = armv7_read_thumb_16_instr_a8_mul(raw); break; case b1110: - result = armv7_read_thumb_16_instr_bic_register(raw); + result = armv7_read_thumb_16_instr_a8_bic_register(raw); break; case b1111: - result = armv7_read_thumb_16_instr_mvn_register(raw); + result = armv7_read_thumb_16_instr_a8_mvn_register(raw); break; } @@ -327,31 +327,31 @@ static GArchInstruction *process_armv7_thumb_16_special_data_instructions_and_br opcode = (raw >> 6) & b1111; if (opcode == b0000) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_add_register_thumb(raw); else if (opcode == b0001) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_add_register_thumb(raw); else if ((opcode & b1110) == b0010) - result = armv7_read_thumb_16_instr_add_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_add_register_thumb(raw); else if ((opcode & b1100) == b0100) - result = armv7_read_thumb_16_instr_cmp_register(raw); + result = armv7_read_thumb_16_instr_a8_cmp_register(raw); else if (opcode == b1000) - result = armv7_read_thumb_16_instr_mov_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_mov_register_thumb(raw); else if (opcode == b1001) - result = armv7_read_thumb_16_instr_mov_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_mov_register_thumb(raw); else if ((opcode & b1110) == b1010) - result = armv7_read_thumb_16_instr_mov_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_mov_register_thumb(raw); else if ((opcode & b1110) == b1100) - result = armv7_read_thumb_16_instr_bx(raw); + result = armv7_read_thumb_16_instr_a8_bx(raw); else if ((opcode & b1110) == b1110) - result = armv7_read_thumb_16_instr_blx_register(raw); + result = armv7_read_thumb_16_instr_a8_blx_register(raw); return result; @@ -392,35 +392,35 @@ static GArchInstruction *process_armv7_thumb_16_load_store_single_data_item(uint switch (opb) { case b000: - result = armv7_read_thumb_16_instr_str_register(raw); + result = armv7_read_thumb_16_instr_a8_str_register(raw); break; case b001: - result = armv7_read_thumb_16_instr_strh_register(raw); + result = armv7_read_thumb_16_instr_a8_strh_register(raw); break; case b010: - result = armv7_read_thumb_16_instr_strb_register(raw); + result = armv7_read_thumb_16_instr_a8_strb_register(raw); break; case b011: - result = armv7_read_thumb_16_instr_ldrsb_register(raw); + result = armv7_read_thumb_16_instr_a8_ldrsb_register(raw); break; case b100: - result = armv7_read_thumb_16_instr_ldr_register_thumb(raw); + result = armv7_read_thumb_16_instr_a8_ldr_register_thumb(raw); break; case b101: - result = armv7_read_thumb_16_instr_ldrh_register(raw); + result = armv7_read_thumb_16_instr_a8_ldrh_register(raw); break; case b110: - result = armv7_read_thumb_16_instr_ldrb_register(raw); + result = armv7_read_thumb_16_instr_a8_ldrb_register(raw); break; case b111: - result = armv7_read_thumb_16_instr_ldrsh_register(raw); + result = armv7_read_thumb_16_instr_a8_ldrsh_register(raw); break; } @@ -429,36 +429,36 @@ static GArchInstruction *process_armv7_thumb_16_load_store_single_data_item(uint case b0110: if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_str_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_str_immediate_thumb(raw); else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldr_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_ldr_immediate_thumb(raw); break; case b0111: if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_strb_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_strb_immediate_thumb(raw); else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldrb_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_ldrb_immediate_thumb(raw); break; case b1000: if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_strh_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_strh_immediate_thumb(raw); else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldrh_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_ldrh_immediate_thumb(raw); break; case b1001: if ((opb & b100) == b000) - result = armv7_read_thumb_16_instr_str_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_str_immediate_thumb(raw); else /*if ((opb & b100) == b100)*/ - result = armv7_read_thumb_16_instr_ldr_immediate_thumb(raw); + result = armv7_read_thumb_16_instr_a8_ldr_immediate_thumb(raw); break; @@ -498,58 +498,58 @@ static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instruction opcode = (raw >> 5) & b1111111; if ((opcode & b1111100) == b0000000) - result = armv7_read_thumb_16_instr_add_sp_plus_immediate(raw); + result = armv7_read_thumb_16_instr_a8_add_sp_plus_immediate(raw); else if ((opcode & b1111100) == b0000100) - result = armv7_read_thumb_16_instr_sub_sp_minus_immediate(raw); + result = armv7_read_thumb_16_instr_a8_sub_sp_minus_immediate(raw); else if ((opcode & b1111000) == b0001000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); + result = armv7_read_thumb_16_instr_a8_cbnz_cbz(raw); else if ((opcode & b1111110) == b0010000) - result = armv7_read_thumb_16_instr_sxth(raw); + result = armv7_read_thumb_16_instr_a8_sxth(raw); else if ((opcode & b1111110) == b0010010) - result = armv7_read_thumb_16_instr_sxtb(raw); + result = armv7_read_thumb_16_instr_a8_sxtb(raw); else if ((opcode & b1111110) == b0010100) - result = armv7_read_thumb_16_instr_uxth(raw); + result = armv7_read_thumb_16_instr_a8_uxth(raw); else if ((opcode & b1111110) == b0010110) - result = armv7_read_thumb_16_instr_uxtb(raw); + result = armv7_read_thumb_16_instr_a8_uxtb(raw); else if ((opcode & b1111000) == b0011000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); + result = armv7_read_thumb_16_instr_a8_cbnz_cbz(raw); else if ((opcode & b1110000) == b0100000) - result = armv7_read_thumb_16_instr_push(raw); + result = armv7_read_thumb_16_instr_a8_push(raw); else if (opcode == b0110010) - result = armv7_read_thumb_16_instr_setend(raw); + result = armv7_read_thumb_16_instr_a8_setend(raw); else if (opcode == b0110011) - result = armv7_read_thumb_16_instr_cps_thumb(raw); + result = armv7_read_thumb_16_instr_b9_cps_thumb(raw); else if ((opcode & b1111000) == b1001000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); + result = armv7_read_thumb_16_instr_a8_cbnz_cbz(raw); else if ((opcode & b1111110) == b1010000) - result = armv7_read_thumb_16_instr_rev(raw); + result = armv7_read_thumb_16_instr_a8_rev(raw); else if ((opcode & b1111110) == b1010010) - result = armv7_read_thumb_16_instr_rev16(raw); + result = armv7_read_thumb_16_instr_a8_rev16(raw); else if ((opcode & b1111110) == b1010110) - result = armv7_read_thumb_16_instr_revsh(raw); + result = armv7_read_thumb_16_instr_a8_revsh(raw); else if ((opcode & b1111000) == b1011000) - result = armv7_read_thumb_16_instr_cbnz_cbz(raw); + result = armv7_read_thumb_16_instr_a8_cbnz_cbz(raw); else if ((opcode & b1110000) == b1100000) - result = armv7_read_thumb_16_instr_pop_thumb(raw); + result = armv7_read_thumb_16_instr_a8_pop_thumb(raw); else if ((opcode & b1111000) == b1110000) - result = armv7_read_thumb_16_instr_bkpt(raw); + result = armv7_read_thumb_16_instr_a8_bkpt(raw); else if ((opcode & b1111000) == b1111000) result = process_armv7_thumb_16_miscellaneous_16_bit_instructions_if_then_and_hints(raw); @@ -591,29 +591,29 @@ static GArchInstruction *process_armv7_thumb_16_miscellaneous_16_bit_instruction opb = (raw >> 0) & b1111; if (opb != b0000) - result = armv7_read_thumb_16_instr_it(raw); + result = armv7_read_thumb_16_instr_a8_it(raw); else switch (opa) { case b0000: - result = armv7_read_thumb_16_instr_nop(raw); + result = armv7_read_thumb_16_instr_a8_nop(raw); break; case b0001: - result = armv7_read_thumb_16_instr_yield(raw); + result = armv7_read_thumb_16_instr_a8_yield(raw); break; case b0010: - result = armv7_read_thumb_16_instr_wfe(raw); + result = armv7_read_thumb_16_instr_a8_wfe(raw); break; case b0011: - result = armv7_read_thumb_16_instr_wfi(raw); + result = armv7_read_thumb_16_instr_a8_wfi(raw); break; case b0100: - result = armv7_read_thumb_16_instr_sev(raw); + result = armv7_read_thumb_16_instr_a8_sev(raw); break; } @@ -654,15 +654,15 @@ static GArchInstruction *process_armv7_thumb_16_conditional_branch_and_superviso switch (opcode) { case b1110: - result = armv7_read_thumb_16_instr_udf(raw); + result = armv7_read_thumb_16_instr_a8_udf(raw); break; case b1111: - result = armv7_read_thumb_16_instr_svc_previously_swi(raw); + result = armv7_read_thumb_16_instr_a8_svc_previously_swi(raw); break; default: - result = armv7_read_thumb_16_instr_b(raw); + result = armv7_read_thumb_16_instr_a8_b(raw); break; } diff --git a/plugins/arm/v7/thumb_32.c b/plugins/arm/v7/thumb_32.c index 41e5f46..fe06465 100644 --- a/plugins/arm/v7/thumb_32.c +++ b/plugins/arm/v7/thumb_32.c @@ -244,77 +244,77 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia case b0000: if (rds == b11111) - result = armv7_read_thumb_32_instr_tst_immediate(raw); + result = armv7_read_thumb_32_instr_a8_tst_immediate(raw); else - result = armv7_read_thumb_32_instr_and_immediate(raw); + result = armv7_read_thumb_32_instr_a8_and_immediate(raw); break; case b0001: - result = armv7_read_thumb_32_instr_bic_immediate(raw); + result = armv7_read_thumb_32_instr_a8_bic_immediate(raw); break; case b0010: if (rn == b1111) - result = armv7_read_thumb_32_instr_mov_immediate(raw); + result = armv7_read_thumb_32_instr_a8_mov_immediate(raw); else - result = armv7_read_thumb_32_instr_orr_immediate(raw); + result = armv7_read_thumb_32_instr_a8_orr_immediate(raw); break; case b0011: if (rn == b1111) - result = armv7_read_thumb_32_instr_mvn_immediate(raw); + result = armv7_read_thumb_32_instr_a8_mvn_immediate(raw); else - result = armv7_read_thumb_32_instr_orn_immediate(raw); + result = armv7_read_thumb_32_instr_a8_orn_immediate(raw); break; case b0100: if (rds == b11111) - result = armv7_read_thumb_32_instr_teq_immediate(raw); + result = armv7_read_thumb_32_instr_a8_teq_immediate(raw); else - result = armv7_read_thumb_32_instr_eor_immediate(raw); + result = armv7_read_thumb_32_instr_a8_eor_immediate(raw); break; case b1000: if (rds == b11111) - result = armv7_read_thumb_32_instr_cmn_immediate(raw); + result = armv7_read_thumb_32_instr_a8_cmn_immediate(raw); else - result = armv7_read_thumb_32_instr_add_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_add_immediate_thumb(raw); break; case b1010: - result = armv7_read_thumb_32_instr_adc_immediate(raw); + result = armv7_read_thumb_32_instr_a8_adc_immediate(raw); break; case b1011: - result = armv7_read_thumb_32_instr_sbc_immediate(raw); + result = armv7_read_thumb_32_instr_a8_sbc_immediate(raw); break; case b1101: if (rds == b11111) - result = armv7_read_thumb_32_instr_cmp_immediate(raw); + result = armv7_read_thumb_32_instr_a8_cmp_immediate(raw); else - result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_sub_immediate_thumb(raw); break; case b1110: - result = armv7_read_thumb_32_instr_rsb_immediate(raw); + result = armv7_read_thumb_32_instr_a8_rsb_immediate(raw); break; } @@ -359,75 +359,75 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm case b00000: if (rn == b1111) - result = armv7_read_thumb_32_instr_adr(raw); + result = armv7_read_thumb_32_instr_a8_adr(raw); else - result = armv7_read_thumb_32_instr_add_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_add_immediate_thumb(raw); break; case b00100: - result = armv7_read_thumb_32_instr_mov_immediate(raw); + result = armv7_read_thumb_32_instr_a8_mov_immediate(raw); break; case b01010: if (rn == b11111) - result = armv7_read_thumb_32_instr_adr(raw); + result = armv7_read_thumb_32_instr_a8_adr(raw); else - result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_sub_immediate_thumb(raw); break; case b01100: - result = armv7_read_thumb_32_instr_movt(raw); + result = armv7_read_thumb_32_instr_a8_movt(raw); break; case b10000: - result = armv7_read_thumb_32_instr_ssat(raw); + result = armv7_read_thumb_32_instr_a8_ssat(raw); break; case b10010: if ((raw & 0x000070c0) != 0) - result = armv7_read_thumb_32_instr_ssat(raw); + result = armv7_read_thumb_32_instr_a8_ssat(raw); else - result = armv7_read_thumb_32_instr_ssat16(raw); + result = armv7_read_thumb_32_instr_a8_ssat16(raw); break; case b10100: - result = armv7_read_thumb_32_instr_sbfx(raw); + result = armv7_read_thumb_32_instr_a8_sbfx(raw); break; case b10110: if (rn == b11111) - result = armv7_read_thumb_32_instr_bfc(raw); + result = armv7_read_thumb_32_instr_a8_bfc(raw); else - result = armv7_read_thumb_32_instr_bfi(raw); + result = armv7_read_thumb_32_instr_a8_bfi(raw); break; case b11000: - result = armv7_read_thumb_32_instr_usat(raw); + result = armv7_read_thumb_32_instr_a8_usat(raw); break; case b11010: if ((raw & 0x000070c0) != 0) - result = armv7_read_thumb_32_instr_usat(raw); + result = armv7_read_thumb_32_instr_a8_usat(raw); else - result = armv7_read_thumb_32_instr_usat16(raw); + result = armv7_read_thumb_32_instr_a8_usat16(raw); break; case b11100: - result = armv7_read_thumb_32_instr_ubfx(raw); + result = armv7_read_thumb_32_instr_a8_ubfx(raw); break; } @@ -472,30 +472,30 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr imm8 = (raw >> 0) & b11111111; if (op1 == b000 && op == b1111110) - result = armv7_read_thumb_32_instr_hvc(raw); + result = armv7_read_thumb_32_instr_b9_hvc(raw); else if (op1 == b000 && op == b1111111) - result = armv7_read_thumb_32_instr_smc_previously_smi(raw); + result = armv7_read_thumb_32_instr_b9_smc_previously_smi(raw); else if ((op1 & b101) == b000) { if ((op & b0111000) != b0111000) - result = armv7_read_thumb_32_instr_b(raw); + result = armv7_read_thumb_32_instr_a8_b(raw); else if ((imm8 & b00100000) == b00100000 && (op & b1111110) == b0111000) - result = armv7_read_thumb_32_instr_msr_banked_register(raw); + result = armv7_read_thumb_32_instr_b9_msr_banked_register(raw); else if ((imm8 & b00100000) == b00000000 && op == b0111000 && (op2 & b0011) == b0000) - result = armv7_read_thumb_32_instr_msr_register(raw); + result = armv7_read_thumb_32_instr_a8_msr_register(raw); else if ((imm8 & b00100000) == b00000000 && op == b0111000 && (op2 & b0011) == b0001) - result = armv7_read_thumb_32_instr_b_msr_register(raw); + result = armv7_read_thumb_32_instr_b9_msr_register(raw); else if ((imm8 & b00100000) == b00000000 && op == b0111000 && (op2 & b0010) == b0010) - result = armv7_read_thumb_32_instr_b_msr_register(raw); + result = armv7_read_thumb_32_instr_b9_msr_register(raw); else if ((imm8 & b00100000) == b00000000 && op == b0111001) - result = armv7_read_thumb_32_instr_b_msr_register(raw); + result = armv7_read_thumb_32_instr_b9_msr_register(raw); else if (op == b0111010) result = process_armv7_thumb_32_change_processor_state_and_hints(raw); @@ -504,36 +504,36 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr result = process_armv7_thumb_32_miscellaneous_control_instructions(raw); else if (op == b0111100) - result = armv7_read_thumb_32_instr_bxj(raw); + result = armv7_read_thumb_32_instr_a8_bxj(raw); else if (imm8 == b00000000 && op == b0111101) - result = armv7_read_thumb_32_instr_eret(raw); + result = armv7_read_thumb_32_instr_b9_eret(raw); else if (imm8 != b00000000 && op == b0111101) - result = armv7_read_thumb_32_instr_subs_pc_lr_thumb(raw); + result = armv7_read_thumb_32_instr_b9_subs_pc_lr_thumb(raw); else if ((imm8 & b00100000) == b00100000 && (op & b1111110) == b0111110) - result = armv7_read_thumb_32_instr_mrs_banked_register(raw); + result = armv7_read_thumb_32_instr_b9_mrs_banked_register(raw); else if ((imm8 & b00100000) == b00000000 && op == b0111110) - result = armv7_read_thumb_32_instr_mrs(raw); + result = armv7_read_thumb_32_instr_a8_mrs(raw); else if ((imm8 & b00100000) == b00000000 && op == b0111111) - result = armv7_read_thumb_32_instr_b_mrs(raw); + result = armv7_read_thumb_32_instr_b9_mrs(raw); } else if ((op1 & b101) == b001) - result = armv7_read_thumb_32_instr_b(raw); + result = armv7_read_thumb_32_instr_a8_b(raw); else if (op1 == b010 && op == b1111111) - result = armv7_read_thumb_32_instr_udf(raw); + result = armv7_read_thumb_32_instr_a8_udf(raw); else if ((op1 & b101) == b100) - result = armv7_read_thumb_32_instr_bl_blx_immediate(raw); + result = armv7_read_thumb_32_instr_a8_bl_blx_immediate(raw); else if ((op1 & b101) == b101) - result = armv7_read_thumb_32_instr_bl_blx_immediate(raw); + result = armv7_read_thumb_32_instr_a8_bl_blx_immediate(raw); return result; @@ -572,27 +572,27 @@ static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints op2 = (raw >> 0) & b11111111; if (op1 != b000) - result = armv7_read_thumb_32_instr_cps_thumb(raw); + result = armv7_read_thumb_32_instr_b9_cps_thumb(raw); else { if (op2 == b00000000) - result = armv7_read_thumb_32_instr_nop(raw); + result = armv7_read_thumb_32_instr_a8_nop(raw); else if (op2 == b00000001) - result = armv7_read_thumb_32_instr_yield(raw); + result = armv7_read_thumb_32_instr_a8_yield(raw); else if (op2 == b00000010) - result = armv7_read_thumb_32_instr_wfe(raw); + result = armv7_read_thumb_32_instr_a8_wfe(raw); else if (op2 == b00000011) - result = armv7_read_thumb_32_instr_wfi(raw); + result = armv7_read_thumb_32_instr_a8_wfi(raw); else if (op2 == b00000100) - result = armv7_read_thumb_32_instr_sev(raw); + result = armv7_read_thumb_32_instr_a8_sev(raw); else if ((op2 & b11110000) == b11110000) - result = armv7_read_thumb_32_instr_dbg(raw); + result = armv7_read_thumb_32_instr_a8_dbg(raw); } @@ -633,27 +633,27 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructio switch (op) { case b0000: - result = armv7_read_thumb_32_instr_enterx_leavex(raw); + result = armv7_read_thumb_32_instr_a9_enterx_leavex(raw); break; case b0001: - result = armv7_read_thumb_32_instr_enterx_leavex(raw); + result = armv7_read_thumb_32_instr_a9_enterx_leavex(raw); break; case b0010: - result = armv7_read_thumb_32_instr_clrex(raw); + result = armv7_read_thumb_32_instr_a8_clrex(raw); break; case b0100: - result = armv7_read_thumb_32_instr_dsb(raw); + result = armv7_read_thumb_32_instr_a8_dsb(raw); break; case b0101: - result = armv7_read_thumb_32_instr_dmb(raw); + result = armv7_read_thumb_32_instr_a8_dmb(raw); break; case b0110: - result = armv7_read_thumb_32_instr_isb(raw); + result = armv7_read_thumb_32_instr_a8_isb(raw); break; } @@ -700,25 +700,25 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw case b00: if (l == b0) - result = armv7_read_thumb_32_instr_srs_thumb(raw); + result = armv7_read_thumb_32_instr_b9_srs_thumb(raw); else - result = armv7_read_thumb_32_instr_rfe(raw); + result = armv7_read_thumb_32_instr_b9_rfe(raw); break; case b01: if (l == b0) - result = armv7_read_thumb_32_instr_stm_stmia_stmea(raw); + result = armv7_read_thumb_32_instr_a8_stm_stmia_stmea(raw); else { if (wrn == b11101) - result = armv7_read_thumb_32_instr_pop_thumb(raw); + result = armv7_read_thumb_32_instr_a8_pop_thumb(raw); else - result = armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldm_ldmia_ldmfd_thumb(raw); } @@ -729,25 +729,25 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw if (l == b0) { if (wrn == b11101) - result = armv7_read_thumb_32_instr_push(raw); + result = armv7_read_thumb_32_instr_a8_push(raw); else - result = armv7_read_thumb_32_instr_stmdb_stmfd(raw); + result = armv7_read_thumb_32_instr_a8_stmdb_stmfd(raw); } else - result = armv7_read_thumb_32_instr_ldmdb_ldmea(raw); + result = armv7_read_thumb_32_instr_a8_ldmdb_ldmea(raw); break; case b11: if (l == b0) - result = armv7_read_thumb_32_instr_srs_thumb(raw); + result = armv7_read_thumb_32_instr_b9_srs_thumb(raw); else - result = armv7_read_thumb_32_instr_rfe(raw); + result = armv7_read_thumb_32_instr_b9_rfe(raw); break; @@ -793,34 +793,34 @@ static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclu op3 = (raw >> 4) & 0xf; if (op1 == b00 && op2 == b00) - result = armv7_read_thumb_32_instr_strex(raw); + result = armv7_read_thumb_32_instr_a8_strex(raw); else if (op1 == b00 && op2 == b01) - result = armv7_read_thumb_32_instr_ldrex(raw); + result = armv7_read_thumb_32_instr_a8_ldrex(raw); else if ((op1 & b10) == b00 && op2 == b10) - result = armv7_read_thumb_32_instr_strd_immediate(raw); + result = armv7_read_thumb_32_instr_a8_strd_immediate(raw); else if ((op1 & b10) == b10 && (op2 & b01) == b00) - result = armv7_read_thumb_32_instr_strd_immediate(raw); + result = armv7_read_thumb_32_instr_a8_strd_immediate(raw); else if ((op1 & b10) == b00 && op2 == b11) { if (rn != b1111) - result = armv7_read_thumb_32_instr_ldrd_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrd_immediate(raw); else/* if (rn == b1111)*/ - result = armv7_read_thumb_32_instr_ldrd_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldrd_literal(raw); } else if ((op1 & b10) == b10 && (op2 & b01) == b01) { if (rn != b1111) - result = armv7_read_thumb_32_instr_ldrd_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrd_immediate(raw); else/* if (rn == b1111)*/ - result = armv7_read_thumb_32_instr_ldrd_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldrd_literal(raw); } @@ -828,15 +828,15 @@ static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclu switch (op3) { case b0100: - result = armv7_read_thumb_32_instr_strexb(raw); + result = armv7_read_thumb_32_instr_a8_strexb(raw); break; case b0101: - result = armv7_read_thumb_32_instr_strexh(raw); + result = armv7_read_thumb_32_instr_a8_strexh(raw); break; case b0111: - result = armv7_read_thumb_32_instr_strexd(raw); + result = armv7_read_thumb_32_instr_a8_strexd(raw); break; } @@ -845,23 +845,23 @@ static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclu switch (op3) { case b0000: - result = armv7_read_thumb_32_instr_tbb_tbh(raw); + result = armv7_read_thumb_32_instr_a8_tbb_tbh(raw); break; case b0001: - result = armv7_read_thumb_32_instr_tbb_tbh(raw); + result = armv7_read_thumb_32_instr_a8_tbb_tbh(raw); break; case b0100: - result = armv7_read_thumb_32_instr_ldrexb(raw); + result = armv7_read_thumb_32_instr_a8_ldrexb(raw); break; case b0101: - result = armv7_read_thumb_32_instr_ldrexh(raw); + result = armv7_read_thumb_32_instr_a8_ldrexh(raw); break; case b0111: - result = armv7_read_thumb_32_instr_ldrexd(raw); + result = armv7_read_thumb_32_instr_a8_ldrexd(raw); break; } @@ -908,28 +908,28 @@ static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t raw) case b00: if (op2 == b000000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldr_register_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldr_register_thumb(raw); else if ((op2 & b100100) == b100100 && rn != b1111) - result = armv7_read_thumb_32_instr_ldr_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldr_immediate_thumb(raw); else if ((op2 & b111100) == b110000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldr_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldr_immediate_thumb(raw); else if ((op2 & b111100) == b111000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrt(raw); + result = armv7_read_thumb_32_instr_a8_ldrt(raw); break; case b01: if (rn != b1111) - result = armv7_read_thumb_32_instr_ldr_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldr_immediate_thumb(raw); break; } if (result == NULL && (op1 & b10) == b00 && rn == b1111) - result = armv7_read_thumb_32_instr_ldr_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldr_literal(raw); return result; @@ -975,17 +975,17 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3 if ((op1 & b10) == b00) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldrh_literal(raw); else/* if (rt == b1111)*/ - result = armv7_read_thumb_32_instr_pld_literal(raw); + result = armv7_read_thumb_32_instr_a8_pld_literal(raw); } else/* if ((op1 & b10) == b10)*/ { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldrsh_literal(raw); else/* if (rt == b1111)*/ result = g_undef_instruction_new(IBS_NOP); @@ -999,48 +999,48 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3 if (op1 == b00) { if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldrh_immediate_thumb(raw); else if ((op2 & b111100) == b110000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldrh_immediate_thumb(raw); else if (op2 == b000000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_register(raw); + result = armv7_read_thumb_32_instr_a8_ldrh_register(raw); else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_ldrht(raw); + result = armv7_read_thumb_32_instr_a8_ldrht(raw); else if (op2 == b000000 && rt == b1111) - result = armv7_read_thumb_32_instr_pld_pldw_register(raw); + result = armv7_read_thumb_32_instr_a8_pld_pldw_register(raw); else if ((op2 & b111100) == b110000 && rt == b1111) - result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw); + result = armv7_read_thumb_32_instr_a8_pld_pldw_immediate(raw); } else if (op1 == b01) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldrh_immediate_thumb(raw); else/* if (rt == b1111)*/ - result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw); + result = armv7_read_thumb_32_instr_a8_pld_pldw_immediate(raw); } else if (op1 == b10) { if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrsh_immediate(raw); else if ((op2 & b111100) == b110000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrsh_immediate(raw); else if (op2 == b000000 && rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_register(raw); + result = armv7_read_thumb_32_instr_a8_ldrsh_register(raw); else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_ldrsht(raw); + result = armv7_read_thumb_32_instr_a8_ldrsht(raw); else if (op2 == b000000 && rt == b1111) result = g_undef_instruction_new(IBS_NOP); @@ -1053,7 +1053,7 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3 else if (op1 == b11) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrsh_immediate(raw); else/* if (rt == b1111)*/ result = g_undef_instruction_new(IBS_NOP); @@ -1104,90 +1104,90 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t if (op1 == b00 && op2 == b000000 && rn != b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_register(raw); + result = armv7_read_thumb_32_instr_a8_ldrb_register(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_register(raw); + result = armv7_read_thumb_32_instr_a8_pld_register(raw); } else if ((op1 & b10) == b00 && rn == b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldrb_literal(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_literal(raw); + result = armv7_read_thumb_32_instr_a8_pld_literal(raw); } else if (op1 == b00 && (op2 & b100100) == b100100 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldrb_immediate_thumb(raw); else if (op1 == b00 && (op2 & b111100) == b110000 && rn != b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldrb_immediate_thumb(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_immediate(raw); + result = armv7_read_thumb_32_instr_a8_pld_immediate(raw); } else if (op1 == b00 && (op2 & b111100) == b111000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrbt(raw); + result = armv7_read_thumb_32_instr_a8_ldrbt(raw); else if (op1 == b01 && rn != b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_ldrb_immediate_thumb(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pld_immediate(raw); + result = armv7_read_thumb_32_instr_a8_pld_immediate(raw); } if (op1 == b10 && op2 == b000000 && rn != b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_register(raw); + result = armv7_read_thumb_32_instr_a8_ldrsb_register(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_register(raw); + result = armv7_read_thumb_32_instr_a8_pli_register(raw); } else if ((op1 & b10) == b10 && rn == b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldrsb_literal(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); + result = armv7_read_thumb_32_instr_a8_pli_immediate_literal(raw); } else if (op1 == b10 && (op2 & b100100) == b100100 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrsb_immediate(raw); else if (op1 == b10 && (op2 & b111100) == b110000 && rn != b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrsb_immediate(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); + result = armv7_read_thumb_32_instr_a8_pli_immediate_literal(raw); } else if (op1 == b10 && (op2 & b111100) == b111000 && rn != b1111) - result = armv7_read_thumb_32_instr_ldrsbt(raw); + result = armv7_read_thumb_32_instr_a8_ldrsbt(raw); else if (op1 == b11 && rn != b1111) { if (rt != b1111) - result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldrsb_immediate(raw); else /*if (rt == b1111) */ - result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); + result = armv7_read_thumb_32_instr_a8_pli_immediate_literal(raw); } @@ -1231,61 +1231,61 @@ static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t case b000: if (op2 == b000000) - result = armv7_read_thumb_32_instr_strb_register(raw); + result = armv7_read_thumb_32_instr_a8_strb_register(raw); else if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_strb_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_strb_immediate_thumb(raw); else if ((op2 & b111100) == b110000) - result = armv7_read_thumb_32_instr_strb_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_strb_immediate_thumb(raw); else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_strbt(raw); + result = armv7_read_thumb_32_instr_a8_strbt(raw); break; case b001: if (op2 == b000000) - result = armv7_read_thumb_32_instr_strh_register(raw); + result = armv7_read_thumb_32_instr_a8_strh_register(raw); else if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_strh_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_strh_immediate_thumb(raw); else if ((op2 & b111100) == b110000) - result = armv7_read_thumb_32_instr_strh_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_strh_immediate_thumb(raw); else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_strht(raw); + result = armv7_read_thumb_32_instr_a8_strht(raw); break; case b010: if (op2 == b000000) - result = armv7_read_thumb_32_instr_str_register(raw); + result = armv7_read_thumb_32_instr_a8_str_register(raw); else if ((op2 & b100100) == b100100) - result = armv7_read_thumb_32_instr_str_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_str_immediate_thumb(raw); else if ((op2 & b111100) == b110000) - result = armv7_read_thumb_32_instr_str_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_str_immediate_thumb(raw); else if ((op2 & b111100) == b111000) - result = armv7_read_thumb_32_instr_strt(raw); + result = armv7_read_thumb_32_instr_a8_strt(raw); break; case b100: - result = armv7_read_thumb_32_instr_strb_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_strb_immediate_thumb(raw); break; case b101: - result = armv7_read_thumb_32_instr_strh_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_strh_immediate_thumb(raw); break; case b110: - result = armv7_read_thumb_32_instr_str_immediate_thumb(raw); + result = armv7_read_thumb_32_instr_a8_str_immediate_thumb(raw); break; } @@ -1332,15 +1332,15 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register case b0000: if (rds == b11111) - result = armv7_read_thumb_32_instr_tst_register(raw); + result = armv7_read_thumb_32_instr_a8_tst_register(raw); else - result = armv7_read_thumb_32_instr_and_register(raw); + result = armv7_read_thumb_32_instr_a8_and_register(raw); break; case b0001: - result = armv7_read_thumb_32_instr_bic_register(raw); + result = armv7_read_thumb_32_instr_a8_bic_register(raw); break; case b0010: @@ -1349,64 +1349,64 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register result = process_armv7_thumb_32_move_register_and_immediate_shifts(raw); else - result = armv7_read_thumb_32_instr_orr_register(raw); + result = armv7_read_thumb_32_instr_a8_orr_register(raw); break; case b0011: if (rn == b11111) - result = armv7_read_thumb_32_instr_mvn_register(raw); + result = armv7_read_thumb_32_instr_a8_mvn_register(raw); else - result = armv7_read_thumb_32_instr_orn_register(raw); + result = armv7_read_thumb_32_instr_a8_orn_register(raw); break; case b0100: if (rds == b11111) - result = armv7_read_thumb_32_instr_teq_register(raw); + result = armv7_read_thumb_32_instr_a8_teq_register(raw); else - result = armv7_read_thumb_32_instr_eor_register(raw); + result = armv7_read_thumb_32_instr_a8_eor_register(raw); break; case b0110: - result = armv7_read_thumb_32_instr_pkh(raw); + result = armv7_read_thumb_32_instr_a8_pkh(raw); break; case b1000: if (rds == b11111) - result = armv7_read_thumb_32_instr_cmn_register(raw); + result = armv7_read_thumb_32_instr_a8_cmn_register(raw); else - result = armv7_read_thumb_32_instr_add_register_thumb(raw); + result = armv7_read_thumb_32_instr_a8_add_register_thumb(raw); break; case b1010: - result = armv7_read_thumb_32_instr_adc_register(raw); + result = armv7_read_thumb_32_instr_a8_adc_register(raw); break; case b1011: - result = armv7_read_thumb_32_instr_sbc_register(raw); + result = armv7_read_thumb_32_instr_a8_sbc_register(raw); break; case b1101: if (rds == b11111) - result = armv7_read_thumb_32_instr_cmp_register(raw); + result = armv7_read_thumb_32_instr_a8_cmp_register(raw); else - result = armv7_read_thumb_32_instr_sub_register_thumb(raw); + result = armv7_read_thumb_32_instr_a8_sub_register_thumb(raw); break; case b1110: - result = armv7_read_thumb_32_instr_rsb_register(raw); + result = armv7_read_thumb_32_instr_a8_rsb_register(raw); break; } @@ -1452,28 +1452,28 @@ static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shif case b00: if (imm5 == b00000) - result = armv7_read_thumb_32_instr_mov_register_thumb(raw); + result = armv7_read_thumb_32_instr_a8_mov_register_thumb(raw); else/* if (imm5 != b00000)*/ - result = armv7_read_thumb_32_instr_lsl_immediate(raw); + result = armv7_read_thumb_32_instr_a8_lsl_immediate(raw); break; case b01: - result = armv7_read_thumb_32_instr_lsr_immediate(raw); + result = armv7_read_thumb_32_instr_a8_lsr_immediate(raw); break; case b10: - result = armv7_read_thumb_32_instr_asr_immediate(raw); + result = armv7_read_thumb_32_instr_a8_asr_immediate(raw); break; case b11: if (imm5 == b00000) - result = armv7_read_thumb_32_instr_rrx(raw); + result = armv7_read_thumb_32_instr_a8_rrx(raw); else/* if (imm5 != b00000)*/ - result = armv7_read_thumb_32_instr_ror_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ror_immediate(raw); break; @@ -1517,74 +1517,74 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_ op2 = (raw >> 4) & b1111; if ((op1 & b1110) == b0000 && op2 == b0000) - result = armv7_read_thumb_32_instr_lsl_register(raw); + result = armv7_read_thumb_32_instr_a8_lsl_register(raw); else if ((op1 & b1110) == b0010 && op2 == b0000) - result = armv7_read_thumb_32_instr_lsr_register(raw); + result = armv7_read_thumb_32_instr_a8_lsr_register(raw); else if ((op1 & b1110) == b0100 && op2 == b0000) - result = armv7_read_thumb_32_instr_asr_register(raw); + result = armv7_read_thumb_32_instr_a8_asr_register(raw); else if ((op1 & b1110) == b0110 && op2 == b0000) - result = armv7_read_thumb_32_instr_ror_register(raw); + result = armv7_read_thumb_32_instr_a8_ror_register(raw); else if (op1 == b0000 && (op2 & b1000) == b1000) { if (rn == b1111) - result = armv7_read_thumb_32_instr_sxth(raw); + result = armv7_read_thumb_32_instr_a8_sxth(raw); else - result = armv7_read_thumb_32_instr_sxtah(raw); + result = armv7_read_thumb_32_instr_a8_sxtah(raw); } else if (op1 == b0001 && (op2 & b1000) == b1000) { if (rn == b1111) - result = armv7_read_thumb_32_instr_uxth(raw); + result = armv7_read_thumb_32_instr_a8_uxth(raw); else - result = armv7_read_thumb_32_instr_uxtah(raw); + result = armv7_read_thumb_32_instr_a8_uxtah(raw); } else if (op1 == b0010 && (op2 & b1000) == b1000) { if (rn == b1111) - result = armv7_read_thumb_32_instr_sxtb16(raw); + result = armv7_read_thumb_32_instr_a8_sxtb16(raw); else - result = armv7_read_thumb_32_instr_sxtab16(raw); + result = armv7_read_thumb_32_instr_a8_sxtab16(raw); } else if (op1 == b0011 && (op2 & b1000) == b1000) { if (rn == b1111) - result = armv7_read_thumb_32_instr_uxtb16(raw); + result = armv7_read_thumb_32_instr_a8_uxtb16(raw); else - result = armv7_read_thumb_32_instr_uxtab16(raw); + result = armv7_read_thumb_32_instr_a8_uxtab16(raw); } else if (op1 == b0100 && (op2 & b1000) == b1000) { if (rn == b1111) - result = armv7_read_thumb_32_instr_sxtb(raw); + result = armv7_read_thumb_32_instr_a8_sxtb(raw); else - result = armv7_read_thumb_32_instr_sxtab(raw); + result = armv7_read_thumb_32_instr_a8_sxtab(raw); } else if (op1 == b0101 && (op2 & b1000) == b1000) { if (rn == b1111) - result = armv7_read_thumb_32_instr_uxtb(raw); + result = armv7_read_thumb_32_instr_a8_uxtb(raw); else - result = armv7_read_thumb_32_instr_uxtab(raw); + result = armv7_read_thumb_32_instr_a8_uxtab(raw); } @@ -1638,27 +1638,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio switch (op1) { case b001: - result = armv7_read_thumb_32_instr_sadd16(raw); + result = armv7_read_thumb_32_instr_a8_sadd16(raw); break; case b010: - result = armv7_read_thumb_32_instr_sasx(raw); + result = armv7_read_thumb_32_instr_a8_sasx(raw); break; case b110: - result = armv7_read_thumb_32_instr_ssax(raw); + result = armv7_read_thumb_32_instr_a8_ssax(raw); break; case b101: - result = armv7_read_thumb_32_instr_ssub16(raw); + result = armv7_read_thumb_32_instr_a8_ssub16(raw); break; case b000: - result = armv7_read_thumb_32_instr_sadd8(raw); + result = armv7_read_thumb_32_instr_a8_sadd8(raw); break; case b100: - result = armv7_read_thumb_32_instr_ssub8(raw); + result = armv7_read_thumb_32_instr_a8_ssub8(raw); break; } @@ -1668,27 +1668,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio switch (op1) { case b001: - result = armv7_read_thumb_32_instr_sqadd16(raw); + result = armv7_read_thumb_32_instr_a8_sqadd16(raw); break; case b010: - result = armv7_read_thumb_32_instr_sqasx(raw); + result = armv7_read_thumb_32_instr_a8_sqasx(raw); break; case b110: - result = armv7_read_thumb_32_instr_sqsax(raw); + result = armv7_read_thumb_32_instr_a8_sqsax(raw); break; case b101: - result = armv7_read_thumb_32_instr_sqsub16(raw); + result = armv7_read_thumb_32_instr_a8_sqsub16(raw); break; case b000: - result = armv7_read_thumb_32_instr_sqadd8(raw); + result = armv7_read_thumb_32_instr_a8_sqadd8(raw); break; case b100: - result = armv7_read_thumb_32_instr_sqsub8(raw); + result = armv7_read_thumb_32_instr_a8_sqsub8(raw); break; } @@ -1698,27 +1698,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio switch (op1) { case b001: - result = armv7_read_thumb_32_instr_shadd16(raw); + result = armv7_read_thumb_32_instr_a8_shadd16(raw); break; case b010: - result = armv7_read_thumb_32_instr_shasx(raw); + result = armv7_read_thumb_32_instr_a8_shasx(raw); break; case b110: - result = armv7_read_thumb_32_instr_shsax(raw); + result = armv7_read_thumb_32_instr_a8_shsax(raw); break; case b101: - result = armv7_read_thumb_32_instr_shsub16(raw); + result = armv7_read_thumb_32_instr_a8_shsub16(raw); break; case b000: - result = armv7_read_thumb_32_instr_shadd8(raw); + result = armv7_read_thumb_32_instr_a8_shadd8(raw); break; case b100: - result = armv7_read_thumb_32_instr_shsub8(raw); + result = armv7_read_thumb_32_instr_a8_shsub8(raw); break; } @@ -1767,27 +1767,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio switch (op1) { case b001: - result = armv7_read_thumb_32_instr_uadd16(raw); + result = armv7_read_thumb_32_instr_a8_uadd16(raw); break; case b010: - result = armv7_read_thumb_32_instr_uasx(raw); + result = armv7_read_thumb_32_instr_a8_uasx(raw); break; case b110: - result = armv7_read_thumb_32_instr_usax(raw); + result = armv7_read_thumb_32_instr_a8_usax(raw); break; case b101: - result = armv7_read_thumb_32_instr_usub16(raw); + result = armv7_read_thumb_32_instr_a8_usub16(raw); break; case b000: - result = armv7_read_thumb_32_instr_uadd8(raw); + result = armv7_read_thumb_32_instr_a8_uadd8(raw); break; case b100: - result = armv7_read_thumb_32_instr_usub8(raw); + result = armv7_read_thumb_32_instr_a8_usub8(raw); break; } @@ -1797,27 +1797,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio switch (op1) { case b001: - result = armv7_read_thumb_32_instr_uqadd16(raw); + result = armv7_read_thumb_32_instr_a8_uqadd16(raw); break; case b010: - result = armv7_read_thumb_32_instr_uqasx(raw); + result = armv7_read_thumb_32_instr_a8_uqasx(raw); break; case b110: - result = armv7_read_thumb_32_instr_uqsax(raw); + result = armv7_read_thumb_32_instr_a8_uqsax(raw); break; case b101: - result = armv7_read_thumb_32_instr_uqsub16(raw); + result = armv7_read_thumb_32_instr_a8_uqsub16(raw); break; case b000: - result = armv7_read_thumb_32_instr_uqadd8(raw); + result = armv7_read_thumb_32_instr_a8_uqadd8(raw); break; case b100: - result = armv7_read_thumb_32_instr_uqsub8(raw); + result = armv7_read_thumb_32_instr_a8_uqsub8(raw); break; } @@ -1827,27 +1827,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio switch (op1) { case b001: - result = armv7_read_thumb_32_instr_uhadd16(raw); + result = armv7_read_thumb_32_instr_a8_uhadd16(raw); break; case b010: - result = armv7_read_thumb_32_instr_uhasx(raw); + result = armv7_read_thumb_32_instr_a8_uhasx(raw); break; case b110: - result = armv7_read_thumb_32_instr_uhsax(raw); + result = armv7_read_thumb_32_instr_a8_uhsax(raw); break; case b101: - result = armv7_read_thumb_32_instr_uhsub16(raw); + result = armv7_read_thumb_32_instr_a8_uhsub16(raw); break; case b000: - result = armv7_read_thumb_32_instr_uhadd8(raw); + result = armv7_read_thumb_32_instr_a8_uhadd8(raw); break; case b100: - result = armv7_read_thumb_32_instr_uhsub8(raw); + result = armv7_read_thumb_32_instr_a8_uhsub8(raw); break; } @@ -1896,19 +1896,19 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_ switch (op2) { case b00: - result = armv7_read_thumb_32_instr_qadd(raw); + result = armv7_read_thumb_32_instr_a8_qadd(raw); break; case b01: - result = armv7_read_thumb_32_instr_qdadd(raw); + result = armv7_read_thumb_32_instr_a8_qdadd(raw); break; case b10: - result = armv7_read_thumb_32_instr_qsub(raw); + result = armv7_read_thumb_32_instr_a8_qsub(raw); break; case b11: - result = armv7_read_thumb_32_instr_qdsub(raw); + result = armv7_read_thumb_32_instr_a8_qdsub(raw); break; } @@ -1918,19 +1918,19 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_ switch (op2) { case b00: - result = armv7_read_thumb_32_instr_rev(raw); + result = armv7_read_thumb_32_instr_a8_rev(raw); break; case b01: - result = armv7_read_thumb_32_instr_rev16(raw); + result = armv7_read_thumb_32_instr_a8_rev16(raw); break; case b10: - result = armv7_read_thumb_32_instr_rbit(raw); + result = armv7_read_thumb_32_instr_a8_rbit(raw); break; case b11: - result = armv7_read_thumb_32_instr_revsh(raw); + result = armv7_read_thumb_32_instr_a8_revsh(raw); break; } @@ -1938,12 +1938,12 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_ case b10: if (op2 == b00) - result = armv7_read_thumb_32_instr_sel(raw); + result = armv7_read_thumb_32_instr_a8_sel(raw); break; case b11: if (op2 == b00) - result = armv7_read_thumb_32_instr_clz(raw); + result = armv7_read_thumb_32_instr_a8_clz(raw); break; } @@ -1992,25 +1992,25 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and if (op2 == b00) { if (ra == b1111) - result = armv7_read_thumb_32_instr_mul(raw); + result = armv7_read_thumb_32_instr_a8_mul(raw); else - result = armv7_read_thumb_32_instr_mla(raw); + result = armv7_read_thumb_32_instr_a8_mla(raw); } else if (op2 == b01) - result = armv7_read_thumb_32_instr_mls(raw); + result = armv7_read_thumb_32_instr_a8_mls(raw); break; case b001: if (ra == b1111) - result = armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(raw); + result = armv7_read_thumb_32_instr_a8_smulbb_smulbt_smultb_smultt(raw); else - result = armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(raw); + result = armv7_read_thumb_32_instr_a8_smlabb_smlabt_smlatb_smlatt(raw); break; @@ -2018,10 +2018,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and if ((op2 & b10) == b00) { if (ra == b1111) - result = armv7_read_thumb_32_instr_smuad(raw); + result = armv7_read_thumb_32_instr_a8_smuad(raw); else - result = armv7_read_thumb_32_instr_smlad(raw); + result = armv7_read_thumb_32_instr_a8_smlad(raw); } break; @@ -2030,10 +2030,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and if ((op2 & b10) == b00) { if (ra == b1111) - result = armv7_read_thumb_32_instr_smulwb_smulwt(raw); + result = armv7_read_thumb_32_instr_a8_smulwb_smulwt(raw); else - result = armv7_read_thumb_32_instr_smlawb_smlawt(raw); + result = armv7_read_thumb_32_instr_a8_smlawb_smlawt(raw); } break; @@ -2042,10 +2042,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and if ((op2 & b10) == b00) { if (ra == b1111) - result = armv7_read_thumb_32_instr_smusd(raw); + result = armv7_read_thumb_32_instr_a8_smusd(raw); else - result = armv7_read_thumb_32_instr_smlsd(raw); + result = armv7_read_thumb_32_instr_a8_smlsd(raw); } break; @@ -2054,27 +2054,27 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and if ((op2 & b10) == b00) { if (ra == b1111) - result = armv7_read_thumb_32_instr_smmul(raw); + result = armv7_read_thumb_32_instr_a8_smmul(raw); else - result = armv7_read_thumb_32_instr_smmla(raw); + result = armv7_read_thumb_32_instr_a8_smmla(raw); } break; case b110: if ((op2 & b10) == b00) - result = armv7_read_thumb_32_instr_smmls(raw); + result = armv7_read_thumb_32_instr_a8_smmls(raw); break; case b111: if (op2 == b00) { if (ra == b1111) - result = armv7_read_thumb_32_instr_usad8(raw); + result = armv7_read_thumb_32_instr_a8_usad8(raw); else - result = armv7_read_thumb_32_instr_usada8(raw); + result = armv7_read_thumb_32_instr_a8_usada8(raw); } break; @@ -2120,49 +2120,49 @@ static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accu { case b000: if (op2 == b0000) - result = armv7_read_thumb_32_instr_smull(raw); + result = armv7_read_thumb_32_instr_a8_smull(raw); break; case b001: if (op2 == b1111) - result = armv7_read_thumb_32_instr_sdiv(raw); + result = armv7_read_thumb_32_instr_a8_sdiv(raw); break; case b010: if (op2 == b0000) - result = armv7_read_thumb_32_instr_umull(raw); + result = armv7_read_thumb_32_instr_a8_umull(raw); break; case b011: if (op2 == b1111) - result = armv7_read_thumb_32_instr_udiv(raw); + result = armv7_read_thumb_32_instr_a8_udiv(raw); break; case b100: if (op2 == b0000) - result = armv7_read_thumb_32_instr_smlal(raw); + result = armv7_read_thumb_32_instr_a8_smlal(raw); else if ((op2 & b1100) == b1000) - result = armv7_read_thumb_32_instr_smlalbb_smlalbt_smlaltb_smlaltt(raw); + result = armv7_read_thumb_32_instr_a8_smlalbb_smlalbt_smlaltb_smlaltt(raw); else if ((op2 & b1110) == b1100) - result = armv7_read_thumb_32_instr_smlald(raw); + result = armv7_read_thumb_32_instr_a8_smlald(raw); break; case b101: if ((op2 & b1110) == b1100) - result = armv7_read_thumb_32_instr_smlsld(raw); + result = armv7_read_thumb_32_instr_a8_smlsld(raw); break; case b110: if (op2 == b0000) - result = armv7_read_thumb_32_instr_umlal(raw); + result = armv7_read_thumb_32_instr_a8_umlal(raw); else if (op2 == b0110) - result = armv7_read_thumb_32_instr_umaal(raw); + result = armv7_read_thumb_32_instr_a8_umaal(raw); break; @@ -2216,32 +2216,32 @@ static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_fl else if ((coproc & b1110) != b1010) { if ((op1 & b100001) == b000000 && (op1 & b111010) != b000000) - result = armv7_read_thumb_32_instr_stc_stc2(raw); + result = armv7_read_thumb_32_instr_a8_stc_stc2(raw); else if ((op1 & b100001) == b000001 && (op1 & b111010) != b000000) { if (rn != b1111) - result = armv7_read_thumb_32_instr_ldc_ldc2_immediate(raw); + result = armv7_read_thumb_32_instr_a8_ldc_ldc2_immediate(raw); else/* if (rn == b1111)*/ - result = armv7_read_thumb_32_instr_ldc_ldc2_literal(raw); + result = armv7_read_thumb_32_instr_a8_ldc_ldc2_literal(raw); } else if (op1 == b000100) - result = armv7_read_thumb_32_instr_mcrr_mcrr2(raw); + result = armv7_read_thumb_32_instr_a8_mcrr_mcrr2(raw); else if (op1 == b000101) - result = armv7_read_thumb_32_instr_mrrc_mrrc2(raw); + result = armv7_read_thumb_32_instr_a8_mrrc_mrrc2(raw); else if ((op1 & b110000) == b100000 && op == b0) - result = armv7_read_thumb_32_instr_cdp_cdp2(raw); + result = armv7_read_thumb_32_instr_a8_cdp_cdp2(raw); else if ((op1 & b110001) == b100000 && op == b1) - result = armv7_read_thumb_32_instr_mcr_mcr2(raw); + result = armv7_read_thumb_32_instr_a8_mcr_mcr2(raw); else if ((op1 & b110001) == b100001 && op == b1) - result = armv7_read_thumb_32_instr_mrc_mrc2(raw); + result = armv7_read_thumb_32_instr_a8_mrc_mrc2(raw); } diff --git a/tools/d2c/coder.c b/tools/d2c/coder.c index 2e02e47..cd64d88 100644 --- a/tools/d2c/coder.c +++ b/tools/d2c/coder.c @@ -26,6 +26,7 @@ #include #include +#include #include #include #include @@ -99,7 +100,7 @@ static void init_coder_opcodes_file(int, const output_info *, const char *); static void init_coder_code_file(int, const char *); /* Centralise l'impression du nom de fonction de désassemblage. */ -static void write_read_function_name(int fd, const char *, const string_exch *, const char *); +static void write_read_function_name(const rented_coder *, const output_info *, int, const string_exch *); /* Génère ou complète un fichier contenant le code C principal. */ static bool output_coder_raw(const rented_coder *, const output_info *, const string_exch *, const encoding_spec *, int, int); @@ -523,6 +524,55 @@ void mark_coder_as_useless(rented_coder *coder) /****************************************************************************** * * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * +* * +* Description : Crée la désignation principale d'une instruction. * +* * +* Retour : Identifiant à libérer après usage. * +* * +* Remarques : - * +* * +******************************************************************************/ + +char *build_coder_main_identifier(const rented_coder *coder, const output_info *info) +{ + char *result; /* Chaîne construite à renvoyer*/ + char *filename; /* Nom de fichier modifiable */ + char *sub; /* Compartimentage à insérer */ + char *name; /* Désignation à manipuler */ + + if (info->filename_reuse > 0) + { + filename = strdup(coder->input); + + sub = basename(filename); + + if (info->filename_reuse < strlen(sub)) + sub[info->filename_reuse] = '\0'; + + } + + name = get_coder_code_name(coder); + make_string_upper(name); + + if (info->filename_reuse > 0) + asprintf(&result, "%s_%s_%s", info->id_prefix, sub, name); + else + asprintf(&result, "%s_%s", info->id_prefix, name); + + free(name); + + if (info->filename_reuse > 0) + free(filename); + + return result; + +} + + +/****************************************************************************** +* * * Paramètres : coder = gestion par la machine en remplacement de l'humain. * * info = précisions quant à la génération. * * prefix = type d'encodage à répercuter sur le nom de fichier. * @@ -994,10 +1044,10 @@ bool output_coder_body(const rented_coder *coder, const output_info *info) /****************************************************************************** * * -* Paramètres : fd = flux ouvert en écriture. * -* arch = architecture en cours de traitement. * -* sub = encodage choisi comme sous-ensemble d'architecture. * -* name = désignation complète d'une instruction. * +* Paramètres : coder = gestion automatique de l'écriture de code. * +* info = précisions quant à la génération. * +* fd = flux ouvert en écriture. * +* enc = encodage choisi comme sous-ensemble d'architecture. * * * * Description : Centralise l'impression du nom de fonction de désassemblage. * * * @@ -1007,12 +1057,53 @@ bool output_coder_body(const rented_coder *coder, const output_info *info) * * ******************************************************************************/ -static void write_read_function_name(int fd, const char *arch, const string_exch *sub, const char *name) +static void write_read_function_name(const rented_coder *coder, const output_info *info, int fd, const string_exch *enc) { - if (sub->dest == NULL) - dprintf(fd, "%s_read_instr_%s", arch, name); + char *arch; /* Architecture à traiter */ + char *filename; /* Nom de fichier modifiable */ + char *sub; /* Compartimentage à insérer */ + char *name; /* Désignation à manipuler */ + + /* Préparations */ + + arch = strdup(info->arch_cn); + make_string_lower(arch); + + if (info->filename_reuse > 0) + { + filename = strdup(coder->input); + + sub = basename(filename); + + if (info->filename_reuse < strlen(sub)) + sub[info->filename_reuse] = '\0'; + + make_string_lower(sub); + + } + + name = get_coder_code_name(coder); + + /* Impressions */ + + if (enc->dest == NULL) + dprintf(fd, "%s_read_instr", arch); else - dprintf(fd, "%s_read_%s_instr_%s", arch, sub->dest, name); + dprintf(fd, "%s_read_%s_instr", arch, enc->dest); + + if (info->filename_reuse > 0) + dprintf(fd, "_%s", sub); + + dprintf(fd, "_%s", name); + + /* Sortie propre */ + + free(name); + + if (info->filename_reuse > 0) + free(filename); + + free(arch); } @@ -1038,18 +1129,15 @@ static bool output_coder_raw(const rented_coder *coder, const output_info *info, { bool result; /* Bilan à retourner */ char *arch; /* Architecture à traiter */ - char *name; /* Désignation à manipuler */ char *prefix; /* Préfixe employé en suffixe */ coding_bits *bits; /* Gestionnaire de bits */ unsigned int wide; /* Taille des mots */ size_t maxlen; /* Taille à compléter */ - char *fullname; /* Désignation complète */ + char *constant; /* Définition d'une constante */ arch = strdup(info->arch_cn); make_string_lower(arch); - name = get_coder_code_name(coder); - prefix = build_encoding_spec_prefix(encoding); bits = get_bits_in_encoding_spec(encoding); @@ -1062,7 +1150,7 @@ static bool output_coder_raw(const rented_coder *coder, const output_info *info, dprintf(hfd, "/* Décode une forme d'instruction de type '%s'. */\n", coder->ins); dprintf(hfd, "GArchInstruction *"); - write_read_function_name(hfd, arch, enc_name, name); + write_read_function_name(coder, info, hfd, enc_name); dprintf(hfd, "_%s", prefix); dprintf(hfd, "("); @@ -1101,7 +1189,7 @@ static bool output_coder_raw(const rented_coder *coder, const output_info *info, dprintf(cfd, "static "); dprintf(cfd, "GArchInstruction *"); - write_read_function_name(cfd, arch, enc_name, name); + write_read_function_name(coder, info, cfd, enc_name); dprintf(cfd, "_%s", prefix); dprintf(cfd, "("); @@ -1112,13 +1200,11 @@ static bool output_coder_raw(const rented_coder *coder, const output_info *info, dprintf(cfd, "{"); dprintf(cfd, "\n"); - make_string_upper(name); - - asprintf(&fullname, "%s_%s", info->id_prefix, name); + constant = build_coder_main_identifier(coder, info); - result = write_encoding_spec_raw_disass(encoding, cfd, arch, fullname, coder->pp); + result = write_encoding_spec_raw_disass(encoding, cfd, arch, constant, coder->pp); - free(fullname); + free(constant); dprintf(cfd, "}\n"); dprintf(cfd, "\n"); @@ -1127,8 +1213,6 @@ static bool output_coder_raw(const rented_coder *coder, const output_info *info, free(prefix); - free(name); - free(arch); return result; @@ -1155,8 +1239,6 @@ static bool output_coder_raw(const rented_coder *coder, const output_info *info, static bool output_coder_main_raw(const rented_coder *coder, const output_info *info, const string_exch *enc_name, int hfd, int cfd) { bool result; /* Bilan à retourner */ - char *arch; /* Architecture à traiter */ - char *name; /* Désignation à manipuler */ unsigned int wide; /* Taille des mots */ size_t maxlen; /* Taille à compléter */ bool first; /* Note un premier appel */ @@ -1165,11 +1247,6 @@ static bool output_coder_main_raw(const rented_coder *coder, const output_info * result = false; - arch = strdup(info->arch_cn); - make_string_lower(arch); - - name = get_coder_code_name(coder); - wide = get_bit_width_for_encoding_spec(coder, enc_name); /* Désassemblage : déclaration */ @@ -1177,7 +1254,7 @@ static bool output_coder_main_raw(const rented_coder *coder, const output_info * dprintf(hfd, "/* Décode une instruction de type '%s'. */\n", coder->ins); dprintf(hfd, "GArchInstruction *"); - write_read_function_name(hfd, arch, enc_name, name); + write_read_function_name(coder, info, hfd, enc_name); dprintf(hfd, "("); dprintf(hfd, "uint%u_t raw", wide); @@ -1210,7 +1287,7 @@ static bool output_coder_main_raw(const rented_coder *coder, const output_info * dprintf(cfd, "\n"); dprintf(cfd, "GArchInstruction *"); - write_read_function_name(cfd, arch, enc_name, name); + write_read_function_name(coder, info, cfd, enc_name); dprintf(cfd, "("); dprintf(cfd, "uint%u_t raw", wide); @@ -1237,7 +1314,7 @@ static bool output_coder_main_raw(const rented_coder *coder, const output_info * if (first) { dprintf(cfd, "\tresult = "); - write_read_function_name(cfd, arch, enc_name, name); + write_read_function_name(coder, info, cfd, enc_name); dprintf(cfd, "_%s(raw);\n", prefix); dprintf(cfd, "\n"); @@ -1250,7 +1327,7 @@ static bool output_coder_main_raw(const rented_coder *coder, const output_info * dprintf(cfd, "\tif (result == NULL)\n"); dprintf(cfd, "\t\tresult = "); - write_read_function_name(cfd, arch, enc_name, name); + write_read_function_name(coder, info, cfd, enc_name); dprintf(cfd, "_%s(raw);\n", prefix); dprintf(cfd, "\n"); @@ -1267,12 +1344,6 @@ static bool output_coder_main_raw(const rented_coder *coder, const output_info * dprintf(cfd, "}\n"); dprintf(cfd, "\n"); - /* Conclusion */ - - free(name); - - free(arch); - return result; } @@ -1299,21 +1370,18 @@ static bool output_coder_format(const rented_coder *coder, const output_info *in { bool result; /* Bilan à retourner */ char *arch; /* Architecture à traiter */ - char *name; /* Désignation à manipuler */ size_t maxlen; /* Taille à compléter */ - char *fullname; /* Désignation complète */ + char *constant; /* Définition d'une constante */ arch = strdup(info->arch_cn); make_string_lower(arch); - name = get_coder_code_name(coder); - /* Désassemblage : déclaration */ dprintf(hfd, "/* Décode une instruction de type '%s'. */\n", coder->ins); dprintf(hfd, "GArchInstruction *"); - write_read_function_name(hfd, arch, enc_name, name); + write_read_function_name(coder, info, hfd, enc_name); dprintf(hfd, "("); dprintf(hfd, "const GArchProcessor *, GProcContext *, const GBinContent *, "); @@ -1351,7 +1419,7 @@ static bool output_coder_format(const rented_coder *coder, const output_info *in dprintf(cfd, "\n"); dprintf(cfd, "GArchInstruction *"); - write_read_function_name(cfd, arch, enc_name, name); + write_read_function_name(coder, info, cfd, enc_name); dprintf(cfd, "("); dprintf(cfd, "const GArchProcessor *proc, GProcContext *ctx, const GBinContent *content, "); @@ -1362,21 +1430,17 @@ static bool output_coder_format(const rented_coder *coder, const output_info *in dprintf(cfd, "{"); dprintf(cfd, "\n"); - make_string_upper(name); - - asprintf(&fullname, "%s_%s", info->id_prefix, name); + constant = build_coder_main_identifier(coder, info); - result = write_encoding_spec_format_disass(encoding, cfd, arch, fullname, info->fmt_prefix); + result = write_encoding_spec_format_disass(encoding, cfd, arch, constant, info->fmt_prefix); - free(fullname); + free(constant); dprintf(cfd, "}\n"); dprintf(cfd, "\n"); /* Conclusion */ - free(name); - free(arch); return result; @@ -1482,11 +1546,12 @@ bool output_coder_identifier(const rented_coder *coder, const output_info *info) bool result; /* Bilan à retourner */ bool created; /* Note une création */ int fd; /* Flux ouvert en écriture */ + char *constant; /* Définition d'une constante */ char *name; /* Désignation à manipuler */ instr_id *id; /* Gestionnaire d'identifiant */ unsigned int iid; /* Identifiant unique attribué */ - char *constant; /* Définition d'une constante */ char *comment; /* Contenu du commentaire */ + char *aligned; /* Adaptation pour l'alignement*/ result = false; @@ -1503,12 +1568,7 @@ bool output_coder_identifier(const rented_coder *coder, const output_info *info) /* Constitution de la constante */ - name = get_coder_code_name(coder); - make_string_upper(name); - - asprintf(&constant, "%s_%s,", info->id_prefix, name); - - free(name); + constant = build_coder_main_identifier(coder, info); /* Définition du commentaire */ @@ -1523,7 +1583,11 @@ bool output_coder_identifier(const rented_coder *coder, const output_info *info) /* Impression de la ligne */ - dprintf(fd, " %-40s/* %-28s*/\n", constant, comment); + asprintf(&aligned, "%s,", constant); + + dprintf(fd, " %-40s/* %-28s*/\n", aligned, comment); + + free(aligned); free(constant); free(comment); @@ -1631,8 +1695,7 @@ bool output_coder_sub_identifier(const rented_coder *coder, const output_info *i bool result; /* Bilan à retourner */ bool created; /* Note une création */ int fd; /* Flux ouvert en écriture */ - char *name; /* Désignation à manipuler */ - char *fullname; /* Désignation complète */ + char *constant; /* Définition d'une constante */ size_t i; /* Boucle de parcours */ result = false; @@ -1650,21 +1713,14 @@ bool output_coder_sub_identifier(const rented_coder *coder, const output_info *i /* Impression des sous-identifiants */ - name = get_coder_code_name(coder); - make_string_upper(name); - - asprintf(&fullname, "%s_%s", info->id_prefix, name); - - free(name); + constant = build_coder_main_identifier(coder, info); result = true; for (i = 0; i < coder->specs_count && result; i++) - result = write_encoding_spec_subid(coder->specs[i], fd, fullname); - - free(fullname); + result = write_encoding_spec_subid(coder->specs[i], fd, constant); - result = true; + free(constant); ocsi_exit: @@ -1795,9 +1851,9 @@ bool output_coder_keyword(const rented_coder *coder, const output_info *info) bool result; /* Bilan à retourner */ bool created; /* Note une création */ int fd; /* Flux ouvert en écriture */ - char *name; /* Désignation à manipuler */ - char *fullname; /* Désignation complète */ + char *constant; /* Définition d'une constante */ size_t i; /* Boucle de parcours */ + char *name; /* Désignation à manipuler */ result = false; @@ -1822,12 +1878,7 @@ bool output_coder_keyword(const rented_coder *coder, const output_info *info) /* Lancement des impressions */ - name = get_coder_code_name(coder); - make_string_upper(name); - - asprintf(&fullname, "%s_%s", info->id_prefix, name); - - free(name); + constant = build_coder_main_identifier(coder, info); result = true; @@ -1840,7 +1891,7 @@ bool output_coder_keyword(const rented_coder *coder, const output_info *info) break; case IOT_RAW: - result = write_encoding_spec_keywords(coder->specs[i], fd, fullname); + result = write_encoding_spec_keywords(coder->specs[i], fd, constant); break; case IOT_FORMAT: @@ -1848,7 +1899,7 @@ bool output_coder_keyword(const rented_coder *coder, const output_info *info) /* Impression de la colonne */ - dprintf(fd, "\t[%s] = ", fullname); + dprintf(fd, "\t[%s] = ", constant); /* Impression du mot clef */ @@ -1862,7 +1913,7 @@ bool output_coder_keyword(const rented_coder *coder, const output_info *info) } - free(fullname); + free(constant); ock_exit: @@ -1995,8 +2046,7 @@ bool output_coder_hooks(const rented_coder *coder, const output_info *info) bool result; /* Bilan à retourner */ bool created; /* Note une création */ int fd; /* Flux ouvert en écriture */ - char *name; /* Désignation à manipuler */ - char *fullname; /* Désignation complète */ + char *constant; /* Définition d'une constante */ size_t i; /* Boucle de parcours */ result = false; @@ -2022,12 +2072,7 @@ bool output_coder_hooks(const rented_coder *coder, const output_info *info) /* Lancement des impressions */ - name = get_coder_code_name(coder); - make_string_upper(name); - - asprintf(&fullname, "%s_%s", info->id_prefix, name); - - free(name); + constant = build_coder_main_identifier(coder, info); result = true; @@ -2040,17 +2085,17 @@ bool output_coder_hooks(const rented_coder *coder, const output_info *info) break; case IOT_RAW: - result = write_encoding_spec_hooks(coder->specs[i], fd, fullname, true); + result = write_encoding_spec_hooks(coder->specs[i], fd, constant, true); break; case IOT_FORMAT: assert(i == 0); - result = write_encoding_spec_hooks(coder->specs[i], fd, fullname, false); + result = write_encoding_spec_hooks(coder->specs[i], fd, constant, false); break; } - free(fullname); + free(constant); och_exit: @@ -2163,6 +2208,7 @@ bool output_coder_description(const rented_coder *coder, const output_info *info bool result; /* Bilan à retourner */ bool created; /* Note une création */ int fd; /* Flux ouvert en écriture */ + char *constant; /* Définition d'une constante */ char *name; /* Désignation à manipuler */ result = false; @@ -2188,12 +2234,11 @@ bool output_coder_description(const rented_coder *coder, const output_info *info /* Impression de la colonne */ - name = get_coder_code_name(coder); - make_string_upper(name); + constant = build_coder_main_identifier(coder, info); - dprintf(fd, "\t[%s_%s] = ", info->id_prefix, name); + dprintf(fd, "\t[%s] = ", constant); - free(name); + free(constant); /* Impression du mot clef */ diff --git a/tools/d2c/coder.h b/tools/d2c/coder.h index 218ab92..143b969 100644 --- a/tools/d2c/coder.h +++ b/tools/d2c/coder.h @@ -117,9 +117,14 @@ typedef struct _output_info const char *id_prefix; /* Préfixe pour les constantes */ int id_len; /* Largeur des identifiants */ + size_t filename_reuse; /* Taille d'une extention */ + } output_info; +/* Crée la désignation principale d'une instruction. */ +char *build_coder_main_identifier(const rented_coder *, const output_info *); + /* Génère ou complète un fichier contenant le code C principal. */ bool output_coder_body(const rented_coder *, const output_info *); diff --git a/tools/d2c/d2c.c b/tools/d2c/d2c.c index 1d9b5b6..9cb2df4 100644 --- a/tools/d2c/d2c.c +++ b/tools/d2c/d2c.c @@ -89,6 +89,14 @@ static void show_usage(const char *argv0) printf("\n"); + printf("Raw specific options:\n"); + + printf("\n"); + + printf("\t--filename-reuse \t\tSet the length of filename to include in identifiers (default = 0).\n"); + + printf("\n"); + printf("Format specific options:\n"); printf("\n"); @@ -133,21 +141,23 @@ int main(int argc, char **argv) static struct option long_options[] = { - { "help", no_argument, NULL, 'h' }, - { "exec", required_argument, NULL, 'x' }, - { "outdir", required_argument, NULL, 'o' }, - { "type", required_argument, NULL, 't' }, - { "arch", required_argument, NULL, 'a' }, - { "name", required_argument, NULL, 'n' }, - { "guard", required_argument, NULL, 'G' }, - { "encoding", required_argument, NULL, 'e' }, + { "help", no_argument, NULL, 'h' }, + { "exec", required_argument, NULL, 'x' }, + { "outdir", required_argument, NULL, 'o' }, + { "type", required_argument, NULL, 't' }, + { "arch", required_argument, NULL, 'a' }, + { "name", required_argument, NULL, 'n' }, + { "guard", required_argument, NULL, 'G' }, + { "encoding", required_argument, NULL, 'e' }, + + { "id-prefix", required_argument, NULL, 0x100 }, + { "id-expected", required_argument, NULL, 0x101 }, - { "id-prefix", required_argument, NULL, 0x100 }, - { "id-expected",required_argument, NULL, 0x101 }, + { "filename-reuse", required_argument, NULL, 0x200 }, - { "op-prefix", required_argument, NULL, 0x200 }, + { "op-prefix", required_argument, NULL, 0x300 }, - { NULL, 0, NULL, 0 } + { NULL, 0, NULL, 0 } }; @@ -163,7 +173,7 @@ int main(int argc, char **argv) while (!has_error) { - ret = getopt_long(argc, argv, "hx:o:t:a:n:e:G:", long_options, &index); + ret = getopt_long(argc, argv, "hx:o:t:a:n:G:e:", long_options, &index); if (ret == -1) break; switch (ret) @@ -244,6 +254,10 @@ int main(int argc, char **argv) break; case 0x200: + info.filename_reuse = strtoul(optarg, NULL, 10); + break; + + case 0x300: info.fmt_prefix = optarg; break; -- cgit v0.11.2-87-g4458