From 0a7b9b66bdcf386a36ec13ec480b52aa17406385 Mon Sep 17 00:00:00 2001 From: Cyrille Bagard Date: Fri, 5 Dec 2014 22:32:21 +0000 Subject: Defined a new kind of operands for memory accesses. git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@436 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a --- ChangeLog | 53 ++++- src/arch/arm/v7/helpers.h | 106 ++++++---- src/arch/arm/v7/opcodes/Makefile.am | 6 + src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h | 4 - src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h | 3 - src/arch/arm/v7/opdefs/Makefile.am | 4 + src/arch/arm/v7/opdefs/ldr_A8862.d | 137 ++++++++++++ src/arch/arm/v7/opdefs/ldr_A8864.d | 78 +++++++ src/arch/arm/v7/opdefs/mov_A88102.d | 2 +- src/arch/arm/v7/opdefs/mov_A88103.d | 90 ++++++++ src/arch/arm/v7/opdefs/str_A88203.d | 135 ++++++++++++ src/arch/arm/v7/operands/Makefile.am | 2 + src/arch/arm/v7/operands/maccess.c | 281 +++++++++++++++++++++++++ src/arch/arm/v7/operands/maccess.h | 69 ++++++ src/arch/arm/v7/operands/offset.c | 243 +++++++++++++++++++++ src/arch/arm/v7/operands/offset.h | 66 ++++++ src/arch/arm/v7/operands/shift.c | 22 +- src/arch/arm/v7/operands/shift.h | 10 +- src/arch/arm/v7/thumb_32.c | 4 +- tools/d2c/conv.c | 6 +- tools/d2c/d2c_tok.l | 12 +- 21 files changed, 1261 insertions(+), 72 deletions(-) create mode 100644 src/arch/arm/v7/opdefs/ldr_A8862.d create mode 100644 src/arch/arm/v7/opdefs/ldr_A8864.d create mode 100644 src/arch/arm/v7/opdefs/mov_A88103.d create mode 100644 src/arch/arm/v7/opdefs/str_A88203.d create mode 100644 src/arch/arm/v7/operands/maccess.c create mode 100644 src/arch/arm/v7/operands/maccess.h create mode 100644 src/arch/arm/v7/operands/offset.c create mode 100644 src/arch/arm/v7/operands/offset.h diff --git a/ChangeLog b/ChangeLog index ad98e00..fabaa54 100644 --- a/ChangeLog +++ b/ChangeLog @@ -1,3 +1,55 @@ +14-12-05 Cyrille Bagard + + * src/arch/arm/v7/helpers.h: + Remove tabulations. Add the 'MakeAccessOffset', 'MakeMemoryAccess' + and 'MakeMemoryNotIndexed' new macros. + + * src/arch/arm/v7/opcodes/Makefile.am: + Update libarcharmv7opcodes_la_SOURCES. + + * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h: + * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h: + Update missing prototypes. + + * src/arch/arm/v7/opdefs/ldr_A8862.d: + * src/arch/arm/v7/opdefs/ldr_A8864.d: + New entries: support new ARMv7 instructions. + + * src/arch/arm/v7/opdefs/Makefile.am: + Add new definitions to ARMV7_DEFS. + + * src/arch/arm/v7/opdefs/mov_A88102.d: + Fix a forgotten instruction keyword. + + * src/arch/arm/v7/opdefs/mov_A88103.d: + * src/arch/arm/v7/opdefs/str_A88203.d: + New entries: support new ARMv7 instructions. + + * src/arch/arm/v7/operands/maccess.c: + * src/arch/arm/v7/operands/maccess.h: + New entries: define a new kind of operands for memory accesses. + + * src/arch/arm/v7/operands/Makefile.am: + Add the 'maccess.[ch]' and 'offset.[ch]' new files to + libarcharmv7operands_la_SOURCES. + + * src/arch/arm/v7/operands/offset.c: + * src/arch/arm/v7/operands/offset.h: + New entries: define a new kind of operands for access offsets. + + * src/arch/arm/v7/operands/shift.c: + * src/arch/arm/v7/operands/shift.h: + Remove tabulations. Typos. + + * src/arch/arm/v7/thumb_32.c: + Fix two bugs in the disassembling process. + + * tools/d2c/conv.c: + Handle variable types other than the raw one. + + * tools/d2c/d2c_tok.l: + Support longer specification number (more than one digit). + 14-12-04 Cyrille Bagard * src/arch/arm/instruction.c: @@ -22,7 +74,6 @@ * tools/d2c/syntax.h: Allow the compiler to handle suffixes or other values for instruction names. - 14-12-04 Cyrille Bagard * src/arch/arm/v7/processor.c: diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h index 394302b..4ef7087 100644 --- a/src/arch/arm/v7/helpers.h +++ b/src/arch/arm/v7/helpers.h @@ -29,6 +29,8 @@ #include "pseudo.h" +#include "operands/maccess.h" +#include "operands/offset.h" #include "operands/shift.h" #include "../../operand.h" @@ -36,48 +38,48 @@ -#define ARMExpandImm_C(imm12, c) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ +#define ARMExpandImm_C(imm12, c) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define ARMExpandImm(imm12) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_arm_expand_imm(imm12, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ +#define ARMExpandImm(imm12) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_arm_expand_imm(imm12, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define ThumbExpandImm_C(imm12, c) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_thumb_expand_imm_c(imm12, (bool []) { c }, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ +#define ThumbExpandImm_C(imm12, c) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_thumb_expand_imm_c(imm12, (bool []) { c }, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define ThumbExpandImm(imm12) \ - ({ \ - GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_thumb_expand_imm(imm12, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ - __result; \ +#define ThumbExpandImm(imm12) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_thumb_expand_imm(imm12, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) @@ -86,8 +88,8 @@ -#define DecodeImmShift(type, imm5) \ - ({ \ +#define DecodeImmShift(type, imm5) \ + ({ \ GArchOperand *__result; \ SRType __shift_t; \ uint32_t __shift_n; \ @@ -142,6 +144,34 @@ return shift_t; + + + +/** + * Glue purement interne. + */ + + +#define MakeAccessOffset(add, off) \ + g_armv7_offset_operand_new(add, off) + + +#define MakeMemoryAccess(base, off, add, wr) \ + ({ \ + GArchOperand *__off; \ + __off = MakeAccessOffset(add, off); \ + g_armv7_maccess_operand_new(base, __off, wr); \ + }) + + +#define MakeMemoryNotIndexed(base, wr) \ + g_armv7_maccess_operand_new(base, NULL, wr) + + + + + + /* Effectue une rotation vers la droit d'une valeur. */ GArchOperand *ror_armv7_imm(uint32_t, unsigned int); diff --git a/src/arch/arm/v7/opcodes/Makefile.am b/src/arch/arm/v7/opcodes/Makefile.am index b2f5695..30d0e16 100644 --- a/src/arch/arm/v7/opcodes/Makefile.am +++ b/src/arch/arm/v7/opcodes/Makefile.am @@ -12,6 +12,7 @@ libarcharmv7opcodes_la_SOURCES = \ arm_cmn.c \ arm_cmp.c \ arm_eor.c \ + arm_ldr.c \ arm_mla.c \ arm_mls.c \ arm_mov.c \ @@ -23,6 +24,7 @@ libarcharmv7opcodes_la_SOURCES = \ arm_sbc.c \ arm_smlal.c \ arm_smull.c \ + arm_str.c \ arm_sub.c \ arm_subs.c \ arm_teq.c \ @@ -40,6 +42,7 @@ libarcharmv7opcodes_la_SOURCES = \ thumb_16_cmn.c \ thumb_16_cmp.c \ thumb_16_eor.c \ + thumb_16_ldr.c \ thumb_16_mla.c \ thumb_16_mls.c \ thumb_16_mov.c \ @@ -51,6 +54,7 @@ libarcharmv7opcodes_la_SOURCES = \ thumb_16_sbc.c \ thumb_16_smlal.c \ thumb_16_smull.c \ + thumb_16_str.c \ thumb_16_sub.c \ thumb_16_subs.c \ thumb_16_teq.c \ @@ -68,6 +72,7 @@ libarcharmv7opcodes_la_SOURCES = \ thumb_32_cmn.c \ thumb_32_cmp.c \ thumb_32_eor.c \ + thumb_32_ldr.c \ thumb_32_mla.c \ thumb_32_mls.c \ thumb_32_mov.c \ @@ -79,6 +84,7 @@ libarcharmv7opcodes_la_SOURCES = \ thumb_32_sbc.c \ thumb_32_smlal.c \ thumb_32_smull.c \ + thumb_32_str.c \ thumb_32_sub.c \ thumb_32_subs.c \ thumb_32_teq.c \ diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h index 3f7e8e5..4620f83 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h @@ -25,8 +25,6 @@ #define armv7_read_thumb_16_instr_ldrb_register(r) NULL #define armv7_read_thumb_16_instr_ldrh_immediate_thumb(r) NULL #define armv7_read_thumb_16_instr_ldrh_register(r) NULL -#define armv7_read_thumb_16_instr_ldr_immediate_thumb(r) NULL -#define armv7_read_thumb_16_instr_ldr_literal(r) NULL #define armv7_read_thumb_16_instr_ldr_register_thumb(r) NULL #define armv7_read_thumb_16_instr_ldrsb_register(r) NULL #define armv7_read_thumb_16_instr_ldrsh_register(r) NULL @@ -34,7 +32,6 @@ #define armv7_read_thumb_16_instr_lsl_register(r) NULL #define armv7_read_thumb_16_instr_lsr_immediate(r) NULL #define armv7_read_thumb_16_instr_lsr_register(r) NULL -#define armv7_read_thumb_16_instr_mov_register_thumb(r) NULL #define armv7_read_thumb_16_instr_mul(r) NULL #define armv7_read_thumb_16_instr_mvn_register(r) NULL #define armv7_read_thumb_16_instr_nop(r) NULL @@ -54,7 +51,6 @@ #define armv7_read_thumb_16_instr_strb_register(r) NULL #define armv7_read_thumb_16_instr_strh_immediate_thumb(r) NULL #define armv7_read_thumb_16_instr_strh_register(r) NULL -#define armv7_read_thumb_16_instr_str_immediate_thumb(r) NULL #define armv7_read_thumb_16_instr_str_register(r) NULL #define armv7_read_thumb_16_instr_sub_immediate_thumb(r) NULL #define armv7_read_thumb_16_instr_sub_register(r) NULL diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h index 8cd59a0..999cd0d 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -22,8 +22,6 @@ #define armv7_read_thumb_32_instr_isb(r) NULL #define armv7_read_thumb_32_instr_ldmdb_ldmea(r) NULL #define armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(r) NULL -#define armv7_read_thumb_32_instr_ldr_immediate_thumb(r) NULL -#define armv7_read_thumb_32_instr_ldr_literal(r) NULL #define armv7_read_thumb_32_instr_ldr_register_thumb(r) NULL #define armv7_read_thumb_32_instr_ldrt(r) NULL #define armv7_read_thumb_32_instr_lsl_register(r) NULL @@ -97,7 +95,6 @@ #define armv7_read_thumb_32_instr_strh_immediate_thumb(r) NULL #define armv7_read_thumb_32_instr_strh_register(r) NULL #define armv7_read_thumb_32_instr_strht(r) NULL -#define armv7_read_thumb_32_instr_str_immediate_thumb(r) NULL #define armv7_read_thumb_32_instr_str_register(r) NULL #define armv7_read_thumb_32_instr_strt(r) NULL #define armv7_read_thumb_32_instr_sub_immediate_thumb(r) NULL diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am index ff9f4a5..348cbf6 100644 --- a/src/arch/arm/v7/opdefs/Makefile.am +++ b/src/arch/arm/v7/opdefs/Makefile.am @@ -38,9 +38,12 @@ ARMV7_DEFS = \ cmp_A8838.d \ eor_A8846.d \ eor_A8847.d \ + ldr_A8862.d \ + ldr_A8864.d \ mla_A88100.d \ mls_A88101.d \ mov_A88102.d \ + mov_A88103.d \ mov_A88104.d \ mul_A88114.d \ mvn_A88115.d \ @@ -55,6 +58,7 @@ ARMV7_DEFS = \ sbc_A88162.d \ smlal_A88178.d \ smull_A88189.d \ + str_A88203.d \ sub_A88222.d \ sub_A88223.d \ teq_A88237.d \ diff --git a/src/arch/arm/v7/opdefs/ldr_A8862.d b/src/arch/arm/v7/opdefs/ldr_A8862.d new file mode 100644 index 0000000..7799fce --- /dev/null +++ b/src/arch/arm/v7/opdefs/ldr_A8862.d @@ -0,0 +1,137 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2014 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title LDR (immediate, Thumb) + +@encoding(t1) { + + @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) + + @syntax + + @conv { + + Rgt = Register(Rt) + Rgn = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 7, 32); + access = MakeMemoryAccess(Rgn, imm32, 1, 0) + + } + +} + +@encoding(t2) { + + @half 1 0 0 1 1 Rt(3) imm8(8) + + @syntax + + @conv { + + Rgt = Register(Rt) + Sp = Register(13) + imm32 = ZeroExtend(imm8:'00', 10, 32); + access = MakeMemoryAccess(Sp, imm32, 1, 0) + + } + +} + +@encoding(T3) { + + @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) + + @syntax "ldr.W" + + @conv { + + Rgt = Register(Rt) + Rgn = Register(Rn) + imm32 = ZeroExtend(imm12, 12, 32); + access = MakeMemoryAccess(Rgn, imm32, 1, 0) + + } + + @rules { + + //if Rn == '1111' then SEE LDR (literal); + //if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE; + + } + +} + +@encoding(T41) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 U(1) W(1) imm8(8) + + @syntax + + @conv { + + Rgt = Register(Rt) + Rgn = Register(Rn) + imm32 = ZeroExtend(imm8, 8, 32); + access = MakeMemoryAccess(Rgn, imm32, U, W) + + } + + @rules { + + //if Rn == '1111' then SEE LDR (literal); + //if P == '1' && U == '1' && W == '0' then SEE LDRT; + //if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP; + //if P == '0' && W == '0' then UNDEFINED; + //if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; + + } + +} + +@encoding(T42) { + + @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 0 U(1) W(1) imm8(8) + + @syntax + + @conv { + + Rgt = Register(Rt) + Rgn = Register(Rn) + imm32 = ZeroExtend(imm8, 8, 32); + base = MakeMemoryNotIndexed(Rgn, W) + offset = MakeAccessOffset(U, imm32) + + } + + @rules { + + //if Rn == '1111' then SEE LDR (literal); + //if P == '1' && U == '1' && W == '0' then SEE LDRT; + //if Rn == '1101' && P == '0' && U == '1' && W == '1' && imm8 == '00000100' then SEE POP; + //if P == '0' && W == '0' then UNDEFINED; + //if (wback && n == t) || (t == 15 && InITBlock() && !LastInITBlock()) then UNPREDICTABLE; + + } + +} diff --git a/src/arch/arm/v7/opdefs/ldr_A8864.d b/src/arch/arm/v7/opdefs/ldr_A8864.d new file mode 100644 index 0000000..acb6f94 --- /dev/null +++ b/src/arch/arm/v7/opdefs/ldr_A8864.d @@ -0,0 +1,78 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2014 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see . + */ + + +@title LDR (literal) + +@encoding(t1) { + + @half 0 1 0 0 1 Rt(3) imm8(8) + + @syntax