From 39ef3e002877a13be4274b3ef8d04aac0ae7a7f3 Mon Sep 17 00:00:00 2001
From: Cyrille Bagard <nocbos@gmail.com>
Date: Fri, 16 Jan 2015 20:21:12 +0000
Subject: Fixed mistakes between lower cases and upper cases in encodings, once
again (!).
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@457 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
---
ChangeLog | 13 +++++++++++++
src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h | 6 ------
src/arch/arm/v7/opdefs/and_A8814.d | 2 +-
src/arch/arm/v7/opdefs/cmn_A8835.d | 2 +-
src/arch/arm/v7/opdefs/mul_A88114.d | 2 +-
src/arch/arm/v7/opdefs/orr_A88123.d | 2 +-
src/arch/arm/v7/opdefs/sbc_A88162.d | 2 +-
src/arch/arm/v7/opdefs/tst_A88241.d | 2 +-
8 files changed, 19 insertions(+), 12 deletions(-)
diff --git a/ChangeLog b/ChangeLog
index 8943ab8..7e13a2f 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,5 +1,18 @@
15-01-16 Cyrille Bagard <nocbos@gmail.com>
+ * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h:
+ Update missing prototypes.
+
+ * src/arch/arm/v7/opdefs/and_A8814.d:
+ * src/arch/arm/v7/opdefs/cmn_A8835.d:
+ * src/arch/arm/v7/opdefs/mul_A88114.d:
+ * src/arch/arm/v7/opdefs/orr_A88123.d:
+ * src/arch/arm/v7/opdefs/sbc_A88162.d:
+ * src/arch/arm/v7/opdefs/tst_A88241.d:
+ Fix mistakes between lower cases and upper cases in encodings, once again (!).
+
+15-01-16 Cyrille Bagard <nocbos@gmail.com>
+
* src/arch/arm/v7/helpers.h:
Create a virtual macro helper named 'Imm16'.
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
index b30a543..8fbd93e 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
@@ -1,10 +1,8 @@
#ifndef thumb_16_def_tmp_h
#define thumb_16_def_tmp_h
-#define armv7_read_thumb_16_instr_and_register(r) NULL
#define armv7_read_thumb_16_instr_asr_immediate(r) NULL
#define armv7_read_thumb_16_instr_asr_register(r) NULL
#define armv7_read_thumb_16_instr_bkpt(r) NULL
-#define armv7_read_thumb_16_instr_cmn_register(r) NULL
#define armv7_read_thumb_16_instr_cps_thumb(r) NULL
#define armv7_read_thumb_16_instr_it(r) NULL
#define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL
@@ -16,13 +14,10 @@
#define armv7_read_thumb_16_instr_lsl_register(r) NULL
#define armv7_read_thumb_16_instr_lsr_immediate(r) NULL
#define armv7_read_thumb_16_instr_lsr_register(r) NULL
-#define armv7_read_thumb_16_instr_mul(r) NULL
-#define armv7_read_thumb_16_instr_orr_register(r) NULL
#define armv7_read_thumb_16_instr_rev(r) NULL
#define armv7_read_thumb_16_instr_rev16(r) NULL
#define armv7_read_thumb_16_instr_revsh(r) NULL
#define armv7_read_thumb_16_instr_ror_register(r) NULL
-#define armv7_read_thumb_16_instr_sbc_register(r) NULL
#define armv7_read_thumb_16_instr_setend(r) NULL
#define armv7_read_thumb_16_instr_sev(r) NULL
#define armv7_read_thumb_16_instr_stm_stmia_stmea(r) NULL
@@ -34,7 +29,6 @@
#define armv7_read_thumb_16_instr_svc_previously_swi(r) NULL
#define armv7_read_thumb_16_instr_sxtb(r) NULL
#define armv7_read_thumb_16_instr_sxth(r) NULL
-#define armv7_read_thumb_16_instr_tst_register(r) NULL
#define armv7_read_thumb_16_instr_udf(r) NULL
#define armv7_read_thumb_16_instr_uxtb(r) NULL
#define armv7_read_thumb_16_instr_uxth(r) NULL
diff --git a/src/arch/arm/v7/opdefs/and_A8814.d b/src/arch/arm/v7/opdefs/and_A8814.d
index 7991596..10593a0 100644
--- a/src/arch/arm/v7/opdefs/and_A8814.d
+++ b/src/arch/arm/v7/opdefs/and_A8814.d
@@ -23,7 +23,7 @@
@title AND (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3)
diff --git a/src/arch/arm/v7/opdefs/cmn_A8835.d b/src/arch/arm/v7/opdefs/cmn_A8835.d
index 1b94dbc..e96f17f 100644
--- a/src/arch/arm/v7/opdefs/cmn_A8835.d
+++ b/src/arch/arm/v7/opdefs/cmn_A8835.d
@@ -23,7 +23,7 @@
@title CMN (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3)
diff --git a/src/arch/arm/v7/opdefs/mul_A88114.d b/src/arch/arm/v7/opdefs/mul_A88114.d
index ca75e25..fb4fb43 100644
--- a/src/arch/arm/v7/opdefs/mul_A88114.d
+++ b/src/arch/arm/v7/opdefs/mul_A88114.d
@@ -23,7 +23,7 @@
@title MUL
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3)
diff --git a/src/arch/arm/v7/opdefs/orr_A88123.d b/src/arch/arm/v7/opdefs/orr_A88123.d
index f772c90..978a751 100644
--- a/src/arch/arm/v7/opdefs/orr_A88123.d
+++ b/src/arch/arm/v7/opdefs/orr_A88123.d
@@ -23,7 +23,7 @@
@title ORR (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3)
diff --git a/src/arch/arm/v7/opdefs/sbc_A88162.d b/src/arch/arm/v7/opdefs/sbc_A88162.d
index f2f4b72..e49f8a3 100644
--- a/src/arch/arm/v7/opdefs/sbc_A88162.d
+++ b/src/arch/arm/v7/opdefs/sbc_A88162.d
@@ -23,7 +23,7 @@
@title SBC (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3)
diff --git a/src/arch/arm/v7/opdefs/tst_A88241.d b/src/arch/arm/v7/opdefs/tst_A88241.d
index bbb4c68..070fcb3 100644
--- a/src/arch/arm/v7/opdefs/tst_A88241.d
+++ b/src/arch/arm/v7/opdefs/tst_A88241.d
@@ -23,7 +23,7 @@
@title TST (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3)
--
cgit v0.11.2-87-g4458