From 48b4166d1f2931fa7f311b6ec1c77153052e63a0 Mon Sep 17 00:00:00 2001 From: Cyrille Bagard Date: Thu, 31 May 2018 18:24:27 +0200 Subject: Handled lists of simples ARMv7 SIMD registers. --- plugins/arm/v7/helpers.h | 81 +- plugins/arm/v7/opcodes/opcodes_tmp_arm.h | 17 - plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h | 17 - plugins/arm/v7/opdefs/A88306_vcvt.d | 48 +- plugins/arm/v7/opdefs/A88320_vld1.d | 6261 +++++++++++++++++++++++++ plugins/arm/v7/opdefs/A88322_vld1.d | 1715 +++++++ plugins/arm/v7/opdefs/A88323_vld2.d | 5289 +++++++++++++++++++++ plugins/arm/v7/opdefs/A88325_vld2.d | 2085 ++++++++ plugins/arm/v7/opdefs/A88326_vld3.d | 2157 +++++++++ plugins/arm/v7/opdefs/A88328_vld3.d | 1029 ++++ plugins/arm/v7/opdefs/A88329_vld4.d | 4413 +++++++++++++++++ plugins/arm/v7/opdefs/A88331_vld4.d | 2957 ++++++++++++ plugins/arm/v7/opdefs/A88332_vldm.d | 241 + plugins/arm/v7/opdefs/A88334_vmax.d | 98 +- plugins/arm/v7/opdefs/A88335_vmax.d | 18 +- plugins/arm/v7/opdefs/A88336_vmla.d | 98 +- plugins/arm/v7/opdefs/A88337_vmla.d | 34 +- plugins/arm/v7/opdefs/A88343_vmov.d | 10 +- plugins/arm/v7/opdefs/A88344_vmov.d | 18 +- plugins/arm/v7/opdefs/A88345_vmov.d | 10 +- plugins/arm/v7/opdefs/A88346_vmovl.d | 26 +- plugins/arm/v7/opdefs/A88347_vmovn.d | 14 +- plugins/arm/v7/opdefs/A88348_vmrs.d | 6 +- plugins/arm/v7/opdefs/A88349_vmsr.d | 6 +- plugins/arm/v7/opdefs/A88350_vmul.d | 86 +- plugins/arm/v7/opdefs/A88351_vmul.d | 18 +- plugins/arm/v7/opdefs/A88353_vmvn.d | 114 +- plugins/arm/v7/opdefs/A88354_vmvn.d | 6 +- plugins/arm/v7/opdefs/A88355_vneg.d | 26 +- plugins/arm/v7/opdefs/A88356_vnm.d | 26 +- plugins/arm/v7/opdefs/A88358_vorn.d | 10 +- plugins/arm/v7/opdefs/A88359_vorr.d | 114 +- plugins/arm/v7/opdefs/A88360_vorr.d | 10 +- plugins/arm/v7/opdefs/A88361_vpadal.d | 50 +- plugins/arm/v7/opdefs/A88362_vpadd.d | 14 +- plugins/arm/v7/opdefs/A88363_vpadd.d | 6 +- plugins/arm/v7/opdefs/A88364_vpaddl.d | 50 +- plugins/arm/v7/opdefs/A88365_vpmax.d | 50 +- plugins/arm/v7/opdefs/A88366_vpmax.d | 10 +- plugins/arm/v7/opdefs/A88367_vpop.d | 113 + plugins/arm/v7/opdefs/A88368_vpush.d | 113 + plugins/arm/v7/opdefs/A88369_vqabs.d | 26 +- plugins/arm/v7/opdefs/A88370_vqadd.d | 66 +- plugins/arm/v7/opdefs/A88374_vqmov.d | 38 +- plugins/arm/v7/opdefs/A88375_vqneg.d | 26 +- plugins/arm/v7/opdefs/A88377_vqrshl.d | 66 +- plugins/arm/v7/opdefs/A88379_vqshl.d | 66 +- plugins/arm/v7/opdefs/A88382_vqsub.d | 66 +- plugins/arm/v7/opdefs/A88383_vraddhn.d | 14 +- plugins/arm/v7/opdefs/A88384_vrecpe.d | 18 +- plugins/arm/v7/opdefs/A88385_vrecps.d | 10 +- plugins/arm/v7/opdefs/A88386_vrev.d | 74 +- plugins/arm/v7/opdefs/A88387_vrhadd.d | 50 +- plugins/arm/v7/opdefs/A88388_vrshl.d | 66 +- plugins/arm/v7/opdefs/A88391_vrsqrte.d | 18 +- plugins/arm/v7/opdefs/A88392_vrsqrts.d | 10 +- plugins/arm/v7/opdefs/A88394_vrsubhn.d | 14 +- plugins/arm/v7/opdefs/A88396_vshl.d | 66 +- plugins/arm/v7/opdefs/A88401_vsqrt.d | 10 +- plugins/arm/v7/opdefs/A88404_vst1.d | 6117 ++++++++++++++++++++++++ plugins/arm/v7/opdefs/A88406_vst2.d | 5169 ++++++++++++++++++++ plugins/arm/v7/opdefs/A88408_vst3.d | 2109 +++++++++ plugins/arm/v7/opdefs/A88410_vst4.d | 4317 +++++++++++++++++ plugins/arm/v7/opdefs/A88412_vstm.d | 241 + plugins/arm/v7/opdefs/A88413_vstr.d | 10 +- plugins/arm/v7/opdefs/A88414_vsub.d | 18 +- plugins/arm/v7/opdefs/A88415_vsub.d | 18 +- plugins/arm/v7/opdefs/A88416_vsubhn.d | 14 +- plugins/arm/v7/opdefs/A88417_vsub.d | 50 +- plugins/arm/v7/opdefs/A88418_vswp.d | 10 +- plugins/arm/v7/opdefs/A88419_vtb.d | 453 ++ plugins/arm/v7/opdefs/A88420_vtrn.d | 26 +- plugins/arm/v7/opdefs/A88421_vtst.d | 26 +- plugins/arm/v7/opdefs/A88422_vuzp.d | 26 +- plugins/arm/v7/opdefs/A88423_vzip.d | 26 +- plugins/arm/v7/opdefs/A88424_wfe.d | 8 +- plugins/arm/v7/opdefs/A88425_wfi.d | 8 +- plugins/arm/v7/opdefs/A88426_yield.d | 8 +- plugins/arm/v7/opdefs/A931_enterx.d | 6 +- plugins/arm/v7/opdefs/B9310_msr.d | 6 +- plugins/arm/v7/opdefs/B9311_msr.d | 4 +- plugins/arm/v7/opdefs/B9312_msr.d | 6 +- plugins/arm/v7/opdefs/B9313_rfe.d | 14 +- plugins/arm/v7/opdefs/B9314_smc.d | 6 +- plugins/arm/v7/opdefs/B9315_srs.d | 6 +- plugins/arm/v7/opdefs/B9316_srs.d | 10 +- plugins/arm/v7/opdefs/B9317_stm.d | 10 +- plugins/arm/v7/opdefs/B9319_subs.d | 4 +- plugins/arm/v7/opdefs/B931_cps.d | 12 +- plugins/arm/v7/opdefs/B9320_subs.d | 6 +- plugins/arm/v7/opdefs/B9321_vmrs.d | 6 +- plugins/arm/v7/opdefs/B9322_vmsr.d | 6 +- plugins/arm/v7/opdefs/B932_cps.d | 8 +- plugins/arm/v7/opdefs/B933_eret.d | 6 +- plugins/arm/v7/opdefs/B934_hvc.d | 6 +- plugins/arm/v7/opdefs/B935_ldm.d | 10 +- plugins/arm/v7/opdefs/B936_ldm.d | 10 +- plugins/arm/v7/opdefs/B938_mrs.d | 6 +- plugins/arm/v7/opdefs/B939_mrs.d | 6 +- plugins/arm/v7/opdefs/Makefile.am | 17 + plugins/arm/v7/operands/maccess.c | 2 +- plugins/arm/v7/operands/register.c | 58 +- plugins/arm/v7/operands/register.h | 3 + tools/d2c/args/manager.c | 6 + tools/d2c/assert/manager.c | 123 +- tools/d2c/assert/tokens.l | 2 +- 106 files changed, 46101 insertions(+), 1086 deletions(-) create mode 100644 plugins/arm/v7/opdefs/A88320_vld1.d create mode 100644 plugins/arm/v7/opdefs/A88322_vld1.d create mode 100644 plugins/arm/v7/opdefs/A88323_vld2.d create mode 100644 plugins/arm/v7/opdefs/A88325_vld2.d create mode 100644 plugins/arm/v7/opdefs/A88326_vld3.d create mode 100644 plugins/arm/v7/opdefs/A88328_vld3.d create mode 100644 plugins/arm/v7/opdefs/A88329_vld4.d create mode 100644 plugins/arm/v7/opdefs/A88331_vld4.d create mode 100644 plugins/arm/v7/opdefs/A88332_vldm.d create mode 100644 plugins/arm/v7/opdefs/A88367_vpop.d create mode 100644 plugins/arm/v7/opdefs/A88368_vpush.d create mode 100644 plugins/arm/v7/opdefs/A88404_vst1.d create mode 100644 plugins/arm/v7/opdefs/A88406_vst2.d create mode 100644 plugins/arm/v7/opdefs/A88408_vst3.d create mode 100644 plugins/arm/v7/opdefs/A88410_vst4.d create mode 100644 plugins/arm/v7/opdefs/A88412_vstm.d create mode 100644 plugins/arm/v7/opdefs/A88419_vtb.d diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index bf4bc5a..29ba021 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -64,6 +64,20 @@ }) +#define AlignedRegister(reg, align) \ + ({ \ + GArchOperand *__result; \ + GArmV7RegisterOperand *__cast; \ + __result = reg; \ + if (__result != NULL && align != 0) \ + { \ + __cast = G_ARMV7_REGISTER_OPERAND(__result); \ + g_armv7_register_operand_define_alignement(__cast, align); \ + } \ + __result; \ + }) + + #define ARMExpandImm(imm12) \ ({ \ GArchOperand *__result; \ @@ -197,6 +211,22 @@ }) +#define DynamicVectorTable(target, count, first, inc) \ + ({ \ + GArchOperand *__result; \ + size_t __i; \ + GArchRegister *__reg; \ + __result = g_armv7_reglist_operand_new(0); \ + for (__i = 0; __i < count; __i += inc) \ + { \ + __reg = g_armv7_simd_register_new(target, first + __i); \ + g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), \ + G_ARMV7_REGISTER(__reg)); \ + } \ + __result; \ + }) + + #define Endian(big) \ ({ \ GArchOperand *__result; \ @@ -296,6 +326,22 @@ __result; \ }) + +#define NextDoubleWordVector(ref, n) \ + ({ \ + GArchOperand *__result; \ + uint8_t __idx; \ + GArchRegister *__reg; \ + __idx = g_arm_register_get_index(G_ARM_REGISTER(ref)); \ + __reg = g_armv7_simd_register_new(SRM_DOUBLE_WORD, __idx + n); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(__reg)); \ + __result; \ + }) + + #define NextRegister(idx) \ ({ \ GArchOperand *__result; \ @@ -309,7 +355,7 @@ }) -#define NexSingleWordVector(prev) \ +#define NextSingleWordVector(prev) \ ({ \ GArchOperand *__result; \ uint8_t __idx; \ @@ -591,6 +637,39 @@ }) +#define VectorTable(list, count) \ + ({ \ + GArchOperand *__result; \ + size_t __i; \ + GArchRegister *__reg; \ + __result = g_armv7_reglist_operand_new(0); \ + for (__i = 0; __i < count; __i++) \ + { \ + __reg = g_register_operand_get_register(G_REGISTER_OPERAND(list[__i])); \ + g_object_unref(G_OBJECT(list[__i])); \ + g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), \ + G_ARMV7_REGISTER(__reg)); \ + } \ + __result; \ + }) + + +#define VectorTableDim1(op1) \ + VectorTable(((GArchOperand *[]) { op1 }), 1) + + +#define VectorTableDim2(op1, op2) \ + VectorTable(((GArchOperand *[]) { op1, op2 }), 2) + + +#define VectorTableDim3(op1, op2, op3) \ + VectorTable(((GArchOperand *[]) { op1, op2, op3 }), 3) + + +#define VectorTableDim4(op1, op2, op3, op4) \ + VectorTable(((GArchOperand *[]) { op1, op2, op3, op4 }), 4) + + #define WrittenBackReg(regop, writeback) \ ({ \ GArchOperand *__result; \ diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h index 238b87a..6ad886c 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_arm.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_arm.h @@ -3,19 +3,10 @@ #define armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(r) NULL #define armv7_read_arm_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(r) NULL #define armv7_read_arm_instr_a8_vdup_scalar(r) NULL -#define armv7_read_arm_instr_a8_vld1_multiple_single_elements(r) NULL -#define armv7_read_arm_instr_a8_vld1_single_element_to_all_lanes(r) NULL #define armv7_read_arm_instr_a8_vld1_single_element_to_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vld2_multiple_2_element_structures(r) NULL -#define armv7_read_arm_instr_a8_vld2_single_2_element_structure_to_all_lanes(r) NULL #define armv7_read_arm_instr_a8_vld2_single_2_element_structure_to_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vld3_multiple_3_element_structures(r) NULL -#define armv7_read_arm_instr_a8_vld3_single_3_element_structure_to_all_lanes(r) NULL #define armv7_read_arm_instr_a8_vld3_single_3_element_structure_to_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vld4_multiple_4_element_structures(r) NULL -#define armv7_read_arm_instr_a8_vld4_single_4_element_structure_to_all_lanes(r) NULL #define armv7_read_arm_instr_a8_vld4_single_4_element_structure_to_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vldm(r) NULL #define armv7_read_arm_instr_a8_vldr(r) NULL #define armv7_read_arm_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(r) NULL #define armv7_read_arm_instr_a8_vmov_arm_core_register_to_scalar(r) NULL @@ -23,8 +14,6 @@ #define armv7_read_arm_instr_a8_vmov_register(r) NULL #define armv7_read_arm_instr_a8_vmov_scalar_to_arm_core_register(r) NULL #define armv7_read_arm_instr_a8_vmul_vmull_by_scalar(r) NULL -#define armv7_read_arm_instr_a8_vpop(r) NULL -#define armv7_read_arm_instr_a8_vpush(r) NULL #define armv7_read_arm_instr_a8_vqdmlal_vqdmlsl(r) NULL #define armv7_read_arm_instr_a8_vqdmulh(r) NULL #define armv7_read_arm_instr_a8_vqdmull(r) NULL @@ -42,14 +31,8 @@ #define armv7_read_arm_instr_a8_vsli(r) NULL #define armv7_read_arm_instr_a8_vsra(r) NULL #define armv7_read_arm_instr_a8_vsri(r) NULL -#define armv7_read_arm_instr_a8_vst1_multiple_single_elements(r) NULL #define armv7_read_arm_instr_a8_vst1_single_element_from_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vst2_multiple_2_element_structures(r) NULL #define armv7_read_arm_instr_a8_vst2_single_2_element_structure_from_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vst3_multiple_3_element_structures(r) NULL #define armv7_read_arm_instr_a8_vst3_single_3_element_structure_from_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vst4_multiple_4_element_structures(r) NULL #define armv7_read_arm_instr_a8_vst4_single_4_element_structure_from_one_lane(r) NULL -#define armv7_read_arm_instr_a8_vstm(r) NULL -#define armv7_read_arm_instr_a8_vtbl_vtbx(r) NULL #endif diff --git a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h index c0ec1f8..87792bf 100644 --- a/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/plugins/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -3,19 +3,10 @@ #define armv7_read_thumb_32_instr_a8_vcvt_between_floating_point_and_fixed_point_advanced_simd(r) NULL #define armv7_read_thumb_32_instr_a8_vcvt_between_floating_point_and_fixed_point_floating_point(r) NULL #define armv7_read_thumb_32_instr_a8_vdup_scalar(r) NULL -#define armv7_read_thumb_32_instr_a8_vld1_multiple_single_elements(r) NULL -#define armv7_read_thumb_32_instr_a8_vld1_single_element_to_all_lanes(r) NULL #define armv7_read_thumb_32_instr_a8_vld1_single_element_to_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vld2_multiple_2_element_structures(r) NULL -#define armv7_read_thumb_32_instr_a8_vld2_single_2_element_structure_to_all_lanes(r) NULL #define armv7_read_thumb_32_instr_a8_vld2_single_2_element_structure_to_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vld3_multiple_3_element_structures(r) NULL -#define armv7_read_thumb_32_instr_a8_vld3_single_3_element_structure_to_all_lanes(r) NULL #define armv7_read_thumb_32_instr_a8_vld3_single_3_element_structure_to_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vld4_multiple_4_element_structures(r) NULL -#define armv7_read_thumb_32_instr_a8_vld4_single_4_element_structure_to_all_lanes(r) NULL #define armv7_read_thumb_32_instr_a8_vld4_single_4_element_structure_to_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vldm(r) NULL #define armv7_read_thumb_32_instr_a8_vldr(r) NULL #define armv7_read_thumb_32_instr_a8_vmla_vmlal_vmls_vmlsl_by_scalar(r) NULL #define armv7_read_thumb_32_instr_a8_vmov_arm_core_register_to_scalar(r) NULL @@ -23,8 +14,6 @@ #define armv7_read_thumb_32_instr_a8_vmov_register(r) NULL #define armv7_read_thumb_32_instr_a8_vmov_scalar_to_arm_core_register(r) NULL #define armv7_read_thumb_32_instr_a8_vmul_vmull_by_scalar(r) NULL -#define armv7_read_thumb_32_instr_a8_vpop(r) NULL -#define armv7_read_thumb_32_instr_a8_vpush(r) NULL #define armv7_read_thumb_32_instr_a8_vqdmlal_vqdmlsl(r) NULL #define armv7_read_thumb_32_instr_a8_vqdmulh(r) NULL #define armv7_read_thumb_32_instr_a8_vqdmull(r) NULL @@ -42,14 +31,8 @@ #define armv7_read_thumb_32_instr_a8_vsli(r) NULL #define armv7_read_thumb_32_instr_a8_vsra(r) NULL #define armv7_read_thumb_32_instr_a8_vsri(r) NULL -#define armv7_read_thumb_32_instr_a8_vst1_multiple_single_elements(r) NULL #define armv7_read_thumb_32_instr_a8_vst1_single_element_from_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vst2_multiple_2_element_structures(r) NULL #define armv7_read_thumb_32_instr_a8_vst2_single_2_element_structure_from_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vst3_multiple_3_element_structures(r) NULL #define armv7_read_thumb_32_instr_a8_vst3_single_3_element_structure_from_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vst4_multiple_4_element_structures(r) NULL #define armv7_read_thumb_32_instr_a8_vst4_single_4_element_structure_from_one_lane(r) NULL -#define armv7_read_thumb_32_instr_a8_vstm(r) NULL -#define armv7_read_thumb_32_instr_a8_vtbl_vtbx(r) NULL #endif diff --git a/plugins/arm/v7/opdefs/A88306_vcvt.d b/plugins/arm/v7/opdefs/A88306_vcvt.d index 173232b..8cbc3ce 100644 --- a/plugins/arm/v7/opdefs/A88306_vcvt.d +++ b/plugins/arm/v7/opdefs/A88306_vcvt.d @@ -41,7 +41,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 1 op == 0 @@ -64,7 +64,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 1 op == 1 @@ -87,7 +87,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 0 op == 0 @@ -110,7 +110,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 0 op == 1 @@ -133,7 +133,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 1 op == 0 @@ -156,7 +156,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 1 op == 1 @@ -179,7 +179,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 0 op == 0 @@ -202,7 +202,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 0 op == 1 @@ -225,7 +225,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 1 op == 1 @@ -248,7 +248,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 1 op == 0 @@ -271,7 +271,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 0 op == 1 @@ -294,7 +294,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 0 op == 0 @@ -323,7 +323,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 1 op == 0 @@ -346,7 +346,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 1 op == 1 @@ -369,7 +369,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 0 op == 0 @@ -392,7 +392,7 @@ @assert { - opc2 == 0 + opc2 == 101 sz == 0 op == 1 @@ -415,7 +415,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 1 op == 0 @@ -438,7 +438,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 1 op == 1 @@ -461,7 +461,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 0 op == 0 @@ -484,7 +484,7 @@ @assert { - opc2 == 0 + opc2 == 100 sz == 0 op == 1 @@ -507,7 +507,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 1 op == 1 @@ -530,7 +530,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 1 op == 0 @@ -553,7 +553,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 0 op == 1 @@ -576,7 +576,7 @@ @assert { - opc2 == 0 + opc2 == 000 sz == 0 op == 0 diff --git a/plugins/arm/v7/opdefs/A88320_vld1.d b/plugins/arm/v7/opdefs/A88320_vld1.d new file mode 100644 index 0000000..cd8b715 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88320_vld1.d @@ -0,0 +1,6261 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD1 (multiple single elements) + +@id 312 + +@desc { + + This instruction loads elements from memory into one, two, three, or four registers, without de-interleaving. Every element of each register is loaded. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 1373 + + @assert { + + Rm == 1111 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1374 + + @assert { + + Rm == 1111 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1375 + + @assert { + + Rm == 1111 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1376 + + @assert { + + Rm == 1111 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1377 + + @assert { + + Rm == 1111 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1378 + + @assert { + + Rm == 1111 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1379 + + @assert { + + Rm == 1111 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1380 + + @assert { + + Rm == 1111 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1381 + + @assert { + + Rm == 1111 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1382 + + @assert { + + Rm == 1111 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1383 + + @assert { + + Rm == 1111 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1384 + + @assert { + + Rm == 1111 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1385 + + @assert { + + Rm == 1111 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1386 + + @assert { + + Rm == 1111 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1387 + + @assert { + + Rm == 1111 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1388 + + @assert { + + Rm == 1111 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1389 + + @assert { + + Rm == 1111 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1390 + + @assert { + + Rm == 1111 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1391 + + @assert { + + Rm == 1111 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1392 + + @assert { + + Rm == 1111 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1393 + + @assert { + + Rm == 1111 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1394 + + @assert { + + Rm == 1111 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1395 + + @assert { + + Rm == 1111 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1396 + + @assert { + + Rm == 1111 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1397 + + @assert { + + Rm == 1111 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1398 + + @assert { + + Rm == 1111 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1399 + + @assert { + + Rm == 1111 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1400 + + @assert { + + Rm == 1111 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1401 + + @assert { + + Rm == 1111 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1402 + + @assert { + + Rm == 1111 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1403 + + @assert { + + Rm == 1111 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1404 + + @assert { + + Rm == 1111 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1405 + + @assert { + + Rm == 1111 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1406 + + @assert { + + Rm == 1111 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1407 + + @assert { + + Rm == 1111 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1408 + + @assert { + + Rm == 1111 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1409 + + @assert { + + Rm == 1101 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1410 + + @assert { + + Rm == 1101 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1411 + + @assert { + + Rm == 1101 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1412 + + @assert { + + Rm == 1101 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1413 + + @assert { + + Rm == 1101 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1414 + + @assert { + + Rm == 1101 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1415 + + @assert { + + Rm == 1101 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1416 + + @assert { + + Rm == 1101 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1417 + + @assert { + + Rm == 1101 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1418 + + @assert { + + Rm == 1101 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1419 + + @assert { + + Rm == 1101 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1420 + + @assert { + + Rm == 1101 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1421 + + @assert { + + Rm == 1101 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1422 + + @assert { + + Rm == 1101 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1423 + + @assert { + + Rm == 1101 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1424 + + @assert { + + Rm == 1101 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1425 + + @assert { + + Rm == 1101 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1426 + + @assert { + + Rm == 1101 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1427 + + @assert { + + Rm == 1101 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1428 + + @assert { + + Rm == 1101 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1429 + + @assert { + + Rm == 1101 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1430 + + @assert { + + Rm == 1101 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1431 + + @assert { + + Rm == 1101 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1432 + + @assert { + + Rm == 1101 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1433 + + @assert { + + Rm == 1101 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1434 + + @assert { + + Rm == 1101 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1435 + + @assert { + + Rm == 1101 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1436 + + @assert { + + Rm == 1101 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1437 + + @assert { + + Rm == 1101 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1438 + + @assert { + + Rm == 1101 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1439 + + @assert { + + Rm == 1101 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1440 + + @assert { + + Rm == 1101 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1441 + + @assert { + + Rm == 1101 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1442 + + @assert { + + Rm == 1101 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1443 + + @assert { + + Rm == 1101 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1444 + + @assert { + + Rm == 1101 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1445 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1446 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1447 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1448 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1449 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1450 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1451 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1452 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1453 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1454 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1455 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1456 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1457 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1458 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1459 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1460 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1461 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1462 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1463 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1464 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1465 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1466 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1467 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1468 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1469 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1470 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1471 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1472 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1473 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1474 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1475 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1476 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1477 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1478 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1479 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1480 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 1481 + + @assert { + + Rm == 1111 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1482 + + @assert { + + Rm == 1111 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1483 + + @assert { + + Rm == 1111 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1484 + + @assert { + + Rm == 1111 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1485 + + @assert { + + Rm == 1111 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1486 + + @assert { + + Rm == 1111 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1487 + + @assert { + + Rm == 1111 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1488 + + @assert { + + Rm == 1111 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1489 + + @assert { + + Rm == 1111 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1490 + + @assert { + + Rm == 1111 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1491 + + @assert { + + Rm == 1111 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1492 + + @assert { + + Rm == 1111 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1493 + + @assert { + + Rm == 1111 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1494 + + @assert { + + Rm == 1111 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1495 + + @assert { + + Rm == 1111 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1496 + + @assert { + + Rm == 1111 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1497 + + @assert { + + Rm == 1111 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1498 + + @assert { + + Rm == 1111 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1499 + + @assert { + + Rm == 1111 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1500 + + @assert { + + Rm == 1111 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1501 + + @assert { + + Rm == 1111 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1502 + + @assert { + + Rm == 1111 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1503 + + @assert { + + Rm == 1111 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1504 + + @assert { + + Rm == 1111 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1505 + + @assert { + + Rm == 1111 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1506 + + @assert { + + Rm == 1111 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1507 + + @assert { + + Rm == 1111 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1508 + + @assert { + + Rm == 1111 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1509 + + @assert { + + Rm == 1111 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1510 + + @assert { + + Rm == 1111 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1511 + + @assert { + + Rm == 1111 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1512 + + @assert { + + Rm == 1111 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1513 + + @assert { + + Rm == 1111 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1514 + + @assert { + + Rm == 1111 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1515 + + @assert { + + Rm == 1111 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1516 + + @assert { + + Rm == 1111 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1517 + + @assert { + + Rm == 1101 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1518 + + @assert { + + Rm == 1101 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1519 + + @assert { + + Rm == 1101 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1520 + + @assert { + + Rm == 1101 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1521 + + @assert { + + Rm == 1101 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1522 + + @assert { + + Rm == 1101 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1523 + + @assert { + + Rm == 1101 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1524 + + @assert { + + Rm == 1101 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1525 + + @assert { + + Rm == 1101 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1526 + + @assert { + + Rm == 1101 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1527 + + @assert { + + Rm == 1101 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1528 + + @assert { + + Rm == 1101 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1529 + + @assert { + + Rm == 1101 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1530 + + @assert { + + Rm == 1101 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1531 + + @assert { + + Rm == 1101 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1532 + + @assert { + + Rm == 1101 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1533 + + @assert { + + Rm == 1101 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1534 + + @assert { + + Rm == 1101 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1535 + + @assert { + + Rm == 1101 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1536 + + @assert { + + Rm == 1101 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1537 + + @assert { + + Rm == 1101 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1538 + + @assert { + + Rm == 1101 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1539 + + @assert { + + Rm == 1101 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1540 + + @assert { + + Rm == 1101 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1541 + + @assert { + + Rm == 1101 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1542 + + @assert { + + Rm == 1101 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1543 + + @assert { + + Rm == 1101 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1544 + + @assert { + + Rm == 1101 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1545 + + @assert { + + Rm == 1101 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1546 + + @assert { + + Rm == 1101 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1547 + + @assert { + + Rm == 1101 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1548 + + @assert { + + Rm == 1101 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1549 + + @assert { + + Rm == 1101 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1550 + + @assert { + + Rm == 1101 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1551 + + @assert { + + Rm == 1101 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1552 + + @assert { + + Rm == 1101 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1553 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1554 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1555 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1556 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1557 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1558 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1559 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1560 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1561 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1562 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1563 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1564 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1565 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1566 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1567 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1568 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1569 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1570 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1571 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1572 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1573 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1574 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1575 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1576 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1577 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1578 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1579 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1580 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1581 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1582 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1583 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1584 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1585 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1586 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1587 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + + @syntax { + + @subid 1588 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.64 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88322_vld1.d b/plugins/arm/v7/opdefs/A88322_vld1.d new file mode 100644 index 0000000..7adc007 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88322_vld1.d @@ -0,0 +1,1715 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD1 (single element to all lanes) + +@id 313 + +@desc { + + This instruction loads one element from memory into every element of one or two vectors. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 0 0 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 1589 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1590 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1591 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1592 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1593 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1594 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1595 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1596 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1597 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1598 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1599 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1600 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1601 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1602 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1603 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1604 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1605 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1606 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1607 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1608 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1609 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1610 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1611 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1612 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1613 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1614 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1615 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1616 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1617 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1618 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 0 0 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 1619 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1620 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1621 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1622 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1623 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1624 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1625 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1626 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1627 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1628 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1629 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1630 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1631 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1632 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1633 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1634 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1635 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1636 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1637 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1638 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1639 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1640 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.8 list maccess + + } + + @syntax { + + @subid 1641 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1642 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1643 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1644 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.16 list maccess + + } + + @syntax { + + @subid 1645 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1646 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1647 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + + @syntax { + + @subid 1648 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld1.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88323_vld2.d b/plugins/arm/v7/opdefs/A88323_vld2.d new file mode 100644 index 0000000..515b540 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88323_vld2.d @@ -0,0 +1,5289 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD2 (multiple 2-element structures) + +@id 314 + +@desc { + + This instruction loads multiple 2-element structures from memory into two or four registers, with de-interleaving. For more information, see Element and structure load/store instructions on page A4-181. Every element of each register is loaded. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 1649 + + @assert { + + Rm == 1111 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1650 + + @assert { + + Rm == 1111 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1651 + + @assert { + + Rm == 1111 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1652 + + @assert { + + Rm == 1111 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1653 + + @assert { + + Rm == 1111 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1654 + + @assert { + + Rm == 1111 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1655 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1656 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1657 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1658 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1659 + + @assert { + + Rm == 1111 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1660 + + @assert { + + Rm == 1111 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1661 + + @assert { + + Rm == 1111 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1662 + + @assert { + + Rm == 1111 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1663 + + @assert { + + Rm == 1111 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1664 + + @assert { + + Rm == 1111 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1665 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1666 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1667 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1668 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1669 + + @assert { + + Rm == 1111 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1670 + + @assert { + + Rm == 1111 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1671 + + @assert { + + Rm == 1111 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1672 + + @assert { + + Rm == 1111 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1673 + + @assert { + + Rm == 1111 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1674 + + @assert { + + Rm == 1111 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1675 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1676 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1677 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1678 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1679 + + @assert { + + Rm == 1101 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1680 + + @assert { + + Rm == 1101 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1681 + + @assert { + + Rm == 1101 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1682 + + @assert { + + Rm == 1101 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1683 + + @assert { + + Rm == 1101 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1684 + + @assert { + + Rm == 1101 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1685 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1686 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1687 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1688 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1689 + + @assert { + + Rm == 1101 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1690 + + @assert { + + Rm == 1101 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1691 + + @assert { + + Rm == 1101 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1692 + + @assert { + + Rm == 1101 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1693 + + @assert { + + Rm == 1101 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1694 + + @assert { + + Rm == 1101 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1695 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1696 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1697 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1698 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1699 + + @assert { + + Rm == 1101 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1700 + + @assert { + + Rm == 1101 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1701 + + @assert { + + Rm == 1101 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1702 + + @assert { + + Rm == 1101 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1703 + + @assert { + + Rm == 1101 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1704 + + @assert { + + Rm == 1101 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1705 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1706 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1707 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1708 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1709 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1710 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1711 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1712 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1713 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1714 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1715 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1716 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1717 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1718 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1719 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1720 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1721 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1722 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1723 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1724 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1725 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1726 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1727 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1728 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1729 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1730 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1731 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1732 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1733 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1734 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1735 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1736 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1737 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1738 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 1739 + + @assert { + + Rm == 1111 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1740 + + @assert { + + Rm == 1111 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1741 + + @assert { + + Rm == 1111 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1742 + + @assert { + + Rm == 1111 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1743 + + @assert { + + Rm == 1111 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1744 + + @assert { + + Rm == 1111 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1745 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1746 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1747 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1748 + + @assert { + + Rm == 1111 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1749 + + @assert { + + Rm == 1111 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1750 + + @assert { + + Rm == 1111 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1751 + + @assert { + + Rm == 1111 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1752 + + @assert { + + Rm == 1111 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1753 + + @assert { + + Rm == 1111 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1754 + + @assert { + + Rm == 1111 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1755 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1756 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1757 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1758 + + @assert { + + Rm == 1111 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1759 + + @assert { + + Rm == 1111 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1760 + + @assert { + + Rm == 1111 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1761 + + @assert { + + Rm == 1111 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1762 + + @assert { + + Rm == 1111 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1763 + + @assert { + + Rm == 1111 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1764 + + @assert { + + Rm == 1111 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1765 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1766 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1767 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1768 + + @assert { + + Rm == 1111 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1769 + + @assert { + + Rm == 1101 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1770 + + @assert { + + Rm == 1101 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1771 + + @assert { + + Rm == 1101 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1772 + + @assert { + + Rm == 1101 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1773 + + @assert { + + Rm == 1101 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1774 + + @assert { + + Rm == 1101 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1775 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1776 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1777 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1778 + + @assert { + + Rm == 1101 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1779 + + @assert { + + Rm == 1101 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1780 + + @assert { + + Rm == 1101 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1781 + + @assert { + + Rm == 1101 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1782 + + @assert { + + Rm == 1101 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1783 + + @assert { + + Rm == 1101 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1784 + + @assert { + + Rm == 1101 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1785 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1786 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1787 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1788 + + @assert { + + Rm == 1101 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1789 + + @assert { + + Rm == 1101 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1790 + + @assert { + + Rm == 1101 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1791 + + @assert { + + Rm == 1101 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1792 + + @assert { + + Rm == 1101 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1793 + + @assert { + + Rm == 1101 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1794 + + @assert { + + Rm == 1101 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1795 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1796 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1797 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1798 + + @assert { + + Rm == 1101 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1799 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1800 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1801 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1802 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1803 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1804 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1805 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1806 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1807 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1808 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1809 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1810 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1811 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1812 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1813 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1814 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1815 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1816 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1817 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1818 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1819 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1820 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1821 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1822 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1823 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1824 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1825 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1826 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1827 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1828 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88325_vld2.d b/plugins/arm/v7/opdefs/A88325_vld2.d new file mode 100644 index 0000000..096da34 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88325_vld2.d @@ -0,0 +1,2085 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD2 (single 2-element structure to all lanes) + +@id 315 + +@desc { + + This instruction loads one 2-element structure from memory into all lanes of two registers. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 0 1 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 1829 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1830 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1831 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1832 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1833 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1834 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1835 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1836 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1837 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1838 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1839 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1840 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1841 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1842 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1843 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1844 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1845 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1846 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1847 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1848 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1849 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1850 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1851 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1852 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1853 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1854 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1855 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1856 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1857 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1858 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1859 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1860 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1861 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1862 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1863 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1864 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 0 1 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 1865 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1866 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1867 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1868 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1869 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1870 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1871 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1872 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1873 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1874 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1875 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1876 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1877 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1878 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1879 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1880 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1881 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1882 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1883 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1884 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1885 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1886 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1887 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1888 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1889 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1890 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1891 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 16) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1892 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.8 list maccess + + } + + @syntax { + + @subid 1893 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1894 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1895 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1896 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.16 list maccess + + } + + @syntax { + + @subid 1897 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1898 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1899 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + + @syntax { + + @subid 1900 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld2.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88326_vld3.d b/plugins/arm/v7/opdefs/A88326_vld3.d new file mode 100644 index 0000000..b60efc8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88326_vld3.d @@ -0,0 +1,2157 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD3 (multiple 3-element structures) + +@id 316 + +@desc { + + This instruction loads multiple 3-element structures from memory into three registers, with de-interleaving. For more information, see Element and structure load/store instructions on page A4-181. Every element of each register is loaded. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 1901 + + @assert { + + Rm == 1111 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1902 + + @assert { + + Rm == 1111 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1903 + + @assert { + + Rm == 1111 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1904 + + @assert { + + Rm == 1111 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1905 + + @assert { + + Rm == 1111 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1906 + + @assert { + + Rm == 1111 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1907 + + @assert { + + Rm == 1111 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1908 + + @assert { + + Rm == 1111 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1909 + + @assert { + + Rm == 1111 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1910 + + @assert { + + Rm == 1111 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1911 + + @assert { + + Rm == 1111 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1912 + + @assert { + + Rm == 1111 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1913 + + @assert { + + Rm == 1101 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1914 + + @assert { + + Rm == 1101 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1915 + + @assert { + + Rm == 1101 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1916 + + @assert { + + Rm == 1101 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1917 + + @assert { + + Rm == 1101 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1918 + + @assert { + + Rm == 1101 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1919 + + @assert { + + Rm == 1101 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1920 + + @assert { + + Rm == 1101 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1921 + + @assert { + + Rm == 1101 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1922 + + @assert { + + Rm == 1101 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1923 + + @assert { + + Rm == 1101 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1924 + + @assert { + + Rm == 1101 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1925 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1926 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1927 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1928 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1929 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1930 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1931 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1932 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1933 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1934 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1935 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1936 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 1937 + + @assert { + + Rm == 1111 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1938 + + @assert { + + Rm == 1111 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1939 + + @assert { + + Rm == 1111 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1940 + + @assert { + + Rm == 1111 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1941 + + @assert { + + Rm == 1111 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1942 + + @assert { + + Rm == 1111 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1943 + + @assert { + + Rm == 1111 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1944 + + @assert { + + Rm == 1111 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1945 + + @assert { + + Rm == 1111 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1946 + + @assert { + + Rm == 1111 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1947 + + @assert { + + Rm == 1111 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1948 + + @assert { + + Rm == 1111 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1949 + + @assert { + + Rm == 1101 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1950 + + @assert { + + Rm == 1101 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1951 + + @assert { + + Rm == 1101 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1952 + + @assert { + + Rm == 1101 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1953 + + @assert { + + Rm == 1101 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1954 + + @assert { + + Rm == 1101 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1955 + + @assert { + + Rm == 1101 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1956 + + @assert { + + Rm == 1101 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1957 + + @assert { + + Rm == 1101 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1958 + + @assert { + + Rm == 1101 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1959 + + @assert { + + Rm == 1101 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1960 + + @assert { + + Rm == 1101 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1961 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1962 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1963 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1964 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1965 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1966 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1967 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1968 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1969 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1970 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1971 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1972 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld3.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88328_vld3.d b/plugins/arm/v7/opdefs/A88328_vld3.d new file mode 100644 index 0000000..2c854ef --- /dev/null +++ b/plugins/arm/v7/opdefs/A88328_vld3.d @@ -0,0 +1,1029 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD3 (single 3-element structure to all lanes) + +@id 317 + +@desc { + + This instruction loads one 3-element structure from memory into all lanes of three registers. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 1 0 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 1973 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1974 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1975 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1976 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1977 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1978 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1979 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1980 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1981 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1982 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1983 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1984 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1985 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1986 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1987 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1988 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1989 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1990 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 1 0 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 1991 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1992 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1993 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1994 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 1995 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1996 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 1997 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1998 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 1999 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 2000 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 2001 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 2002 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + maccess = MemAccessPreIndexed(reg_N, NULL) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 2003 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 2004 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.8 list maccess + + } + + @syntax { + + @subid 2005 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 2006 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.16 list maccess + + } + + @syntax { + + @subid 2007 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.32 list maccess + + } + + @syntax { + + @subid 2008 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm vld3.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88329_vld4.d b/plugins/arm/v7/opdefs/A88329_vld4.d new file mode 100644 index 0000000..5d6e272 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88329_vld4.d @@ -0,0 +1,4413 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD4 (multiple 4-element structures) + +@id 318 + +@desc { + + This instruction loads multiple 4-element structures from memory into four registers, with de-interleaving. For more information, see Element and structure load/store instructions on page A4-181. Every element of each register is loaded. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 2009 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2010 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2011 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2012 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2013 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2014 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2015 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2016 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2017 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2018 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2019 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2020 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2021 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2022 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2023 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2024 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2025 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2026 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2027 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2028 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2029 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2030 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2031 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2032 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2033 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2034 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2035 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2036 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2037 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2038 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2039 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2040 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2041 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2042 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2043 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2044 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2045 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2046 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2047 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2048 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2049 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2050 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2051 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2052 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2053 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2054 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2055 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2056 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2057 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2058 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2059 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2060 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2061 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2062 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2063 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2064 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2065 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2066 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2067 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2068 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2069 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2070 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2071 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2072 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2073 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2074 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2075 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2076 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2077 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2078 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2079 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2080 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 1 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 2081 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2082 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2083 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2084 + + @assert { + + Rm == 1111 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2085 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2086 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2087 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2088 + + @assert { + + Rm == 1111 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2089 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2090 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2091 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2092 + + @assert { + + Rm == 1111 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2093 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2094 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2095 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2096 + + @assert { + + Rm == 1111 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2097 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2098 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2099 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2100 + + @assert { + + Rm == 1111 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2101 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2102 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2103 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2104 + + @assert { + + Rm == 1111 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2105 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2106 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2107 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2108 + + @assert { + + Rm == 1101 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2109 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2110 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2111 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2112 + + @assert { + + Rm == 1101 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2113 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2114 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2115 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2116 + + @assert { + + Rm == 1101 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2117 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2118 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2119 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2120 + + @assert { + + Rm == 1101 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2121 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2122 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2123 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2124 + + @assert { + + Rm == 1101 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2125 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2126 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2127 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2128 + + @assert { + + Rm == 1101 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2129 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2130 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2131 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2132 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2133 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2134 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2135 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2136 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2137 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2138 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2139 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2140 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2141 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2142 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2143 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2144 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2145 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2146 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2147 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2148 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2149 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2150 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2151 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2152 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88331_vld4.d b/plugins/arm/v7/opdefs/A88331_vld4.d new file mode 100644 index 0000000..148d319 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88331_vld4.d @@ -0,0 +1,2957 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLD4 (single 4-element structure to all lanes) + +@id 319 + +@desc { + + This instruction loads one 4-element structure from memory into all lanes of four registers. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 1 1 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 2153 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2154 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2155 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2156 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2157 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2158 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2159 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2160 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2161 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2162 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2163 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2164 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2165 + + @assert { + + Rm == 1111 + size == 11 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2166 + + @assert { + + Rm == 1111 + size == 11 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2167 + + @assert { + + Rm == 1111 + size == 11 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2168 + + @assert { + + Rm == 1111 + size == 11 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2169 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2170 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2171 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2172 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2173 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2174 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2175 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2176 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2177 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2178 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2179 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2180 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2181 + + @assert { + + Rm == 1101 + size == 11 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2182 + + @assert { + + Rm == 1101 + size == 11 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2183 + + @assert { + + Rm == 1101 + size == 11 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2184 + + @assert { + + Rm == 1101 + size == 11 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2185 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2186 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2187 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2188 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2189 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2190 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2191 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2192 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2193 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2194 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2195 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2196 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2197 + + @assert { + + Rm != 11x1 + size == 11 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2198 + + @assert { + + Rm != 11x1 + size == 11 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2199 + + @assert { + + Rm != 11x1 + size == 11 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2200 + + @assert { + + Rm != 11x1 + size == 11 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 1 D(1) 1 0 Rn(4) Vd(4) 1 1 1 1 size(2) T(1) a(1) Rm(4) + + @syntax { + + @subid 2201 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2202 + + @assert { + + Rm == 1111 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2203 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2204 + + @assert { + + Rm == 1111 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2205 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2206 + + @assert { + + Rm == 1111 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2207 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2208 + + @assert { + + Rm == 1111 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2209 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2210 + + @assert { + + Rm == 1111 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2211 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2212 + + @assert { + + Rm == 1111 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2213 + + @assert { + + Rm == 1111 + size == 11 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2214 + + @assert { + + Rm == 1111 + size == 11 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2215 + + @assert { + + Rm == 1111 + size == 11 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2216 + + @assert { + + Rm == 1111 + size == 11 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2217 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2218 + + @assert { + + Rm == 1101 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2219 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2220 + + @assert { + + Rm == 1101 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2221 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2222 + + @assert { + + Rm == 1101 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2223 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2224 + + @assert { + + Rm == 1101 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2225 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2226 + + @assert { + + Rm == 1101 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2227 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2228 + + @assert { + + Rm == 1101 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2229 + + @assert { + + Rm == 1101 + size == 11 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2230 + + @assert { + + Rm == 1101 + size == 11 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2231 + + @assert { + + Rm == 1101 + size == 11 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2232 + + @assert { + + Rm == 1101 + size == 11 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2233 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2234 + + @assert { + + Rm != 11x1 + size == 0 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2235 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 32) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2236 + + @assert { + + Rm != 11x1 + size == 0 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.8 list maccess + + } + + @syntax { + + @subid 2237 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2238 + + @assert { + + Rm != 11x1 + size == 1 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2239 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2240 + + @assert { + + Rm != 11x1 + size == 1 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.16 list maccess + + } + + @syntax { + + @subid 2241 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2242 + + @assert { + + Rm != 11x1 + size == 10 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2243 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2244 + + @assert { + + Rm != 11x1 + size == 10 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2245 + + @assert { + + Rm != 11x1 + size == 11 + T == 0 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2246 + + @assert { + + Rm != 11x1 + size == 11 + T == 0 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2247 + + @assert { + + Rm != 11x1 + size == 11 + T == 1 + a == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + + @syntax { + + @subid 2248 + + @assert { + + Rm != 11x1 + size == 11 + T == 1 + a == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vld4.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88332_vldm.d b/plugins/arm/v7/opdefs/A88332_vldm.d new file mode 100644 index 0000000..41f33a9 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88332_vldm.d @@ -0,0 +1,241 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VLDM + +@id 320 + +@desc { + + Vector Load Multiple loads multiple extension registers from consecutive memory locations using an address from an ARM core register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 summarizes these controls. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 2249 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vldmia wb_reg list + + } + + @syntax { + + @subid 2250 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vldmdb wb_reg list + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 2251 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vldmia wb_reg list + + } + + @syntax { + + @subid 2252 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vldmdb wb_reg list + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 2253 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vldmia wb_reg list + + } + + @syntax { + + @subid 2254 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vldmdb wb_reg list + + } + +} + +@encoding (A2) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 1 Rn(4) Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 2255 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vldmia wb_reg list + + } + + @syntax { + + @subid 2256 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vldmdb wb_reg list + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88334_vmax.d b/plugins/arm/v7/opdefs/A88334_vmax.d index b695d70..7ec4d4e 100644 --- a/plugins/arm/v7/opdefs/A88334_vmax.d +++ b/plugins/arm/v7/opdefs/A88334_vmax.d @@ -23,7 +23,7 @@ @title VMAX, VMIN (integer) -@id 312 +@id 321 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1373 + @subid 2257 @assert { @@ -62,7 +62,7 @@ @syntax { - @subid 1374 + @subid 2258 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 1375 + @subid 2259 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 1376 + @subid 2260 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 1377 + @subid 2261 @assert { @@ -162,7 +162,7 @@ @syntax { - @subid 1378 + @subid 2262 @assert { @@ -187,7 +187,7 @@ @syntax { - @subid 1379 + @subid 2263 @assert { @@ -212,7 +212,7 @@ @syntax { - @subid 1380 + @subid 2264 @assert { @@ -237,7 +237,7 @@ @syntax { - @subid 1381 + @subid 2265 @assert { @@ -262,7 +262,7 @@ @syntax { - @subid 1382 + @subid 2266 @assert { @@ -287,7 +287,7 @@ @syntax { - @subid 1383 + @subid 2267 @assert { @@ -312,7 +312,7 @@ @syntax { - @subid 1384 + @subid 2268 @assert { @@ -337,7 +337,7 @@ @syntax { - @subid 1385 + @subid 2269 @assert { @@ -362,7 +362,7 @@ @syntax { - @subid 1386 + @subid 2270 @assert { @@ -387,7 +387,7 @@ @syntax { - @subid 1387 + @subid 2271 @assert { @@ -412,7 +412,7 @@ @syntax { - @subid 1388 + @subid 2272 @assert { @@ -437,7 +437,7 @@ @syntax { - @subid 1389 + @subid 2273 @assert { @@ -462,7 +462,7 @@ @syntax { - @subid 1390 + @subid 2274 @assert { @@ -487,7 +487,7 @@ @syntax { - @subid 1391 + @subid 2275 @assert { @@ -512,7 +512,7 @@ @syntax { - @subid 1392 + @subid 2276 @assert { @@ -537,7 +537,7 @@ @syntax { - @subid 1393 + @subid 2277 @assert { @@ -562,7 +562,7 @@ @syntax { - @subid 1394 + @subid 2278 @assert { @@ -587,7 +587,7 @@ @syntax { - @subid 1395 + @subid 2279 @assert { @@ -612,7 +612,7 @@ @syntax { - @subid 1396 + @subid 2280 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 1397 + @subid 2281 @assert { @@ -668,7 +668,7 @@ @syntax { - @subid 1398 + @subid 2282 @assert { @@ -693,7 +693,7 @@ @syntax { - @subid 1399 + @subid 2283 @assert { @@ -718,7 +718,7 @@ @syntax { - @subid 1400 + @subid 2284 @assert { @@ -743,7 +743,7 @@ @syntax { - @subid 1401 + @subid 2285 @assert { @@ -768,7 +768,7 @@ @syntax { - @subid 1402 + @subid 2286 @assert { @@ -793,7 +793,7 @@ @syntax { - @subid 1403 + @subid 2287 @assert { @@ -818,7 +818,7 @@ @syntax { - @subid 1404 + @subid 2288 @assert { @@ -843,7 +843,7 @@ @syntax { - @subid 1405 + @subid 2289 @assert { @@ -868,7 +868,7 @@ @syntax { - @subid 1406 + @subid 2290 @assert { @@ -893,7 +893,7 @@ @syntax { - @subid 1407 + @subid 2291 @assert { @@ -918,7 +918,7 @@ @syntax { - @subid 1408 + @subid 2292 @assert { @@ -943,7 +943,7 @@ @syntax { - @subid 1409 + @subid 2293 @assert { @@ -968,7 +968,7 @@ @syntax { - @subid 1410 + @subid 2294 @assert { @@ -993,7 +993,7 @@ @syntax { - @subid 1411 + @subid 2295 @assert { @@ -1018,7 +1018,7 @@ @syntax { - @subid 1412 + @subid 2296 @assert { @@ -1043,7 +1043,7 @@ @syntax { - @subid 1413 + @subid 2297 @assert { @@ -1068,7 +1068,7 @@ @syntax { - @subid 1414 + @subid 2298 @assert { @@ -1093,7 +1093,7 @@ @syntax { - @subid 1415 + @subid 2299 @assert { @@ -1118,7 +1118,7 @@ @syntax { - @subid 1416 + @subid 2300 @assert { @@ -1143,7 +1143,7 @@ @syntax { - @subid 1417 + @subid 2301 @assert { @@ -1168,7 +1168,7 @@ @syntax { - @subid 1418 + @subid 2302 @assert { @@ -1193,7 +1193,7 @@ @syntax { - @subid 1419 + @subid 2303 @assert { @@ -1218,7 +1218,7 @@ @syntax { - @subid 1420 + @subid 2304 @assert { diff --git a/plugins/arm/v7/opdefs/A88335_vmax.d b/plugins/arm/v7/opdefs/A88335_vmax.d index d14313e..d2daea5 100644 --- a/plugins/arm/v7/opdefs/A88335_vmax.d +++ b/plugins/arm/v7/opdefs/A88335_vmax.d @@ -23,7 +23,7 @@ @title VMAX, VMIN (floating-point) -@id 313 +@id 322 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1421 + @subid 2305 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1422 + @subid 2306 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1423 + @subid 2307 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1424 + @subid 2308 @assert { @@ -135,7 +135,7 @@ @syntax { - @subid 1425 + @subid 2309 @assert { @@ -158,7 +158,7 @@ @syntax { - @subid 1426 + @subid 2310 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1427 + @subid 2311 @assert { @@ -204,7 +204,7 @@ @syntax { - @subid 1428 + @subid 2312 @assert { diff --git a/plugins/arm/v7/opdefs/A88336_vmla.d b/plugins/arm/v7/opdefs/A88336_vmla.d index 93f0161..b7f6a0d 100644 --- a/plugins/arm/v7/opdefs/A88336_vmla.d +++ b/plugins/arm/v7/opdefs/A88336_vmla.d @@ -23,7 +23,7 @@ @title VMLA, VMLAL, VMLS, VMLSL (integer) -@id 314 +@id 323 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1429 + @subid 2313 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1430 + @subid 2314 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1431 + @subid 2315 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1432 + @subid 2316 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 1433 + @subid 2317 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1434 + @subid 2318 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1435 + @subid 2319 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 1436 + @subid 2320 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 1437 + @subid 2321 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 1438 + @subid 2322 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 1439 + @subid 2323 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1440 + @subid 2324 @assert { @@ -331,7 +331,7 @@ @syntax { - @subid 1441 + @subid 2325 @assert { @@ -355,7 +355,7 @@ @syntax { - @subid 1442 + @subid 2326 @assert { @@ -379,7 +379,7 @@ @syntax { - @subid 1443 + @subid 2327 @assert { @@ -403,7 +403,7 @@ @syntax { - @subid 1444 + @subid 2328 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 1445 + @subid 2329 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 1446 + @subid 2330 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 1447 + @subid 2331 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1448 + @subid 2332 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 1449 + @subid 2333 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 1450 + @subid 2334 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 1451 + @subid 2335 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 1452 + @subid 2336 @assert { @@ -625,7 +625,7 @@ @syntax { - @subid 1453 + @subid 2337 @assert { @@ -649,7 +649,7 @@ @syntax { - @subid 1454 + @subid 2338 @assert { @@ -673,7 +673,7 @@ @syntax { - @subid 1455 + @subid 2339 @assert { @@ -697,7 +697,7 @@ @syntax { - @subid 1456 + @subid 2340 @assert { @@ -721,7 +721,7 @@ @syntax { - @subid 1457 + @subid 2341 @assert { @@ -745,7 +745,7 @@ @syntax { - @subid 1458 + @subid 2342 @assert { @@ -769,7 +769,7 @@ @syntax { - @subid 1459 + @subid 2343 @assert { @@ -793,7 +793,7 @@ @syntax { - @subid 1460 + @subid 2344 @assert { @@ -817,7 +817,7 @@ @syntax { - @subid 1461 + @subid 2345 @assert { @@ -841,7 +841,7 @@ @syntax { - @subid 1462 + @subid 2346 @assert { @@ -865,7 +865,7 @@ @syntax { - @subid 1463 + @subid 2347 @assert { @@ -889,7 +889,7 @@ @syntax { - @subid 1464 + @subid 2348 @assert { @@ -919,7 +919,7 @@ @syntax { - @subid 1465 + @subid 2349 @assert { @@ -943,7 +943,7 @@ @syntax { - @subid 1466 + @subid 2350 @assert { @@ -967,7 +967,7 @@ @syntax { - @subid 1467 + @subid 2351 @assert { @@ -991,7 +991,7 @@ @syntax { - @subid 1468 + @subid 2352 @assert { @@ -1015,7 +1015,7 @@ @syntax { - @subid 1469 + @subid 2353 @assert { @@ -1039,7 +1039,7 @@ @syntax { - @subid 1470 + @subid 2354 @assert { @@ -1063,7 +1063,7 @@ @syntax { - @subid 1471 + @subid 2355 @assert { @@ -1087,7 +1087,7 @@ @syntax { - @subid 1472 + @subid 2356 @assert { @@ -1111,7 +1111,7 @@ @syntax { - @subid 1473 + @subid 2357 @assert { @@ -1135,7 +1135,7 @@ @syntax { - @subid 1474 + @subid 2358 @assert { @@ -1159,7 +1159,7 @@ @syntax { - @subid 1475 + @subid 2359 @assert { @@ -1183,7 +1183,7 @@ @syntax { - @subid 1476 + @subid 2360 @assert { diff --git a/plugins/arm/v7/opdefs/A88337_vmla.d b/plugins/arm/v7/opdefs/A88337_vmla.d index 94d2817..f67b0e1 100644 --- a/plugins/arm/v7/opdefs/A88337_vmla.d +++ b/plugins/arm/v7/opdefs/A88337_vmla.d @@ -23,7 +23,7 @@ @title VMLA, VMLS (floating-point) -@id 315 +@id 324 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1477 + @subid 2361 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1478 + @subid 2362 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1479 + @subid 2363 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1480 + @subid 2364 @assert { @@ -139,7 +139,7 @@ @syntax { - @subid 1481 + @subid 2365 @assert { @@ -162,7 +162,7 @@ @syntax { - @subid 1482 + @subid 2366 @assert { @@ -185,7 +185,7 @@ @syntax { - @subid 1483 + @subid 2367 @assert { @@ -208,7 +208,7 @@ @syntax { - @subid 1484 + @subid 2368 @assert { @@ -237,7 +237,7 @@ @syntax { - @subid 1485 + @subid 2369 @assert { @@ -261,7 +261,7 @@ @syntax { - @subid 1486 + @subid 2370 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 1487 + @subid 2371 @assert { @@ -309,7 +309,7 @@ @syntax { - @subid 1488 + @subid 2372 @assert { @@ -339,7 +339,7 @@ @syntax { - @subid 1489 + @subid 2373 @assert { @@ -362,7 +362,7 @@ @syntax { - @subid 1490 + @subid 2374 @assert { @@ -385,7 +385,7 @@ @syntax { - @subid 1491 + @subid 2375 @assert { @@ -408,7 +408,7 @@ @syntax { - @subid 1492 + @subid 2376 @assert { diff --git a/plugins/arm/v7/opdefs/A88343_vmov.d b/plugins/arm/v7/opdefs/A88343_vmov.d index 1607415..c662ebc 100644 --- a/plugins/arm/v7/opdefs/A88343_vmov.d +++ b/plugins/arm/v7/opdefs/A88343_vmov.d @@ -23,7 +23,7 @@ @title VMOV (between ARM core register and single-precision register) -@id 316 +@id 325 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1493 + @subid 2377 @assert { @@ -58,7 +58,7 @@ @syntax { - @subid 1494 + @subid 2378 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1495 + @subid 2379 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1496 + @subid 2380 @assert { diff --git a/plugins/arm/v7/opdefs/A88344_vmov.d b/plugins/arm/v7/opdefs/A88344_vmov.d index a3de0b8..e653720 100644 --- a/plugins/arm/v7/opdefs/A88344_vmov.d +++ b/plugins/arm/v7/opdefs/A88344_vmov.d @@ -23,7 +23,7 @@ @title VMOV (between two ARM core registers and two single-precision registers) -@id 317 +@id 326 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1497 + @subid 2381 @assert { @@ -48,7 +48,7 @@ @conv { swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) reg_T = Register(Rt) reg_T2 = Register(Rt2) @@ -60,7 +60,7 @@ @syntax { - @subid 1498 + @subid 2382 @assert { @@ -73,7 +73,7 @@ reg_T = Register(Rt) reg_T2 = Register(Rt2) swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) } @@ -89,7 +89,7 @@ @syntax { - @subid 1499 + @subid 2383 @assert { @@ -100,7 +100,7 @@ @conv { swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) reg_T = Register(Rt) reg_T2 = Register(Rt2) @@ -112,7 +112,7 @@ @syntax { - @subid 1500 + @subid 2384 @assert { @@ -125,7 +125,7 @@ reg_T = Register(Rt) reg_T2 = Register(Rt2) swvec_M = SingleWordVector(Vm:M) - reg_Sm1 = NexSingleWordVector(swvec_M) + reg_Sm1 = NextSingleWordVector(swvec_M) } diff --git a/plugins/arm/v7/opdefs/A88345_vmov.d b/plugins/arm/v7/opdefs/A88345_vmov.d index 18c6dfa..b95ac75 100644 --- a/plugins/arm/v7/opdefs/A88345_vmov.d +++ b/plugins/arm/v7/opdefs/A88345_vmov.d @@ -23,7 +23,7 @@ @title VMOV (between two ARM core registers and a doubleword extension register) -@id 318 +@id 327 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1501 + @subid 2385 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1502 + @subid 2386 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 1503 + @subid 2387 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1504 + @subid 2388 @assert { diff --git a/plugins/arm/v7/opdefs/A88346_vmovl.d b/plugins/arm/v7/opdefs/A88346_vmovl.d index 4c73e88..31f9b26 100644 --- a/plugins/arm/v7/opdefs/A88346_vmovl.d +++ b/plugins/arm/v7/opdefs/A88346_vmovl.d @@ -23,7 +23,7 @@ @title VMOVL -@id 319 +@id 328 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1505 + @subid 2389 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1506 + @subid 2390 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1507 + @subid 2391 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1508 + @subid 2392 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 1509 + @subid 2393 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 1510 + @subid 2394 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 1511 + @subid 2395 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 1512 + @subid 2396 @assert { @@ -219,7 +219,7 @@ @syntax { - @subid 1513 + @subid 2397 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 1514 + @subid 2398 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 1515 + @subid 2399 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 1516 + @subid 2400 @assert { diff --git a/plugins/arm/v7/opdefs/A88347_vmovn.d b/plugins/arm/v7/opdefs/A88347_vmovn.d index 1f9f1a1..d4952b4 100644 --- a/plugins/arm/v7/opdefs/A88347_vmovn.d +++ b/plugins/arm/v7/opdefs/A88347_vmovn.d @@ -23,7 +23,7 @@ @title VMOVN -@id 320 +@id 329 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1517 + @subid 2401 @assert { @@ -58,7 +58,7 @@ @syntax { - @subid 1518 + @subid 2402 @assert { @@ -79,7 +79,7 @@ @syntax { - @subid 1519 + @subid 2403 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1520 + @subid 2404 @assert { @@ -127,7 +127,7 @@ @syntax { - @subid 1521 + @subid 2405 @assert { @@ -148,7 +148,7 @@ @syntax { - @subid 1522 + @subid 2406 @assert { diff --git a/plugins/arm/v7/opdefs/A88348_vmrs.d b/plugins/arm/v7/opdefs/A88348_vmrs.d index 182b77f..a17511a 100644 --- a/plugins/arm/v7/opdefs/A88348_vmrs.d +++ b/plugins/arm/v7/opdefs/A88348_vmrs.d @@ -23,7 +23,7 @@ @title VMRS -@id 321 +@id 330 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1523 + @subid 2407 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 1524 + @subid 2408 @conv { diff --git a/plugins/arm/v7/opdefs/A88349_vmsr.d b/plugins/arm/v7/opdefs/A88349_vmsr.d index cda0610..718f3f8 100644 --- a/plugins/arm/v7/opdefs/A88349_vmsr.d +++ b/plugins/arm/v7/opdefs/A88349_vmsr.d @@ -23,7 +23,7 @@ @title VMSR -@id 322 +@id 331 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1525 + @subid 2409 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 1526 + @subid 2410 @conv { diff --git a/plugins/arm/v7/opdefs/A88350_vmul.d b/plugins/arm/v7/opdefs/A88350_vmul.d index 4b1271a..c935978 100644 --- a/plugins/arm/v7/opdefs/A88350_vmul.d +++ b/plugins/arm/v7/opdefs/A88350_vmul.d @@ -23,7 +23,7 @@ @title VMUL, VMULL (integer and polynomial) -@id 323 +@id 332 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1527 + @subid 2411 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1528 + @subid 2412 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1529 + @subid 2413 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1530 + @subid 2414 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 1531 + @subid 2415 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1532 + @subid 2416 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1533 + @subid 2417 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 1534 + @subid 2418 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 1535 + @subid 2419 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 1536 + @subid 2420 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 1537 + @subid 2421 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1538 + @subid 2422 @assert { @@ -331,7 +331,7 @@ @syntax { - @subid 1539 + @subid 2423 @assert { @@ -355,7 +355,7 @@ @syntax { - @subid 1540 + @subid 2424 @assert { @@ -379,7 +379,7 @@ @syntax { - @subid 1541 + @subid 2425 @assert { @@ -403,7 +403,7 @@ @syntax { - @subid 1542 + @subid 2426 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 1543 + @subid 2427 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 1544 + @subid 2428 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 1545 + @subid 2429 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1546 + @subid 2430 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 1547 + @subid 2431 @assert { @@ -553,7 +553,7 @@ @syntax { - @subid 1548 + @subid 2432 @assert { @@ -577,7 +577,7 @@ @syntax { - @subid 1549 + @subid 2433 @assert { @@ -601,7 +601,7 @@ @syntax { - @subid 1550 + @subid 2434 @assert { @@ -625,7 +625,7 @@ @syntax { - @subid 1551 + @subid 2435 @assert { @@ -649,7 +649,7 @@ @syntax { - @subid 1552 + @subid 2436 @assert { @@ -673,7 +673,7 @@ @syntax { - @subid 1553 + @subid 2437 @assert { @@ -697,7 +697,7 @@ @syntax { - @subid 1554 + @subid 2438 @assert { @@ -721,7 +721,7 @@ @syntax { - @subid 1555 + @subid 2439 @assert { @@ -745,7 +745,7 @@ @syntax { - @subid 1556 + @subid 2440 @assert { @@ -769,7 +769,7 @@ @syntax { - @subid 1557 + @subid 2441 @assert { @@ -793,7 +793,7 @@ @syntax { - @subid 1558 + @subid 2442 @assert { @@ -817,7 +817,7 @@ @syntax { - @subid 1559 + @subid 2443 @assert { @@ -847,7 +847,7 @@ @syntax { - @subid 1560 + @subid 2444 @assert { @@ -871,7 +871,7 @@ @syntax { - @subid 1561 + @subid 2445 @assert { @@ -895,7 +895,7 @@ @syntax { - @subid 1562 + @subid 2446 @assert { @@ -919,7 +919,7 @@ @syntax { - @subid 1563 + @subid 2447 @assert { @@ -943,7 +943,7 @@ @syntax { - @subid 1564 + @subid 2448 @assert { @@ -967,7 +967,7 @@ @syntax { - @subid 1565 + @subid 2449 @assert { @@ -991,7 +991,7 @@ @syntax { - @subid 1566 + @subid 2450 @assert { @@ -1015,7 +1015,7 @@ @syntax { - @subid 1567 + @subid 2451 @assert { @@ -1039,7 +1039,7 @@ @syntax { - @subid 1568 + @subid 2452 @assert { diff --git a/plugins/arm/v7/opdefs/A88351_vmul.d b/plugins/arm/v7/opdefs/A88351_vmul.d index 4112d08..f5ad41e 100644 --- a/plugins/arm/v7/opdefs/A88351_vmul.d +++ b/plugins/arm/v7/opdefs/A88351_vmul.d @@ -23,7 +23,7 @@ @title VMUL (floating-point) -@id 324 +@id 333 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1569 + @subid 2453 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1570 + @subid 2454 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 1571 + @subid 2455 @assert { @@ -111,7 +111,7 @@ @syntax { - @subid 1572 + @subid 2456 @assert { @@ -139,7 +139,7 @@ @syntax { - @subid 1573 + @subid 2457 @assert { @@ -162,7 +162,7 @@ @syntax { - @subid 1574 + @subid 2458 @assert { @@ -191,7 +191,7 @@ @syntax { - @subid 1575 + @subid 2459 @assert { @@ -213,7 +213,7 @@ @syntax { - @subid 1576 + @subid 2460 @assert { diff --git a/plugins/arm/v7/opdefs/A88353_vmvn.d b/plugins/arm/v7/opdefs/A88353_vmvn.d index 2801289..1f4c40c 100644 --- a/plugins/arm/v7/opdefs/A88353_vmvn.d +++ b/plugins/arm/v7/opdefs/A88353_vmvn.d @@ -23,7 +23,7 @@ @title VMVN (immediate) -@id 325 +@id 334 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1577 + @subid 2461 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1578 + @subid 2462 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1579 + @subid 2463 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1580 + @subid 2464 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 1581 + @subid 2465 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 1582 + @subid 2466 @assert { @@ -169,7 +169,7 @@ @syntax { - @subid 1583 + @subid 2467 @assert { @@ -191,7 +191,7 @@ @syntax { - @subid 1584 + @subid 2468 @assert { @@ -213,7 +213,7 @@ @syntax { - @subid 1585 + @subid 2469 @assert { @@ -235,7 +235,7 @@ @syntax { - @subid 1586 + @subid 2470 @assert { @@ -257,7 +257,7 @@ @syntax { - @subid 1587 + @subid 2471 @assert { @@ -279,7 +279,7 @@ @syntax { - @subid 1588 + @subid 2472 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1589 + @subid 2473 @assert { @@ -323,7 +323,7 @@ @syntax { - @subid 1590 + @subid 2474 @assert { @@ -345,7 +345,7 @@ @syntax { - @subid 1591 + @subid 2475 @assert { @@ -367,7 +367,7 @@ @syntax { - @subid 1592 + @subid 2476 @assert { @@ -389,7 +389,7 @@ @syntax { - @subid 1593 + @subid 2477 @assert { @@ -411,7 +411,7 @@ @syntax { - @subid 1594 + @subid 2478 @assert { @@ -433,7 +433,7 @@ @syntax { - @subid 1595 + @subid 2479 @assert { @@ -455,7 +455,7 @@ @syntax { - @subid 1596 + @subid 2480 @assert { @@ -477,7 +477,7 @@ @syntax { - @subid 1597 + @subid 2481 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1598 + @subid 2482 @assert { @@ -521,7 +521,7 @@ @syntax { - @subid 1599 + @subid 2483 @assert { @@ -543,7 +543,7 @@ @syntax { - @subid 1600 + @subid 2484 @assert { @@ -565,7 +565,7 @@ @syntax { - @subid 1601 + @subid 2485 @assert { @@ -587,7 +587,7 @@ @syntax { - @subid 1602 + @subid 2486 @assert { @@ -609,7 +609,7 @@ @syntax { - @subid 1603 + @subid 2487 @assert { @@ -631,7 +631,7 @@ @syntax { - @subid 1604 + @subid 2488 @assert { @@ -659,7 +659,7 @@ @syntax { - @subid 1605 + @subid 2489 @assert { @@ -681,7 +681,7 @@ @syntax { - @subid 1606 + @subid 2490 @assert { @@ -703,7 +703,7 @@ @syntax { - @subid 1607 + @subid 2491 @assert { @@ -725,7 +725,7 @@ @syntax { - @subid 1608 + @subid 2492 @assert { @@ -747,7 +747,7 @@ @syntax { - @subid 1609 + @subid 2493 @assert { @@ -769,7 +769,7 @@ @syntax { - @subid 1610 + @subid 2494 @assert { @@ -791,7 +791,7 @@ @syntax { - @subid 1611 + @subid 2495 @assert { @@ -813,7 +813,7 @@ @syntax { - @subid 1612 + @subid 2496 @assert { @@ -835,7 +835,7 @@ @syntax { - @subid 1613 + @subid 2497 @assert { @@ -857,7 +857,7 @@ @syntax { - @subid 1614 + @subid 2498 @assert { @@ -879,7 +879,7 @@ @syntax { - @subid 1615 + @subid 2499 @assert { @@ -901,7 +901,7 @@ @syntax { - @subid 1616 + @subid 2500 @assert { @@ -923,7 +923,7 @@ @syntax { - @subid 1617 + @subid 2501 @assert { @@ -945,7 +945,7 @@ @syntax { - @subid 1618 + @subid 2502 @assert { @@ -967,7 +967,7 @@ @syntax { - @subid 1619 + @subid 2503 @assert { @@ -989,7 +989,7 @@ @syntax { - @subid 1620 + @subid 2504 @assert { @@ -1011,7 +1011,7 @@ @syntax { - @subid 1621 + @subid 2505 @assert { @@ -1033,7 +1033,7 @@ @syntax { - @subid 1622 + @subid 2506 @assert { @@ -1055,7 +1055,7 @@ @syntax { - @subid 1623 + @subid 2507 @assert { @@ -1077,7 +1077,7 @@ @syntax { - @subid 1624 + @subid 2508 @assert { @@ -1099,7 +1099,7 @@ @syntax { - @subid 1625 + @subid 2509 @assert { @@ -1121,7 +1121,7 @@ @syntax { - @subid 1626 + @subid 2510 @assert { @@ -1143,7 +1143,7 @@ @syntax { - @subid 1627 + @subid 2511 @assert { @@ -1165,7 +1165,7 @@ @syntax { - @subid 1628 + @subid 2512 @assert { @@ -1187,7 +1187,7 @@ @syntax { - @subid 1629 + @subid 2513 @assert { @@ -1209,7 +1209,7 @@ @syntax { - @subid 1630 + @subid 2514 @assert { @@ -1231,7 +1231,7 @@ @syntax { - @subid 1631 + @subid 2515 @assert { @@ -1253,7 +1253,7 @@ @syntax { - @subid 1632 + @subid 2516 @assert { diff --git a/plugins/arm/v7/opdefs/A88354_vmvn.d b/plugins/arm/v7/opdefs/A88354_vmvn.d index 30c4391..905661c 100644 --- a/plugins/arm/v7/opdefs/A88354_vmvn.d +++ b/plugins/arm/v7/opdefs/A88354_vmvn.d @@ -23,7 +23,7 @@ @title VMVN (register) -@id 326 +@id 335 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1633 + @subid 2517 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 1634 + @subid 2518 @conv { diff --git a/plugins/arm/v7/opdefs/A88355_vneg.d b/plugins/arm/v7/opdefs/A88355_vneg.d index fca1b13..25204f1 100644 --- a/plugins/arm/v7/opdefs/A88355_vneg.d +++ b/plugins/arm/v7/opdefs/A88355_vneg.d @@ -23,7 +23,7 @@ @title VNEG -@id 327 +@id 336 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1635 + @subid 2519 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1636 + @subid 2520 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1637 + @subid 2521 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1638 + @subid 2522 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 1639 + @subid 2523 @assert { @@ -152,7 +152,7 @@ @syntax { - @subid 1640 + @subid 2524 @assert { @@ -179,7 +179,7 @@ @syntax { - @subid 1641 + @subid 2525 @assert { @@ -201,7 +201,7 @@ @syntax { - @subid 1642 + @subid 2526 @assert { @@ -223,7 +223,7 @@ @syntax { - @subid 1643 + @subid 2527 @assert { @@ -245,7 +245,7 @@ @syntax { - @subid 1644 + @subid 2528 @assert { @@ -273,7 +273,7 @@ @syntax { - @subid 1645 + @subid 2529 @assert { @@ -294,7 +294,7 @@ @syntax { - @subid 1646 + @subid 2530 @assert { diff --git a/plugins/arm/v7/opdefs/A88356_vnm.d b/plugins/arm/v7/opdefs/A88356_vnm.d index 5538125..ca22377 100644 --- a/plugins/arm/v7/opdefs/A88356_vnm.d +++ b/plugins/arm/v7/opdefs/A88356_vnm.d @@ -23,7 +23,7 @@ @title VNMLA, VNMLS, VNMUL -@id 328 +@id 337 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1647 + @subid 2531 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1648 + @subid 2532 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1649 + @subid 2533 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1650 + @subid 2534 @assert { @@ -135,7 +135,7 @@ @syntax { - @subid 1651 + @subid 2535 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1652 + @subid 2536 @assert { @@ -185,7 +185,7 @@ @syntax { - @subid 1653 + @subid 2537 @assert { @@ -208,7 +208,7 @@ @syntax { - @subid 1654 + @subid 2538 @assert { @@ -231,7 +231,7 @@ @syntax { - @subid 1655 + @subid 2539 @assert { @@ -254,7 +254,7 @@ @syntax { - @subid 1656 + @subid 2540 @assert { @@ -283,7 +283,7 @@ @syntax { - @subid 1657 + @subid 2541 @assert { @@ -305,7 +305,7 @@ @syntax { - @subid 1658 + @subid 2542 @assert { diff --git a/plugins/arm/v7/opdefs/A88358_vorn.d b/plugins/arm/v7/opdefs/A88358_vorn.d index 66f68d4..f7684d0 100644 --- a/plugins/arm/v7/opdefs/A88358_vorn.d +++ b/plugins/arm/v7/opdefs/A88358_vorn.d @@ -23,7 +23,7 @@ @title VORN (register) -@id 330 +@id 339 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1659 + @subid 2543 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1660 + @subid 2544 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 1661 + @subid 2545 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1662 + @subid 2546 @assert { diff --git a/plugins/arm/v7/opdefs/A88359_vorr.d b/plugins/arm/v7/opdefs/A88359_vorr.d index 989e4e4..a0a5dc1 100644 --- a/plugins/arm/v7/opdefs/A88359_vorr.d +++ b/plugins/arm/v7/opdefs/A88359_vorr.d @@ -23,7 +23,7 @@ @title VORR (immediate) -@id 331 +@id 340 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1663 + @subid 2547 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1664 + @subid 2548 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1665 + @subid 2549 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1666 + @subid 2550 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 1667 + @subid 2551 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 1668 + @subid 2552 @assert { @@ -169,7 +169,7 @@ @syntax { - @subid 1669 + @subid 2553 @assert { @@ -191,7 +191,7 @@ @syntax { - @subid 1670 + @subid 2554 @assert { @@ -213,7 +213,7 @@ @syntax { - @subid 1671 + @subid 2555 @assert { @@ -235,7 +235,7 @@ @syntax { - @subid 1672 + @subid 2556 @assert { @@ -257,7 +257,7 @@ @syntax { - @subid 1673 + @subid 2557 @assert { @@ -279,7 +279,7 @@ @syntax { - @subid 1674 + @subid 2558 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1675 + @subid 2559 @assert { @@ -323,7 +323,7 @@ @syntax { - @subid 1676 + @subid 2560 @assert { @@ -345,7 +345,7 @@ @syntax { - @subid 1677 + @subid 2561 @assert { @@ -367,7 +367,7 @@ @syntax { - @subid 1678 + @subid 2562 @assert { @@ -389,7 +389,7 @@ @syntax { - @subid 1679 + @subid 2563 @assert { @@ -411,7 +411,7 @@ @syntax { - @subid 1680 + @subid 2564 @assert { @@ -433,7 +433,7 @@ @syntax { - @subid 1681 + @subid 2565 @assert { @@ -455,7 +455,7 @@ @syntax { - @subid 1682 + @subid 2566 @assert { @@ -477,7 +477,7 @@ @syntax { - @subid 1683 + @subid 2567 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1684 + @subid 2568 @assert { @@ -521,7 +521,7 @@ @syntax { - @subid 1685 + @subid 2569 @assert { @@ -543,7 +543,7 @@ @syntax { - @subid 1686 + @subid 2570 @assert { @@ -565,7 +565,7 @@ @syntax { - @subid 1687 + @subid 2571 @assert { @@ -587,7 +587,7 @@ @syntax { - @subid 1688 + @subid 2572 @assert { @@ -609,7 +609,7 @@ @syntax { - @subid 1689 + @subid 2573 @assert { @@ -631,7 +631,7 @@ @syntax { - @subid 1690 + @subid 2574 @assert { @@ -659,7 +659,7 @@ @syntax { - @subid 1691 + @subid 2575 @assert { @@ -681,7 +681,7 @@ @syntax { - @subid 1692 + @subid 2576 @assert { @@ -703,7 +703,7 @@ @syntax { - @subid 1693 + @subid 2577 @assert { @@ -725,7 +725,7 @@ @syntax { - @subid 1694 + @subid 2578 @assert { @@ -747,7 +747,7 @@ @syntax { - @subid 1695 + @subid 2579 @assert { @@ -769,7 +769,7 @@ @syntax { - @subid 1696 + @subid 2580 @assert { @@ -791,7 +791,7 @@ @syntax { - @subid 1697 + @subid 2581 @assert { @@ -813,7 +813,7 @@ @syntax { - @subid 1698 + @subid 2582 @assert { @@ -835,7 +835,7 @@ @syntax { - @subid 1699 + @subid 2583 @assert { @@ -857,7 +857,7 @@ @syntax { - @subid 1700 + @subid 2584 @assert { @@ -879,7 +879,7 @@ @syntax { - @subid 1701 + @subid 2585 @assert { @@ -901,7 +901,7 @@ @syntax { - @subid 1702 + @subid 2586 @assert { @@ -923,7 +923,7 @@ @syntax { - @subid 1703 + @subid 2587 @assert { @@ -945,7 +945,7 @@ @syntax { - @subid 1704 + @subid 2588 @assert { @@ -967,7 +967,7 @@ @syntax { - @subid 1705 + @subid 2589 @assert { @@ -989,7 +989,7 @@ @syntax { - @subid 1706 + @subid 2590 @assert { @@ -1011,7 +1011,7 @@ @syntax { - @subid 1707 + @subid 2591 @assert { @@ -1033,7 +1033,7 @@ @syntax { - @subid 1708 + @subid 2592 @assert { @@ -1055,7 +1055,7 @@ @syntax { - @subid 1709 + @subid 2593 @assert { @@ -1077,7 +1077,7 @@ @syntax { - @subid 1710 + @subid 2594 @assert { @@ -1099,7 +1099,7 @@ @syntax { - @subid 1711 + @subid 2595 @assert { @@ -1121,7 +1121,7 @@ @syntax { - @subid 1712 + @subid 2596 @assert { @@ -1143,7 +1143,7 @@ @syntax { - @subid 1713 + @subid 2597 @assert { @@ -1165,7 +1165,7 @@ @syntax { - @subid 1714 + @subid 2598 @assert { @@ -1187,7 +1187,7 @@ @syntax { - @subid 1715 + @subid 2599 @assert { @@ -1209,7 +1209,7 @@ @syntax { - @subid 1716 + @subid 2600 @assert { @@ -1231,7 +1231,7 @@ @syntax { - @subid 1717 + @subid 2601 @assert { @@ -1253,7 +1253,7 @@ @syntax { - @subid 1718 + @subid 2602 @assert { diff --git a/plugins/arm/v7/opdefs/A88360_vorr.d b/plugins/arm/v7/opdefs/A88360_vorr.d index 6878274..4b2b592 100644 --- a/plugins/arm/v7/opdefs/A88360_vorr.d +++ b/plugins/arm/v7/opdefs/A88360_vorr.d @@ -23,7 +23,7 @@ @title VORR (register) -@id 332 +@id 341 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1719 + @subid 2603 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1720 + @subid 2604 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 1721 + @subid 2605 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1722 + @subid 2606 @assert { diff --git a/plugins/arm/v7/opdefs/A88361_vpadal.d b/plugins/arm/v7/opdefs/A88361_vpadal.d index 6c5aeac..86116f0 100644 --- a/plugins/arm/v7/opdefs/A88361_vpadal.d +++ b/plugins/arm/v7/opdefs/A88361_vpadal.d @@ -23,7 +23,7 @@ @title VPADAL -@id 333 +@id 342 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1723 + @subid 2607 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1724 + @subid 2608 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1725 + @subid 2609 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1726 + @subid 2610 @assert { @@ -129,7 +129,7 @@ @syntax { - @subid 1727 + @subid 2611 @assert { @@ -152,7 +152,7 @@ @syntax { - @subid 1728 + @subid 2612 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 1729 + @subid 2613 @assert { @@ -198,7 +198,7 @@ @syntax { - @subid 1730 + @subid 2614 @assert { @@ -221,7 +221,7 @@ @syntax { - @subid 1731 + @subid 2615 @assert { @@ -244,7 +244,7 @@ @syntax { - @subid 1732 + @subid 2616 @assert { @@ -267,7 +267,7 @@ @syntax { - @subid 1733 + @subid 2617 @assert { @@ -290,7 +290,7 @@ @syntax { - @subid 1734 + @subid 2618 @assert { @@ -319,7 +319,7 @@ @syntax { - @subid 1735 + @subid 2619 @assert { @@ -342,7 +342,7 @@ @syntax { - @subid 1736 + @subid 2620 @assert { @@ -365,7 +365,7 @@ @syntax { - @subid 1737 + @subid 2621 @assert { @@ -388,7 +388,7 @@ @syntax { - @subid 1738 + @subid 2622 @assert { @@ -411,7 +411,7 @@ @syntax { - @subid 1739 + @subid 2623 @assert { @@ -434,7 +434,7 @@ @syntax { - @subid 1740 + @subid 2624 @assert { @@ -457,7 +457,7 @@ @syntax { - @subid 1741 + @subid 2625 @assert { @@ -480,7 +480,7 @@ @syntax { - @subid 1742 + @subid 2626 @assert { @@ -503,7 +503,7 @@ @syntax { - @subid 1743 + @subid 2627 @assert { @@ -526,7 +526,7 @@ @syntax { - @subid 1744 + @subid 2628 @assert { @@ -549,7 +549,7 @@ @syntax { - @subid 1745 + @subid 2629 @assert { @@ -572,7 +572,7 @@ @syntax { - @subid 1746 + @subid 2630 @assert { diff --git a/plugins/arm/v7/opdefs/A88362_vpadd.d b/plugins/arm/v7/opdefs/A88362_vpadd.d index 53b56f9..60c102a 100644 --- a/plugins/arm/v7/opdefs/A88362_vpadd.d +++ b/plugins/arm/v7/opdefs/A88362_vpadd.d @@ -23,7 +23,7 @@ @title VPADD (integer) -@id 334 +@id 343 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1747 + @subid 2631 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1748 + @subid 2632 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1749 + @subid 2633 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 1750 + @subid 2634 @assert { @@ -135,7 +135,7 @@ @syntax { - @subid 1751 + @subid 2635 @assert { @@ -158,7 +158,7 @@ @syntax { - @subid 1752 + @subid 2636 @assert { diff --git a/plugins/arm/v7/opdefs/A88363_vpadd.d b/plugins/arm/v7/opdefs/A88363_vpadd.d index 8149449..eb7a2fc 100644 --- a/plugins/arm/v7/opdefs/A88363_vpadd.d +++ b/plugins/arm/v7/opdefs/A88363_vpadd.d @@ -23,7 +23,7 @@ @title VPADD (floating-point) -@id 335 +@id 344 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1753 + @subid 2637 @assert { @@ -66,7 +66,7 @@ @syntax { - @subid 1754 + @subid 2638 @assert { diff --git a/plugins/arm/v7/opdefs/A88364_vpaddl.d b/plugins/arm/v7/opdefs/A88364_vpaddl.d index 68e83c9..679e206 100644 --- a/plugins/arm/v7/opdefs/A88364_vpaddl.d +++ b/plugins/arm/v7/opdefs/A88364_vpaddl.d @@ -23,7 +23,7 @@ @title VPADDL -@id 336 +@id 345 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1755 + @subid 2639 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1756 + @subid 2640 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1757 + @subid 2641 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1758 + @subid 2642 @assert { @@ -129,7 +129,7 @@ @syntax { - @subid 1759 + @subid 2643 @assert { @@ -152,7 +152,7 @@ @syntax { - @subid 1760 + @subid 2644 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 1761 + @subid 2645 @assert { @@ -198,7 +198,7 @@ @syntax { - @subid 1762 + @subid 2646 @assert { @@ -221,7 +221,7 @@ @syntax { - @subid 1763 + @subid 2647 @assert { @@ -244,7 +244,7 @@ @syntax { - @subid 1764 + @subid 2648 @assert { @@ -267,7 +267,7 @@ @syntax { - @subid 1765 + @subid 2649 @assert { @@ -290,7 +290,7 @@ @syntax { - @subid 1766 + @subid 2650 @assert { @@ -319,7 +319,7 @@ @syntax { - @subid 1767 + @subid 2651 @assert { @@ -342,7 +342,7 @@ @syntax { - @subid 1768 + @subid 2652 @assert { @@ -365,7 +365,7 @@ @syntax { - @subid 1769 + @subid 2653 @assert { @@ -388,7 +388,7 @@ @syntax { - @subid 1770 + @subid 2654 @assert { @@ -411,7 +411,7 @@ @syntax { - @subid 1771 + @subid 2655 @assert { @@ -434,7 +434,7 @@ @syntax { - @subid 1772 + @subid 2656 @assert { @@ -457,7 +457,7 @@ @syntax { - @subid 1773 + @subid 2657 @assert { @@ -480,7 +480,7 @@ @syntax { - @subid 1774 + @subid 2658 @assert { @@ -503,7 +503,7 @@ @syntax { - @subid 1775 + @subid 2659 @assert { @@ -526,7 +526,7 @@ @syntax { - @subid 1776 + @subid 2660 @assert { @@ -549,7 +549,7 @@ @syntax { - @subid 1777 + @subid 2661 @assert { @@ -572,7 +572,7 @@ @syntax { - @subid 1778 + @subid 2662 @assert { diff --git a/plugins/arm/v7/opdefs/A88365_vpmax.d b/plugins/arm/v7/opdefs/A88365_vpmax.d index e36d35b..facb2a7 100644 --- a/plugins/arm/v7/opdefs/A88365_vpmax.d +++ b/plugins/arm/v7/opdefs/A88365_vpmax.d @@ -23,7 +23,7 @@ @title VPMAX, VPMIN (integer) -@id 337 +@id 346 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1779 + @subid 2663 @assert { @@ -62,7 +62,7 @@ @syntax { - @subid 1780 + @subid 2664 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 1781 + @subid 2665 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 1782 + @subid 2666 @assert { @@ -137,7 +137,7 @@ @syntax { - @subid 1783 + @subid 2667 @assert { @@ -162,7 +162,7 @@ @syntax { - @subid 1784 + @subid 2668 @assert { @@ -187,7 +187,7 @@ @syntax { - @subid 1785 + @subid 2669 @assert { @@ -212,7 +212,7 @@ @syntax { - @subid 1786 + @subid 2670 @assert { @@ -237,7 +237,7 @@ @syntax { - @subid 1787 + @subid 2671 @assert { @@ -262,7 +262,7 @@ @syntax { - @subid 1788 + @subid 2672 @assert { @@ -287,7 +287,7 @@ @syntax { - @subid 1789 + @subid 2673 @assert { @@ -312,7 +312,7 @@ @syntax { - @subid 1790 + @subid 2674 @assert { @@ -343,7 +343,7 @@ @syntax { - @subid 1791 + @subid 2675 @assert { @@ -368,7 +368,7 @@ @syntax { - @subid 1792 + @subid 2676 @assert { @@ -393,7 +393,7 @@ @syntax { - @subid 1793 + @subid 2677 @assert { @@ -418,7 +418,7 @@ @syntax { - @subid 1794 + @subid 2678 @assert { @@ -443,7 +443,7 @@ @syntax { - @subid 1795 + @subid 2679 @assert { @@ -468,7 +468,7 @@ @syntax { - @subid 1796 + @subid 2680 @assert { @@ -493,7 +493,7 @@ @syntax { - @subid 1797 + @subid 2681 @assert { @@ -518,7 +518,7 @@ @syntax { - @subid 1798 + @subid 2682 @assert { @@ -543,7 +543,7 @@ @syntax { - @subid 1799 + @subid 2683 @assert { @@ -568,7 +568,7 @@ @syntax { - @subid 1800 + @subid 2684 @assert { @@ -593,7 +593,7 @@ @syntax { - @subid 1801 + @subid 2685 @assert { @@ -618,7 +618,7 @@ @syntax { - @subid 1802 + @subid 2686 @assert { diff --git a/plugins/arm/v7/opdefs/A88366_vpmax.d b/plugins/arm/v7/opdefs/A88366_vpmax.d index d927f44..a6785a6 100644 --- a/plugins/arm/v7/opdefs/A88366_vpmax.d +++ b/plugins/arm/v7/opdefs/A88366_vpmax.d @@ -23,7 +23,7 @@ @title VPMAX, VPMIN (floating-point) -@id 338 +@id 347 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1803 + @subid 2687 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1804 + @subid 2688 @assert { @@ -91,7 +91,7 @@ @syntax { - @subid 1805 + @subid 2689 @assert { @@ -115,7 +115,7 @@ @syntax { - @subid 1806 + @subid 2690 @assert { diff --git a/plugins/arm/v7/opdefs/A88367_vpop.d b/plugins/arm/v7/opdefs/A88367_vpop.d new file mode 100644 index 0000000..56f82b8 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88367_vpop.d @@ -0,0 +1,113 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VPOP + +@id 348 + +@desc { + + Vector Pop loads multiple consecutive extension registers from the stack. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 0 1 D(1) 1 1 1 1 0 1 Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 2691 + + @conv { + + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vpop list + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 1 0 0 1 D(1) 1 1 1 1 0 1 Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 2692 + + @conv { + + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vpop list + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 0 1 D(1) 1 1 1 1 0 1 Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 2693 + + @conv { + + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vpop list + + } + +} + +@encoding (A2) { + + @word 1 1 1 0 1 1 0 0 1 D(1) 1 1 1 1 0 1 Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 2694 + + @conv { + + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vpop list + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88368_vpush.d b/plugins/arm/v7/opdefs/A88368_vpush.d new file mode 100644 index 0000000..2e26a34 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88368_vpush.d @@ -0,0 +1,113 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VPUSH + +@id 349 + +@desc { + + Vector Push stores multiple consecutive extension registers to the stack. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 1 0 D(1) 1 0 1 1 0 1 Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 2695 + + @conv { + + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vpush list + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 1 0 1 0 D(1) 1 0 1 1 0 1 Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 2696 + + @conv { + + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vpush list + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 1 0 D(1) 1 0 1 1 0 1 Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 2697 + + @conv { + + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vpush list + + } + +} + +@encoding (A2) { + + @word 1 1 1 0 1 1 0 1 0 D(1) 1 0 1 1 0 1 Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 2698 + + @conv { + + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vpush list + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88369_vqabs.d b/plugins/arm/v7/opdefs/A88369_vqabs.d index de4af39..8a50563 100644 --- a/plugins/arm/v7/opdefs/A88369_vqabs.d +++ b/plugins/arm/v7/opdefs/A88369_vqabs.d @@ -23,7 +23,7 @@ @title VQABS -@id 339 +@id 350 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1807 + @subid 2699 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1808 + @subid 2700 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1809 + @subid 2701 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1810 + @subid 2702 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 1811 + @subid 2703 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 1812 + @subid 2704 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 1813 + @subid 2705 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 1814 + @subid 2706 @assert { @@ -219,7 +219,7 @@ @syntax { - @subid 1815 + @subid 2707 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 1816 + @subid 2708 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 1817 + @subid 2709 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 1818 + @subid 2710 @assert { diff --git a/plugins/arm/v7/opdefs/A88370_vqadd.d b/plugins/arm/v7/opdefs/A88370_vqadd.d index d5cf213..18e46e7 100644 --- a/plugins/arm/v7/opdefs/A88370_vqadd.d +++ b/plugins/arm/v7/opdefs/A88370_vqadd.d @@ -23,7 +23,7 @@ @title VQADD -@id 340 +@id 351 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1819 + @subid 2711 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1820 + @subid 2712 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1821 + @subid 2713 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1822 + @subid 2714 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 1823 + @subid 2715 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1824 + @subid 2716 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1825 + @subid 2717 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 1826 + @subid 2718 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 1827 + @subid 2719 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 1828 + @subid 2720 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 1829 + @subid 2721 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1830 + @subid 2722 @assert { @@ -325,7 +325,7 @@ @syntax { - @subid 1831 + @subid 2723 @assert { @@ -349,7 +349,7 @@ @syntax { - @subid 1832 + @subid 2724 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 1833 + @subid 2725 @assert { @@ -397,7 +397,7 @@ @syntax { - @subid 1834 + @subid 2726 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 1835 + @subid 2727 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 1836 + @subid 2728 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 1837 + @subid 2729 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1838 + @subid 2730 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 1839 + @subid 2731 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 1840 + @subid 2732 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 1841 + @subid 2733 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 1842 + @subid 2734 @assert { @@ -619,7 +619,7 @@ @syntax { - @subid 1843 + @subid 2735 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 1844 + @subid 2736 @assert { @@ -667,7 +667,7 @@ @syntax { - @subid 1845 + @subid 2737 @assert { @@ -691,7 +691,7 @@ @syntax { - @subid 1846 + @subid 2738 @assert { @@ -715,7 +715,7 @@ @syntax { - @subid 1847 + @subid 2739 @assert { @@ -739,7 +739,7 @@ @syntax { - @subid 1848 + @subid 2740 @assert { @@ -763,7 +763,7 @@ @syntax { - @subid 1849 + @subid 2741 @assert { @@ -787,7 +787,7 @@ @syntax { - @subid 1850 + @subid 2742 @assert { diff --git a/plugins/arm/v7/opdefs/A88374_vqmov.d b/plugins/arm/v7/opdefs/A88374_vqmov.d index 32a2dd0..6127f9d 100644 --- a/plugins/arm/v7/opdefs/A88374_vqmov.d +++ b/plugins/arm/v7/opdefs/A88374_vqmov.d @@ -23,7 +23,7 @@ @title VQMOVN, VQMOVUN -@id 341 +@id 352 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1851 + @subid 2743 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1852 + @subid 2744 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1853 + @subid 2745 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1854 + @subid 2746 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 1855 + @subid 2747 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 1856 + @subid 2748 @assert { @@ -169,7 +169,7 @@ @syntax { - @subid 1857 + @subid 2749 @assert { @@ -191,7 +191,7 @@ @syntax { - @subid 1858 + @subid 2750 @assert { @@ -213,7 +213,7 @@ @syntax { - @subid 1859 + @subid 2751 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 1860 + @subid 2752 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 1861 + @subid 2753 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 1862 + @subid 2754 @assert { @@ -307,7 +307,7 @@ @syntax { - @subid 1863 + @subid 2755 @assert { @@ -329,7 +329,7 @@ @syntax { - @subid 1864 + @subid 2756 @assert { @@ -351,7 +351,7 @@ @syntax { - @subid 1865 + @subid 2757 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 1866 + @subid 2758 @assert { @@ -395,7 +395,7 @@ @syntax { - @subid 1867 + @subid 2759 @assert { @@ -417,7 +417,7 @@ @syntax { - @subid 1868 + @subid 2760 @assert { diff --git a/plugins/arm/v7/opdefs/A88375_vqneg.d b/plugins/arm/v7/opdefs/A88375_vqneg.d index 408c817..873107f 100644 --- a/plugins/arm/v7/opdefs/A88375_vqneg.d +++ b/plugins/arm/v7/opdefs/A88375_vqneg.d @@ -23,7 +23,7 @@ @title VQNEG -@id 342 +@id 353 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1869 + @subid 2761 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1870 + @subid 2762 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1871 + @subid 2763 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 1872 + @subid 2764 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 1873 + @subid 2765 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 1874 + @subid 2766 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 1875 + @subid 2767 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 1876 + @subid 2768 @assert { @@ -219,7 +219,7 @@ @syntax { - @subid 1877 + @subid 2769 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 1878 + @subid 2770 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 1879 + @subid 2771 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 1880 + @subid 2772 @assert { diff --git a/plugins/arm/v7/opdefs/A88377_vqrshl.d b/plugins/arm/v7/opdefs/A88377_vqrshl.d index 3b2b83b..36ac81e 100644 --- a/plugins/arm/v7/opdefs/A88377_vqrshl.d +++ b/plugins/arm/v7/opdefs/A88377_vqrshl.d @@ -23,7 +23,7 @@ @title VQRSHL -@id 343 +@id 354 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1881 + @subid 2773 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1882 + @subid 2774 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1883 + @subid 2775 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1884 + @subid 2776 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 1885 + @subid 2777 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1886 + @subid 2778 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1887 + @subid 2779 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 1888 + @subid 2780 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 1889 + @subid 2781 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 1890 + @subid 2782 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 1891 + @subid 2783 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1892 + @subid 2784 @assert { @@ -325,7 +325,7 @@ @syntax { - @subid 1893 + @subid 2785 @assert { @@ -349,7 +349,7 @@ @syntax { - @subid 1894 + @subid 2786 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 1895 + @subid 2787 @assert { @@ -397,7 +397,7 @@ @syntax { - @subid 1896 + @subid 2788 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 1897 + @subid 2789 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 1898 + @subid 2790 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 1899 + @subid 2791 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1900 + @subid 2792 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 1901 + @subid 2793 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 1902 + @subid 2794 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 1903 + @subid 2795 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 1904 + @subid 2796 @assert { @@ -619,7 +619,7 @@ @syntax { - @subid 1905 + @subid 2797 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 1906 + @subid 2798 @assert { @@ -667,7 +667,7 @@ @syntax { - @subid 1907 + @subid 2799 @assert { @@ -691,7 +691,7 @@ @syntax { - @subid 1908 + @subid 2800 @assert { @@ -715,7 +715,7 @@ @syntax { - @subid 1909 + @subid 2801 @assert { @@ -739,7 +739,7 @@ @syntax { - @subid 1910 + @subid 2802 @assert { @@ -763,7 +763,7 @@ @syntax { - @subid 1911 + @subid 2803 @assert { @@ -787,7 +787,7 @@ @syntax { - @subid 1912 + @subid 2804 @assert { diff --git a/plugins/arm/v7/opdefs/A88379_vqshl.d b/plugins/arm/v7/opdefs/A88379_vqshl.d index fee9008..81b0f15 100644 --- a/plugins/arm/v7/opdefs/A88379_vqshl.d +++ b/plugins/arm/v7/opdefs/A88379_vqshl.d @@ -23,7 +23,7 @@ @title VQSHL (register) -@id 344 +@id 355 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1913 + @subid 2805 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1914 + @subid 2806 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1915 + @subid 2807 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1916 + @subid 2808 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 1917 + @subid 2809 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1918 + @subid 2810 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1919 + @subid 2811 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 1920 + @subid 2812 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 1921 + @subid 2813 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 1922 + @subid 2814 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 1923 + @subid 2815 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1924 + @subid 2816 @assert { @@ -325,7 +325,7 @@ @syntax { - @subid 1925 + @subid 2817 @assert { @@ -349,7 +349,7 @@ @syntax { - @subid 1926 + @subid 2818 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 1927 + @subid 2819 @assert { @@ -397,7 +397,7 @@ @syntax { - @subid 1928 + @subid 2820 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 1929 + @subid 2821 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 1930 + @subid 2822 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 1931 + @subid 2823 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1932 + @subid 2824 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 1933 + @subid 2825 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 1934 + @subid 2826 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 1935 + @subid 2827 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 1936 + @subid 2828 @assert { @@ -619,7 +619,7 @@ @syntax { - @subid 1937 + @subid 2829 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 1938 + @subid 2830 @assert { @@ -667,7 +667,7 @@ @syntax { - @subid 1939 + @subid 2831 @assert { @@ -691,7 +691,7 @@ @syntax { - @subid 1940 + @subid 2832 @assert { @@ -715,7 +715,7 @@ @syntax { - @subid 1941 + @subid 2833 @assert { @@ -739,7 +739,7 @@ @syntax { - @subid 1942 + @subid 2834 @assert { @@ -763,7 +763,7 @@ @syntax { - @subid 1943 + @subid 2835 @assert { @@ -787,7 +787,7 @@ @syntax { - @subid 1944 + @subid 2836 @assert { diff --git a/plugins/arm/v7/opdefs/A88382_vqsub.d b/plugins/arm/v7/opdefs/A88382_vqsub.d index 248f826..202ea01 100644 --- a/plugins/arm/v7/opdefs/A88382_vqsub.d +++ b/plugins/arm/v7/opdefs/A88382_vqsub.d @@ -23,7 +23,7 @@ @title VQSUB -@id 345 +@id 356 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1945 + @subid 2837 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 1946 + @subid 2838 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 1947 + @subid 2839 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1948 + @subid 2840 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 1949 + @subid 2841 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 1950 + @subid 2842 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1951 + @subid 2843 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 1952 + @subid 2844 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 1953 + @subid 2845 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 1954 + @subid 2846 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 1955 + @subid 2847 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 1956 + @subid 2848 @assert { @@ -325,7 +325,7 @@ @syntax { - @subid 1957 + @subid 2849 @assert { @@ -349,7 +349,7 @@ @syntax { - @subid 1958 + @subid 2850 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 1959 + @subid 2851 @assert { @@ -397,7 +397,7 @@ @syntax { - @subid 1960 + @subid 2852 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 1961 + @subid 2853 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 1962 + @subid 2854 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 1963 + @subid 2855 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 1964 + @subid 2856 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 1965 + @subid 2857 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 1966 + @subid 2858 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 1967 + @subid 2859 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 1968 + @subid 2860 @assert { @@ -619,7 +619,7 @@ @syntax { - @subid 1969 + @subid 2861 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 1970 + @subid 2862 @assert { @@ -667,7 +667,7 @@ @syntax { - @subid 1971 + @subid 2863 @assert { @@ -691,7 +691,7 @@ @syntax { - @subid 1972 + @subid 2864 @assert { @@ -715,7 +715,7 @@ @syntax { - @subid 1973 + @subid 2865 @assert { @@ -739,7 +739,7 @@ @syntax { - @subid 1974 + @subid 2866 @assert { @@ -763,7 +763,7 @@ @syntax { - @subid 1975 + @subid 2867 @assert { @@ -787,7 +787,7 @@ @syntax { - @subid 1976 + @subid 2868 @assert { diff --git a/plugins/arm/v7/opdefs/A88383_vraddhn.d b/plugins/arm/v7/opdefs/A88383_vraddhn.d index 731ebbb..ea8fe9d 100644 --- a/plugins/arm/v7/opdefs/A88383_vraddhn.d +++ b/plugins/arm/v7/opdefs/A88383_vraddhn.d @@ -23,7 +23,7 @@ @title VRADDHN -@id 346 +@id 357 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1977 + @subid 2869 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1978 + @subid 2870 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 1979 + @subid 2871 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1980 + @subid 2872 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 1981 + @subid 2873 @assert { @@ -153,7 +153,7 @@ @syntax { - @subid 1982 + @subid 2874 @assert { diff --git a/plugins/arm/v7/opdefs/A88384_vrecpe.d b/plugins/arm/v7/opdefs/A88384_vrecpe.d index 4e3bc18..56c3c24 100644 --- a/plugins/arm/v7/opdefs/A88384_vrecpe.d +++ b/plugins/arm/v7/opdefs/A88384_vrecpe.d @@ -23,7 +23,7 @@ @title VRECPE -@id 347 +@id 358 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1983 + @subid 2875 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1984 + @subid 2876 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1985 + @subid 2877 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1986 + @subid 2878 @assert { @@ -135,7 +135,7 @@ @syntax { - @subid 1987 + @subid 2879 @assert { @@ -158,7 +158,7 @@ @syntax { - @subid 1988 + @subid 2880 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 1989 + @subid 2881 @assert { @@ -204,7 +204,7 @@ @syntax { - @subid 1990 + @subid 2882 @assert { diff --git a/plugins/arm/v7/opdefs/A88385_vrecps.d b/plugins/arm/v7/opdefs/A88385_vrecps.d index 6d8387a..adb8b43 100644 --- a/plugins/arm/v7/opdefs/A88385_vrecps.d +++ b/plugins/arm/v7/opdefs/A88385_vrecps.d @@ -23,7 +23,7 @@ @title VRECPS -@id 348 +@id 359 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1991 + @subid 2883 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 1992 + @subid 2884 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 1993 + @subid 2885 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 1994 + @subid 2886 @assert { diff --git a/plugins/arm/v7/opdefs/A88386_vrev.d b/plugins/arm/v7/opdefs/A88386_vrev.d index c442e06..b8d10fe 100644 --- a/plugins/arm/v7/opdefs/A88386_vrev.d +++ b/plugins/arm/v7/opdefs/A88386_vrev.d @@ -23,7 +23,7 @@ @title VREV16, VREV32, VREV64 -@id 349 +@id 360 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 1995 + @subid 2887 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 1996 + @subid 2888 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 1997 + @subid 2889 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 1998 + @subid 2890 @assert { @@ -129,7 +129,7 @@ @syntax { - @subid 1999 + @subid 2891 @assert { @@ -152,7 +152,7 @@ @syntax { - @subid 2000 + @subid 2892 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 2001 + @subid 2893 @assert { @@ -198,7 +198,7 @@ @syntax { - @subid 2002 + @subid 2894 @assert { @@ -221,7 +221,7 @@ @syntax { - @subid 2003 + @subid 2895 @assert { @@ -244,7 +244,7 @@ @syntax { - @subid 2004 + @subid 2896 @assert { @@ -267,7 +267,7 @@ @syntax { - @subid 2005 + @subid 2897 @assert { @@ -290,7 +290,7 @@ @syntax { - @subid 2006 + @subid 2898 @assert { @@ -313,7 +313,7 @@ @syntax { - @subid 2007 + @subid 2899 @assert { @@ -336,7 +336,7 @@ @syntax { - @subid 2008 + @subid 2900 @assert { @@ -359,7 +359,7 @@ @syntax { - @subid 2009 + @subid 2901 @assert { @@ -382,7 +382,7 @@ @syntax { - @subid 2010 + @subid 2902 @assert { @@ -405,7 +405,7 @@ @syntax { - @subid 2011 + @subid 2903 @assert { @@ -428,7 +428,7 @@ @syntax { - @subid 2012 + @subid 2904 @assert { @@ -457,7 +457,7 @@ @syntax { - @subid 2013 + @subid 2905 @assert { @@ -480,7 +480,7 @@ @syntax { - @subid 2014 + @subid 2906 @assert { @@ -503,7 +503,7 @@ @syntax { - @subid 2015 + @subid 2907 @assert { @@ -526,7 +526,7 @@ @syntax { - @subid 2016 + @subid 2908 @assert { @@ -549,7 +549,7 @@ @syntax { - @subid 2017 + @subid 2909 @assert { @@ -572,7 +572,7 @@ @syntax { - @subid 2018 + @subid 2910 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 2019 + @subid 2911 @assert { @@ -618,7 +618,7 @@ @syntax { - @subid 2020 + @subid 2912 @assert { @@ -641,7 +641,7 @@ @syntax { - @subid 2021 + @subid 2913 @assert { @@ -664,7 +664,7 @@ @syntax { - @subid 2022 + @subid 2914 @assert { @@ -687,7 +687,7 @@ @syntax { - @subid 2023 + @subid 2915 @assert { @@ -710,7 +710,7 @@ @syntax { - @subid 2024 + @subid 2916 @assert { @@ -733,7 +733,7 @@ @syntax { - @subid 2025 + @subid 2917 @assert { @@ -756,7 +756,7 @@ @syntax { - @subid 2026 + @subid 2918 @assert { @@ -779,7 +779,7 @@ @syntax { - @subid 2027 + @subid 2919 @assert { @@ -802,7 +802,7 @@ @syntax { - @subid 2028 + @subid 2920 @assert { @@ -825,7 +825,7 @@ @syntax { - @subid 2029 + @subid 2921 @assert { @@ -848,7 +848,7 @@ @syntax { - @subid 2030 + @subid 2922 @assert { diff --git a/plugins/arm/v7/opdefs/A88387_vrhadd.d b/plugins/arm/v7/opdefs/A88387_vrhadd.d index e97aeaa..e8671b7 100644 --- a/plugins/arm/v7/opdefs/A88387_vrhadd.d +++ b/plugins/arm/v7/opdefs/A88387_vrhadd.d @@ -23,7 +23,7 @@ @title VRHADD -@id 350 +@id 361 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2031 + @subid 2923 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 2032 + @subid 2924 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 2033 + @subid 2925 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2034 + @subid 2926 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 2035 + @subid 2927 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 2036 + @subid 2928 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 2037 + @subid 2929 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 2038 + @subid 2930 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 2039 + @subid 2931 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 2040 + @subid 2932 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 2041 + @subid 2933 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 2042 + @subid 2934 @assert { @@ -331,7 +331,7 @@ @syntax { - @subid 2043 + @subid 2935 @assert { @@ -355,7 +355,7 @@ @syntax { - @subid 2044 + @subid 2936 @assert { @@ -379,7 +379,7 @@ @syntax { - @subid 2045 + @subid 2937 @assert { @@ -403,7 +403,7 @@ @syntax { - @subid 2046 + @subid 2938 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 2047 + @subid 2939 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 2048 + @subid 2940 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 2049 + @subid 2941 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 2050 + @subid 2942 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 2051 + @subid 2943 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 2052 + @subid 2944 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 2053 + @subid 2945 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 2054 + @subid 2946 @assert { diff --git a/plugins/arm/v7/opdefs/A88388_vrshl.d b/plugins/arm/v7/opdefs/A88388_vrshl.d index 7291599..9f7551a 100644 --- a/plugins/arm/v7/opdefs/A88388_vrshl.d +++ b/plugins/arm/v7/opdefs/A88388_vrshl.d @@ -23,7 +23,7 @@ @title VRSHL -@id 351 +@id 362 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2055 + @subid 2947 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 2056 + @subid 2948 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 2057 + @subid 2949 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2058 + @subid 2950 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 2059 + @subid 2951 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 2060 + @subid 2952 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 2061 + @subid 2953 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 2062 + @subid 2954 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 2063 + @subid 2955 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 2064 + @subid 2956 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 2065 + @subid 2957 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 2066 + @subid 2958 @assert { @@ -325,7 +325,7 @@ @syntax { - @subid 2067 + @subid 2959 @assert { @@ -349,7 +349,7 @@ @syntax { - @subid 2068 + @subid 2960 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 2069 + @subid 2961 @assert { @@ -397,7 +397,7 @@ @syntax { - @subid 2070 + @subid 2962 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 2071 + @subid 2963 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 2072 + @subid 2964 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 2073 + @subid 2965 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 2074 + @subid 2966 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 2075 + @subid 2967 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 2076 + @subid 2968 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 2077 + @subid 2969 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 2078 + @subid 2970 @assert { @@ -619,7 +619,7 @@ @syntax { - @subid 2079 + @subid 2971 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 2080 + @subid 2972 @assert { @@ -667,7 +667,7 @@ @syntax { - @subid 2081 + @subid 2973 @assert { @@ -691,7 +691,7 @@ @syntax { - @subid 2082 + @subid 2974 @assert { @@ -715,7 +715,7 @@ @syntax { - @subid 2083 + @subid 2975 @assert { @@ -739,7 +739,7 @@ @syntax { - @subid 2084 + @subid 2976 @assert { @@ -763,7 +763,7 @@ @syntax { - @subid 2085 + @subid 2977 @assert { @@ -787,7 +787,7 @@ @syntax { - @subid 2086 + @subid 2978 @assert { diff --git a/plugins/arm/v7/opdefs/A88391_vrsqrte.d b/plugins/arm/v7/opdefs/A88391_vrsqrte.d index ef55798..050dc18 100644 --- a/plugins/arm/v7/opdefs/A88391_vrsqrte.d +++ b/plugins/arm/v7/opdefs/A88391_vrsqrte.d @@ -23,7 +23,7 @@ @title VRSQRTE -@id 352 +@id 363 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2087 + @subid 2979 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 2088 + @subid 2980 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 2089 + @subid 2981 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 2090 + @subid 2982 @assert { @@ -135,7 +135,7 @@ @syntax { - @subid 2091 + @subid 2983 @assert { @@ -158,7 +158,7 @@ @syntax { - @subid 2092 + @subid 2984 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 2093 + @subid 2985 @assert { @@ -204,7 +204,7 @@ @syntax { - @subid 2094 + @subid 2986 @assert { diff --git a/plugins/arm/v7/opdefs/A88392_vrsqrts.d b/plugins/arm/v7/opdefs/A88392_vrsqrts.d index fdf4d41..7e5f52c 100644 --- a/plugins/arm/v7/opdefs/A88392_vrsqrts.d +++ b/plugins/arm/v7/opdefs/A88392_vrsqrts.d @@ -23,7 +23,7 @@ @title VRSQRTS -@id 353 +@id 364 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2095 + @subid 2987 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 2096 + @subid 2988 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 2097 + @subid 2989 @assert { @@ -112,7 +112,7 @@ @syntax { - @subid 2098 + @subid 2990 @assert { diff --git a/plugins/arm/v7/opdefs/A88394_vrsubhn.d b/plugins/arm/v7/opdefs/A88394_vrsubhn.d index 8ff3228..9dc7085 100644 --- a/plugins/arm/v7/opdefs/A88394_vrsubhn.d +++ b/plugins/arm/v7/opdefs/A88394_vrsubhn.d @@ -23,7 +23,7 @@ @title VRSUBHN -@id 354 +@id 365 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2099 + @subid 2991 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2100 + @subid 2992 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 2101 + @subid 2993 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2102 + @subid 2994 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 2103 + @subid 2995 @assert { @@ -153,7 +153,7 @@ @syntax { - @subid 2104 + @subid 2996 @assert { diff --git a/plugins/arm/v7/opdefs/A88396_vshl.d b/plugins/arm/v7/opdefs/A88396_vshl.d index 85a0446..b41026f 100644 --- a/plugins/arm/v7/opdefs/A88396_vshl.d +++ b/plugins/arm/v7/opdefs/A88396_vshl.d @@ -23,7 +23,7 @@ @title VSHL (register) -@id 355 +@id 366 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2105 + @subid 2997 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 2106 + @subid 2998 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 2107 + @subid 2999 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2108 + @subid 3000 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 2109 + @subid 3001 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 2110 + @subid 3002 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 2111 + @subid 3003 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 2112 + @subid 3004 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 2113 + @subid 3005 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 2114 + @subid 3006 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 2115 + @subid 3007 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 2116 + @subid 3008 @assert { @@ -325,7 +325,7 @@ @syntax { - @subid 2117 + @subid 3009 @assert { @@ -349,7 +349,7 @@ @syntax { - @subid 2118 + @subid 3010 @assert { @@ -373,7 +373,7 @@ @syntax { - @subid 2119 + @subid 3011 @assert { @@ -397,7 +397,7 @@ @syntax { - @subid 2120 + @subid 3012 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 2121 + @subid 3013 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 2122 + @subid 3014 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 2123 + @subid 3015 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 2124 + @subid 3016 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 2125 + @subid 3017 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 2126 + @subid 3018 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 2127 + @subid 3019 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 2128 + @subid 3020 @assert { @@ -619,7 +619,7 @@ @syntax { - @subid 2129 + @subid 3021 @assert { @@ -643,7 +643,7 @@ @syntax { - @subid 2130 + @subid 3022 @assert { @@ -667,7 +667,7 @@ @syntax { - @subid 2131 + @subid 3023 @assert { @@ -691,7 +691,7 @@ @syntax { - @subid 2132 + @subid 3024 @assert { @@ -715,7 +715,7 @@ @syntax { - @subid 2133 + @subid 3025 @assert { @@ -739,7 +739,7 @@ @syntax { - @subid 2134 + @subid 3026 @assert { @@ -763,7 +763,7 @@ @syntax { - @subid 2135 + @subid 3027 @assert { @@ -787,7 +787,7 @@ @syntax { - @subid 2136 + @subid 3028 @assert { diff --git a/plugins/arm/v7/opdefs/A88401_vsqrt.d b/plugins/arm/v7/opdefs/A88401_vsqrt.d index 9cf2222..786bb98 100644 --- a/plugins/arm/v7/opdefs/A88401_vsqrt.d +++ b/plugins/arm/v7/opdefs/A88401_vsqrt.d @@ -23,7 +23,7 @@ @title VSQRT -@id 356 +@id 367 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2137 + @subid 3029 @assert { @@ -58,7 +58,7 @@ @syntax { - @subid 2138 + @subid 3030 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 2139 + @subid 3031 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 2140 + @subid 3032 @assert { diff --git a/plugins/arm/v7/opdefs/A88404_vst1.d b/plugins/arm/v7/opdefs/A88404_vst1.d new file mode 100644 index 0000000..5be4548 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88404_vst1.d @@ -0,0 +1,6117 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VST1 (multiple single elements) + +@id 368 + +@desc { + + Vector Store (multiple single elements) stores elements to memory from one, two, three, or four registers, without interleaving. Every element of each register is stored. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3033 + + @assert { + + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3034 + + @assert { + + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3035 + + @assert { + + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3036 + + @assert { + + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3037 + + @assert { + + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3038 + + @assert { + + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3039 + + @assert { + + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3040 + + @assert { + + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3041 + + @assert { + + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3042 + + @assert { + + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3043 + + @assert { + + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3044 + + @assert { + + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3045 + + @assert { + + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3046 + + @assert { + + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3047 + + @assert { + + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3048 + + @assert { + + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3049 + + @assert { + + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3050 + + @assert { + + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3051 + + @assert { + + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3052 + + @assert { + + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3053 + + @assert { + + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3054 + + @assert { + + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3055 + + @assert { + + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3056 + + @assert { + + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3057 + + @assert { + + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3058 + + @assert { + + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3059 + + @assert { + + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3060 + + @assert { + + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3061 + + @assert { + + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3062 + + @assert { + + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3063 + + @assert { + + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3064 + + @assert { + + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3065 + + @assert { + + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3066 + + @assert { + + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3067 + + @assert { + + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3068 + + @assert { + + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3069 + + @assert { + + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3070 + + @assert { + + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3071 + + @assert { + + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3072 + + @assert { + + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3073 + + @assert { + + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3074 + + @assert { + + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3075 + + @assert { + + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3076 + + @assert { + + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3077 + + @assert { + + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3078 + + @assert { + + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3079 + + @assert { + + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3080 + + @assert { + + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3081 + + @assert { + + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3082 + + @assert { + + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3083 + + @assert { + + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3084 + + @assert { + + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3085 + + @assert { + + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3086 + + @assert { + + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3087 + + @assert { + + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3088 + + @assert { + + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3089 + + @assert { + + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3090 + + @assert { + + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3091 + + @assert { + + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3092 + + @assert { + + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3093 + + @assert { + + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3094 + + @assert { + + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3095 + + @assert { + + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3096 + + @assert { + + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3097 + + @assert { + + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3098 + + @assert { + + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3099 + + @assert { + + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3100 + + @assert { + + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3101 + + @assert { + + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3102 + + @assert { + + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3103 + + @assert { + + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3104 + + @assert { + + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3105 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3106 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3107 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3108 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3109 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3110 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3111 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3112 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3113 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3114 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3115 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3116 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3117 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3118 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3119 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3120 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3121 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3122 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3123 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3124 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3125 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3126 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3127 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3128 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3129 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3130 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3131 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3132 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3133 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3134 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3135 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3136 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3137 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3138 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3139 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3140 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3141 + + @assert { + + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3142 + + @assert { + + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3143 + + @assert { + + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3144 + + @assert { + + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3145 + + @assert { + + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3146 + + @assert { + + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3147 + + @assert { + + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3148 + + @assert { + + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3149 + + @assert { + + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3150 + + @assert { + + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3151 + + @assert { + + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3152 + + @assert { + + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3153 + + @assert { + + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3154 + + @assert { + + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3155 + + @assert { + + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3156 + + @assert { + + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3157 + + @assert { + + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3158 + + @assert { + + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3159 + + @assert { + + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3160 + + @assert { + + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3161 + + @assert { + + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3162 + + @assert { + + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3163 + + @assert { + + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3164 + + @assert { + + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3165 + + @assert { + + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3166 + + @assert { + + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3167 + + @assert { + + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3168 + + @assert { + + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3169 + + @assert { + + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3170 + + @assert { + + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3171 + + @assert { + + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3172 + + @assert { + + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3173 + + @assert { + + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3174 + + @assert { + + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3175 + + @assert { + + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3176 + + @assert { + + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3177 + + @assert { + + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3178 + + @assert { + + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3179 + + @assert { + + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3180 + + @assert { + + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3181 + + @assert { + + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3182 + + @assert { + + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3183 + + @assert { + + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3184 + + @assert { + + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3185 + + @assert { + + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3186 + + @assert { + + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3187 + + @assert { + + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3188 + + @assert { + + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3189 + + @assert { + + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3190 + + @assert { + + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3191 + + @assert { + + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3192 + + @assert { + + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3193 + + @assert { + + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3194 + + @assert { + + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3195 + + @assert { + + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3196 + + @assert { + + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3197 + + @assert { + + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3198 + + @assert { + + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3199 + + @assert { + + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3200 + + @assert { + + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3201 + + @assert { + + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3202 + + @assert { + + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3203 + + @assert { + + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3204 + + @assert { + + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3205 + + @assert { + + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3206 + + @assert { + + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3207 + + @assert { + + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3208 + + @assert { + + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3209 + + @assert { + + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3210 + + @assert { + + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3211 + + @assert { + + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3212 + + @assert { + + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3213 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3214 + + @assert { + + Rm != 11x1 + size == 0 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3215 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3216 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3217 + + @assert { + + Rm != 11x1 + size == 0 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3218 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3219 + + @assert { + + Rm != 11x1 + size == 0 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3220 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3221 + + @assert { + + Rm != 11x1 + size == 0 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.8 list maccess + + } + + @syntax { + + @subid 3222 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3223 + + @assert { + + Rm != 11x1 + size == 1 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3224 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3225 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3226 + + @assert { + + Rm != 11x1 + size == 1 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3227 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3228 + + @assert { + + Rm != 11x1 + size == 1 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3229 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3230 + + @assert { + + Rm != 11x1 + size == 1 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.16 list maccess + + } + + @syntax { + + @subid 3231 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3232 + + @assert { + + Rm != 11x1 + size == 10 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3233 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3234 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3235 + + @assert { + + Rm != 11x1 + size == 10 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3236 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3237 + + @assert { + + Rm != 11x1 + size == 10 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3238 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3239 + + @assert { + + Rm != 11x1 + size == 10 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.32 list maccess + + } + + @syntax { + + @subid 3240 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3241 + + @assert { + + Rm != 11x1 + size == 11 + type == 111 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + list = VectorTableDim1(dwvec_D) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3242 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3243 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3244 + + @assert { + + Rm != 11x1 + size == 11 + type == 1010 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3245 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3246 + + @assert { + + Rm != 11x1 + size == 11 + type == 110 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3247 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + + @syntax { + + @subid 3248 + + @assert { + + Rm != 11x1 + size == 11 + type == 10 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst1.64 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88406_vst2.d b/plugins/arm/v7/opdefs/A88406_vst2.d new file mode 100644 index 0000000..391d750 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88406_vst2.d @@ -0,0 +1,5169 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VST2 (multiple 2-element structures) + +@id 369 + +@desc { + + This instruction stores multiple 2-element structures from two or four registers to memory, with interleaving. For more information, see Element and structure load/store instructions on page A4-181. Every element of each register is saved. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3249 + + @assert { + + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3250 + + @assert { + + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3251 + + @assert { + + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3252 + + @assert { + + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3253 + + @assert { + + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3254 + + @assert { + + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3255 + + @assert { + + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3256 + + @assert { + + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3257 + + @assert { + + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3258 + + @assert { + + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3259 + + @assert { + + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3260 + + @assert { + + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3261 + + @assert { + + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3262 + + @assert { + + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3263 + + @assert { + + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3264 + + @assert { + + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3265 + + @assert { + + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3266 + + @assert { + + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3267 + + @assert { + + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3268 + + @assert { + + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3269 + + @assert { + + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3270 + + @assert { + + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3271 + + @assert { + + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3272 + + @assert { + + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3273 + + @assert { + + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3274 + + @assert { + + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3275 + + @assert { + + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3276 + + @assert { + + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3277 + + @assert { + + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3278 + + @assert { + + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3279 + + @assert { + + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3280 + + @assert { + + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3281 + + @assert { + + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3282 + + @assert { + + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3283 + + @assert { + + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3284 + + @assert { + + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3285 + + @assert { + + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3286 + + @assert { + + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3287 + + @assert { + + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3288 + + @assert { + + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3289 + + @assert { + + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3290 + + @assert { + + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3291 + + @assert { + + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3292 + + @assert { + + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3293 + + @assert { + + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3294 + + @assert { + + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3295 + + @assert { + + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3296 + + @assert { + + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3297 + + @assert { + + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3298 + + @assert { + + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3299 + + @assert { + + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3300 + + @assert { + + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3301 + + @assert { + + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3302 + + @assert { + + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3303 + + @assert { + + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3304 + + @assert { + + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3305 + + @assert { + + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3306 + + @assert { + + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3307 + + @assert { + + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3308 + + @assert { + + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3309 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3310 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3311 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3312 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3313 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3314 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3315 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3316 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3317 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3318 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3319 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3320 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3321 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3322 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3323 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3324 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3325 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3326 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3327 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3328 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3329 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3330 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3331 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3332 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3333 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3334 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3335 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3336 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3337 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3338 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3339 + + @assert { + + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3340 + + @assert { + + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3341 + + @assert { + + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3342 + + @assert { + + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3343 + + @assert { + + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3344 + + @assert { + + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3345 + + @assert { + + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3346 + + @assert { + + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3347 + + @assert { + + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3348 + + @assert { + + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3349 + + @assert { + + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3350 + + @assert { + + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3351 + + @assert { + + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3352 + + @assert { + + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3353 + + @assert { + + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3354 + + @assert { + + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3355 + + @assert { + + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3356 + + @assert { + + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3357 + + @assert { + + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3358 + + @assert { + + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3359 + + @assert { + + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3360 + + @assert { + + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3361 + + @assert { + + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3362 + + @assert { + + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3363 + + @assert { + + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3364 + + @assert { + + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3365 + + @assert { + + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3366 + + @assert { + + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3367 + + @assert { + + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3368 + + @assert { + + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3369 + + @assert { + + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3370 + + @assert { + + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3371 + + @assert { + + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3372 + + @assert { + + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3373 + + @assert { + + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3374 + + @assert { + + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3375 + + @assert { + + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3376 + + @assert { + + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3377 + + @assert { + + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3378 + + @assert { + + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3379 + + @assert { + + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3380 + + @assert { + + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3381 + + @assert { + + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3382 + + @assert { + + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3383 + + @assert { + + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3384 + + @assert { + + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3385 + + @assert { + + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3386 + + @assert { + + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3387 + + @assert { + + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3388 + + @assert { + + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3389 + + @assert { + + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3390 + + @assert { + + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3391 + + @assert { + + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3392 + + @assert { + + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3393 + + @assert { + + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3394 + + @assert { + + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3395 + + @assert { + + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3396 + + @assert { + + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3397 + + @assert { + + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3398 + + @assert { + + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3399 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3400 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3401 + + @assert { + + Rm != 11x1 + size == 0 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3402 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3403 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3404 + + @assert { + + Rm != 11x1 + size == 0 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3405 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3406 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3407 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3408 + + @assert { + + Rm != 11x1 + size == 0 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.8 list maccess + + } + + @syntax { + + @subid 3409 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3410 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3411 + + @assert { + + Rm != 11x1 + size == 1 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3412 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3413 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3414 + + @assert { + + Rm != 11x1 + size == 1 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3415 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3416 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3417 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3418 + + @assert { + + Rm != 11x1 + size == 1 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.16 list maccess + + } + + @syntax { + + @subid 3419 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3420 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3421 + + @assert { + + Rm != 11x1 + size == 10 + type == 1000 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + list = VectorTableDim2(dwvec_D, dwvec_D_1) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3422 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3423 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3424 + + @assert { + + Rm != 11x1 + size == 10 + type == 1001 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim2(dwvec_D, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3425 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3426 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3427 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + + @syntax { + + @subid 3428 + + @assert { + + Rm != 11x1 + size == 10 + type == 11 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst2.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88408_vst3.d b/plugins/arm/v7/opdefs/A88408_vst3.d new file mode 100644 index 0000000..07da2ac --- /dev/null +++ b/plugins/arm/v7/opdefs/A88408_vst3.d @@ -0,0 +1,2109 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VST3 (multiple 3-element structures) + +@id 370 + +@desc { + + This instruction stores multiple 3-element structures to memory from three registers, with interleaving. For more information, see Element and structure load/store instructions on page A4-181. Every element of each register is saved. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3429 + + @assert { + + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3430 + + @assert { + + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3431 + + @assert { + + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3432 + + @assert { + + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3433 + + @assert { + + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3434 + + @assert { + + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3435 + + @assert { + + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3436 + + @assert { + + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3437 + + @assert { + + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3438 + + @assert { + + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3439 + + @assert { + + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3440 + + @assert { + + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3441 + + @assert { + + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3442 + + @assert { + + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3443 + + @assert { + + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3444 + + @assert { + + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3445 + + @assert { + + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3446 + + @assert { + + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3447 + + @assert { + + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3448 + + @assert { + + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3449 + + @assert { + + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3450 + + @assert { + + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3451 + + @assert { + + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3452 + + @assert { + + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3453 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3454 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3455 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3456 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3457 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3458 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3459 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3460 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3461 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3462 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3463 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3464 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3465 + + @assert { + + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3466 + + @assert { + + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3467 + + @assert { + + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3468 + + @assert { + + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3469 + + @assert { + + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3470 + + @assert { + + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3471 + + @assert { + + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3472 + + @assert { + + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3473 + + @assert { + + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3474 + + @assert { + + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3475 + + @assert { + + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3476 + + @assert { + + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3477 + + @assert { + + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3478 + + @assert { + + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3479 + + @assert { + + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3480 + + @assert { + + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3481 + + @assert { + + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3482 + + @assert { + + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3483 + + @assert { + + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3484 + + @assert { + + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3485 + + @assert { + + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3486 + + @assert { + + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3487 + + @assert { + + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3488 + + @assert { + + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3489 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3490 + + @assert { + + Rm != 11x1 + size == 0 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3491 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3492 + + @assert { + + Rm != 11x1 + size == 0 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.8 list maccess + + } + + @syntax { + + @subid 3493 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3494 + + @assert { + + Rm != 11x1 + size == 1 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3495 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3496 + + @assert { + + Rm != 11x1 + size == 1 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.16 list maccess + + } + + @syntax { + + @subid 3497 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3498 + + @assert { + + Rm != 11x1 + size == 10 + type == 100 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + list = VectorTableDim3(dwvec_D, dwvec_D_1, dwvec_D_2) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3499 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + + @syntax { + + @subid 3500 + + @assert { + + Rm != 11x1 + size == 10 + type == 101 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + list = VectorTableDim3(dwvec_D, dwvec_D_2, dwvec_D_4) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst3.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88410_vst4.d b/plugins/arm/v7/opdefs/A88410_vst4.d new file mode 100644 index 0000000..778d311 --- /dev/null +++ b/plugins/arm/v7/opdefs/A88410_vst4.d @@ -0,0 +1,4317 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VST4 (multiple 4-element structures) + +@id 371 + +@desc { + + This instruction stores multiple 4-element structures to memory from four registers, with interleaving. For more information, see Element and structure load/store instructions on page A4-181. Every element of each register is saved. For details of the addressing mode see Advanced SIMD addressing mode on page A7-277. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3501 + + @assert { + + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3502 + + @assert { + + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3503 + + @assert { + + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3504 + + @assert { + + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3505 + + @assert { + + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3506 + + @assert { + + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3507 + + @assert { + + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3508 + + @assert { + + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3509 + + @assert { + + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3510 + + @assert { + + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3511 + + @assert { + + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3512 + + @assert { + + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3513 + + @assert { + + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3514 + + @assert { + + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3515 + + @assert { + + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3516 + + @assert { + + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3517 + + @assert { + + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3518 + + @assert { + + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3519 + + @assert { + + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3520 + + @assert { + + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3521 + + @assert { + + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3522 + + @assert { + + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3523 + + @assert { + + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3524 + + @assert { + + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3525 + + @assert { + + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3526 + + @assert { + + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3527 + + @assert { + + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3528 + + @assert { + + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3529 + + @assert { + + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3530 + + @assert { + + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3531 + + @assert { + + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3532 + + @assert { + + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3533 + + @assert { + + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3534 + + @assert { + + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3535 + + @assert { + + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3536 + + @assert { + + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3537 + + @assert { + + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3538 + + @assert { + + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3539 + + @assert { + + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3540 + + @assert { + + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3541 + + @assert { + + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3542 + + @assert { + + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3543 + + @assert { + + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3544 + + @assert { + + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3545 + + @assert { + + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3546 + + @assert { + + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3547 + + @assert { + + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3548 + + @assert { + + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3549 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3550 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3551 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3552 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3553 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3554 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3555 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3556 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3557 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3558 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3559 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3560 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3561 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3562 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3563 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3564 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3565 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3566 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3567 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3568 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3569 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3570 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3571 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3572 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 0 0 1 0 D(1) 0 0 Rn(4) Vd(4) type(4) size(2) align(2) Rm(4) + + @syntax { + + @subid 3573 + + @assert { + + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3574 + + @assert { + + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3575 + + @assert { + + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3576 + + @assert { + + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3577 + + @assert { + + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3578 + + @assert { + + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3579 + + @assert { + + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3580 + + @assert { + + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3581 + + @assert { + + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3582 + + @assert { + + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3583 + + @assert { + + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3584 + + @assert { + + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3585 + + @assert { + + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3586 + + @assert { + + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3587 + + @assert { + + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3588 + + @assert { + + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3589 + + @assert { + + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3590 + + @assert { + + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3591 + + @assert { + + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3592 + + @assert { + + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3593 + + @assert { + + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3594 + + @assert { + + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3595 + + @assert { + + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3596 + + @assert { + + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessOffset(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3597 + + @assert { + + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3598 + + @assert { + + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3599 + + @assert { + + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3600 + + @assert { + + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3601 + + @assert { + + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3602 + + @assert { + + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3603 + + @assert { + + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3604 + + @assert { + + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3605 + + @assert { + + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3606 + + @assert { + + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3607 + + @assert { + + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3608 + + @assert { + + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3609 + + @assert { + + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3610 + + @assert { + + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3611 + + @assert { + + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3612 + + @assert { + + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3613 + + @assert { + + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3614 + + @assert { + + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3615 + + @assert { + + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3616 + + @assert { + + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3617 + + @assert { + + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3618 + + @assert { + + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3619 + + @assert { + + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3620 + + @assert { + + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + maccess = MemAccessPreIndexed(aligned, NULL) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3621 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3622 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3623 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3624 + + @assert { + + Rm != 11x1 + size == 0 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3625 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3626 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3627 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3628 + + @assert { + + Rm != 11x1 + size == 0 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.8 list maccess + + } + + @syntax { + + @subid 3629 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3630 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3631 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3632 + + @assert { + + Rm != 11x1 + size == 1 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3633 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3634 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3635 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3636 + + @assert { + + Rm != 11x1 + size == 1 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.16 list maccess + + } + + @syntax { + + @subid 3637 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3638 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3639 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3640 + + @assert { + + Rm != 11x1 + size == 10 + type == 0 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_1 = NextDoubleWordVector(dwvec_D, 1) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_3 = NextDoubleWordVector(dwvec_D, 3) + list = VectorTableDim4(dwvec_D, dwvec_D_1, dwvec_D_2, dwvec_D_3) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3641 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 64) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3642 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 128) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3643 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 256) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + + @syntax { + + @subid 3644 + + @assert { + + Rm != 11x1 + size == 10 + type == 1 + align == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_D_2 = NextDoubleWordVector(dwvec_D, 2) + dwvec_D_4 = NextDoubleWordVector(dwvec_D, 4) + dwvec_D_6 = NextDoubleWordVector(dwvec_D, 6) + list = VectorTableDim4(dwvec_D, dwvec_D_2, dwvec_D_4, dwvec_D_6) + reg_N = Register(Rn) + aligned = AlignedRegister(reg_N, 0) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(aligned, reg_M) + + } + + @asm vst4.32 list maccess + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88412_vstm.d b/plugins/arm/v7/opdefs/A88412_vstm.d new file mode 100644 index 0000000..1a1c32a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88412_vstm.d @@ -0,0 +1,241 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VSTM + +@id 372 + +@desc { + + Vector Store Multiple stores multiple extension registers to consecutive memory locations using an address from an ARM core register. Depending on settings in the CPACR, NSACR, HCPTR, and FPEXC registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of general controls of CP10 and CP11 functionality on page B1-1230 and Summary of access controls for Advanced SIMD functionality on page B1-1232 summarize these controls. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 3645 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vstmia wb_reg list + + } + + @syntax { + + @subid 3646 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vstmdb wb_reg list + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 3647 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vstmia wb_reg list + + } + + @syntax { + + @subid 3648 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vstmdb wb_reg list + + } + +} + +@encoding (A1) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) Vd(4) 1 0 1 1 imm8(8) + + @syntax { + + @subid 3649 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vstmia wb_reg list + + } + + @syntax { + + @subid 3650 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_DOUBLE_WORD, imm8, Vd:D, 2) + + } + + @asm vstmdb wb_reg list + + } + +} + +@encoding (A2) { + + @word 1 1 1 0 1 1 0 P(1) U(1) D(1) W(1) 0 Rn(4) Vd(4) 1 0 1 0 imm8(8) + + @syntax { + + @subid 3651 + + @assert { + + P == 0 + U == 1 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vstmia wb_reg list + + } + + @syntax { + + @subid 3652 + + @assert { + + P == 1 + U == 0 + + } + + @conv { + + reg_N = Register(Rn) + wb_reg = WrittenBackReg(reg_N, W) + list = DynamicVectorTable(SRM_SINGLE_WORD, imm8, Vd:D, 1) + + } + + @asm vstmdb wb_reg list + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88413_vstr.d b/plugins/arm/v7/opdefs/A88413_vstr.d index cca3bc5..1357904 100644 --- a/plugins/arm/v7/opdefs/A88413_vstr.d +++ b/plugins/arm/v7/opdefs/A88413_vstr.d @@ -23,7 +23,7 @@ @title VSTR -@id 357 +@id 373 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2141 + @subid 3653 @conv { @@ -60,7 +60,7 @@ @syntax { - @subid 2142 + @subid 3654 @conv { @@ -83,7 +83,7 @@ @syntax { - @subid 2143 + @subid 3655 @conv { @@ -106,7 +106,7 @@ @syntax { - @subid 2144 + @subid 3656 @conv { diff --git a/plugins/arm/v7/opdefs/A88414_vsub.d b/plugins/arm/v7/opdefs/A88414_vsub.d index 3081e98..ce40943 100644 --- a/plugins/arm/v7/opdefs/A88414_vsub.d +++ b/plugins/arm/v7/opdefs/A88414_vsub.d @@ -23,7 +23,7 @@ @title VSUB (integer) -@id 358 +@id 374 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2145 + @subid 3657 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2146 + @subid 3658 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 2147 + @subid 3659 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 2148 + @subid 3660 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 2149 + @subid 3661 @assert { @@ -153,7 +153,7 @@ @syntax { - @subid 2150 + @subid 3662 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 2151 + @subid 3663 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 2152 + @subid 3664 @assert { diff --git a/plugins/arm/v7/opdefs/A88415_vsub.d b/plugins/arm/v7/opdefs/A88415_vsub.d index 21dc6e6..625379e 100644 --- a/plugins/arm/v7/opdefs/A88415_vsub.d +++ b/plugins/arm/v7/opdefs/A88415_vsub.d @@ -23,7 +23,7 @@ @title VSUB (floating-point) -@id 359 +@id 375 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2153 + @subid 3665 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 2154 + @subid 3666 @assert { @@ -89,7 +89,7 @@ @syntax { - @subid 2155 + @subid 3667 @assert { @@ -111,7 +111,7 @@ @syntax { - @subid 2156 + @subid 3668 @assert { @@ -139,7 +139,7 @@ @syntax { - @subid 2157 + @subid 3669 @assert { @@ -162,7 +162,7 @@ @syntax { - @subid 2158 + @subid 3670 @assert { @@ -191,7 +191,7 @@ @syntax { - @subid 2159 + @subid 3671 @assert { @@ -213,7 +213,7 @@ @syntax { - @subid 2160 + @subid 3672 @assert { diff --git a/plugins/arm/v7/opdefs/A88416_vsubhn.d b/plugins/arm/v7/opdefs/A88416_vsubhn.d index 19efab5..89b87e7 100644 --- a/plugins/arm/v7/opdefs/A88416_vsubhn.d +++ b/plugins/arm/v7/opdefs/A88416_vsubhn.d @@ -23,7 +23,7 @@ @title VSUBHN -@id 360 +@id 376 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2161 + @subid 3673 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2162 + @subid 3674 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 2163 + @subid 3675 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2164 + @subid 3676 @assert { @@ -131,7 +131,7 @@ @syntax { - @subid 2165 + @subid 3677 @assert { @@ -153,7 +153,7 @@ @syntax { - @subid 2166 + @subid 3678 @assert { diff --git a/plugins/arm/v7/opdefs/A88417_vsub.d b/plugins/arm/v7/opdefs/A88417_vsub.d index e547bae..cea486e 100644 --- a/plugins/arm/v7/opdefs/A88417_vsub.d +++ b/plugins/arm/v7/opdefs/A88417_vsub.d @@ -23,7 +23,7 @@ @title VSUBL, VSUBW -@id 361 +@id 377 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2167 + @subid 3679 @assert { @@ -61,7 +61,7 @@ @syntax { - @subid 2168 + @subid 3680 @assert { @@ -85,7 +85,7 @@ @syntax { - @subid 2169 + @subid 3681 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2170 + @subid 3682 @assert { @@ -133,7 +133,7 @@ @syntax { - @subid 2171 + @subid 3683 @assert { @@ -157,7 +157,7 @@ @syntax { - @subid 2172 + @subid 3684 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 2173 + @subid 3685 @assert { @@ -205,7 +205,7 @@ @syntax { - @subid 2174 + @subid 3686 @assert { @@ -229,7 +229,7 @@ @syntax { - @subid 2175 + @subid 3687 @assert { @@ -253,7 +253,7 @@ @syntax { - @subid 2176 + @subid 3688 @assert { @@ -277,7 +277,7 @@ @syntax { - @subid 2177 + @subid 3689 @assert { @@ -301,7 +301,7 @@ @syntax { - @subid 2178 + @subid 3690 @assert { @@ -331,7 +331,7 @@ @syntax { - @subid 2179 + @subid 3691 @assert { @@ -355,7 +355,7 @@ @syntax { - @subid 2180 + @subid 3692 @assert { @@ -379,7 +379,7 @@ @syntax { - @subid 2181 + @subid 3693 @assert { @@ -403,7 +403,7 @@ @syntax { - @subid 2182 + @subid 3694 @assert { @@ -427,7 +427,7 @@ @syntax { - @subid 2183 + @subid 3695 @assert { @@ -451,7 +451,7 @@ @syntax { - @subid 2184 + @subid 3696 @assert { @@ -475,7 +475,7 @@ @syntax { - @subid 2185 + @subid 3697 @assert { @@ -499,7 +499,7 @@ @syntax { - @subid 2186 + @subid 3698 @assert { @@ -523,7 +523,7 @@ @syntax { - @subid 2187 + @subid 3699 @assert { @@ -547,7 +547,7 @@ @syntax { - @subid 2188 + @subid 3700 @assert { @@ -571,7 +571,7 @@ @syntax { - @subid 2189 + @subid 3701 @assert { @@ -595,7 +595,7 @@ @syntax { - @subid 2190 + @subid 3702 @assert { diff --git a/plugins/arm/v7/opdefs/A88418_vswp.d b/plugins/arm/v7/opdefs/A88418_vswp.d index 68bb331..555afcc 100644 --- a/plugins/arm/v7/opdefs/A88418_vswp.d +++ b/plugins/arm/v7/opdefs/A88418_vswp.d @@ -23,7 +23,7 @@ @title VSWP -@id 362 +@id 378 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2191 + @subid 3703 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2192 + @subid 3704 @assert { @@ -87,7 +87,7 @@ @syntax { - @subid 2193 + @subid 3705 @assert { @@ -109,7 +109,7 @@ @syntax { - @subid 2194 + @subid 3706 @assert { diff --git a/plugins/arm/v7/opdefs/A88419_vtb.d b/plugins/arm/v7/opdefs/A88419_vtb.d new file mode 100644 index 0000000..775834a --- /dev/null +++ b/plugins/arm/v7/opdefs/A88419_vtb.d @@ -0,0 +1,453 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see . + */ + + +@title VTBL, VTBX + +@id 379 + +@desc { + + Vector Table Lookup uses byte indexes in a control vector to look up byte values in a table and generate a new vector. Indexes out of range return 0. Vector Table Extension works in the same way, except that indexes out of range leave the destination element unchanged. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 Vn(4) Vd(4) 1 0 len(2) N(1) op(1) M(1) 0 Vm(4) + + @syntax { + + @subid 3707 + + @assert { + + op == 0 + len == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + list = VectorTableDim1(dwvec_N) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3708 + + @assert { + + op == 0 + len == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + list = VectorTableDim2(dwvec_N, dwvec_N_1) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3709 + + @assert { + + op == 0 + len == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + list = VectorTableDim3(dwvec_N, dwvec_N_1, dwvec_N_2) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3710 + + @assert { + + op == 0 + len == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + dwvec_N_3 = NextDoubleWordVector(dwvec_N, 3) + list = VectorTableDim4(dwvec_N, dwvec_N_1, dwvec_N_2, dwvec_N_3) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3711 + + @assert { + + op == 1 + len == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + list = VectorTableDim1(dwvec_N) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3712 + + @assert { + + op == 1 + len == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + list = VectorTableDim2(dwvec_N, dwvec_N_1) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3713 + + @assert { + + op == 1 + len == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + list = VectorTableDim3(dwvec_N, dwvec_N_1, dwvec_N_2) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3714 + + @assert { + + op == 1 + len == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + dwvec_N_3 = NextDoubleWordVector(dwvec_N, 3) + list = VectorTableDim4(dwvec_N, dwvec_N_1, dwvec_N_2, dwvec_N_3) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + +} + +@encoding (A1) { + + @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 Vn(4) Vd(4) 1 0 len(2) N(1) op(1) M(1) 0 Vm(4) + + @syntax { + + @subid 3715 + + @assert { + + op == 0 + len == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + list = VectorTableDim1(dwvec_N) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3716 + + @assert { + + op == 0 + len == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + list = VectorTableDim2(dwvec_N, dwvec_N_1) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3717 + + @assert { + + op == 0 + len == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + list = VectorTableDim3(dwvec_N, dwvec_N_1, dwvec_N_2) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3718 + + @assert { + + op == 0 + len == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + dwvec_N_3 = NextDoubleWordVector(dwvec_N, 3) + list = VectorTableDim4(dwvec_N, dwvec_N_1, dwvec_N_2, dwvec_N_3) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbl.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3719 + + @assert { + + op == 1 + len == 0 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + list = VectorTableDim1(dwvec_N) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3720 + + @assert { + + op == 1 + len == 1 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + list = VectorTableDim2(dwvec_N, dwvec_N_1) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3721 + + @assert { + + op == 1 + len == 10 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + list = VectorTableDim3(dwvec_N, dwvec_N_1, dwvec_N_2) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + + @syntax { + + @subid 3722 + + @assert { + + op == 1 + len == 11 + + } + + @conv { + + dwvec_D = DoubleWordVector(D:Vd) + dwvec_N = DoubleWordVector(N:Vn) + dwvec_N_1 = NextDoubleWordVector(dwvec_N, 1) + dwvec_N_2 = NextDoubleWordVector(dwvec_N, 2) + dwvec_N_3 = NextDoubleWordVector(dwvec_N, 3) + list = VectorTableDim4(dwvec_N, dwvec_N_1, dwvec_N_2, dwvec_N_3) + dwvec_M = DoubleWordVector(M:Vm) + + } + + @asm vtbx.8 dwvec_D list dwvec_M + + } + +} + diff --git a/plugins/arm/v7/opdefs/A88420_vtrn.d b/plugins/arm/v7/opdefs/A88420_vtrn.d index baf38c9..74d2d21 100644 --- a/plugins/arm/v7/opdefs/A88420_vtrn.d +++ b/plugins/arm/v7/opdefs/A88420_vtrn.d @@ -23,7 +23,7 @@ @title VTRN -@id 363 +@id 380 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2195 + @subid 3723 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2196 + @subid 3724 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 2197 + @subid 3725 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 2198 + @subid 3726 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 2199 + @subid 3727 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 2200 + @subid 3728 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 2201 + @subid 3729 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 2202 + @subid 3730 @assert { @@ -219,7 +219,7 @@ @syntax { - @subid 2203 + @subid 3731 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 2204 + @subid 3732 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 2205 + @subid 3733 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 2206 + @subid 3734 @assert { diff --git a/plugins/arm/v7/opdefs/A88421_vtst.d b/plugins/arm/v7/opdefs/A88421_vtst.d index 24471de..b2914c5 100644 --- a/plugins/arm/v7/opdefs/A88421_vtst.d +++ b/plugins/arm/v7/opdefs/A88421_vtst.d @@ -23,7 +23,7 @@ @title VTST -@id 364 +@id 381 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2207 + @subid 3735 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 2208 + @subid 3736 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 2209 + @subid 3737 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 2210 + @subid 3738 @assert { @@ -129,7 +129,7 @@ @syntax { - @subid 2211 + @subid 3739 @assert { @@ -152,7 +152,7 @@ @syntax { - @subid 2212 + @subid 3740 @assert { @@ -181,7 +181,7 @@ @syntax { - @subid 2213 + @subid 3741 @assert { @@ -204,7 +204,7 @@ @syntax { - @subid 2214 + @subid 3742 @assert { @@ -227,7 +227,7 @@ @syntax { - @subid 2215 + @subid 3743 @assert { @@ -250,7 +250,7 @@ @syntax { - @subid 2216 + @subid 3744 @assert { @@ -273,7 +273,7 @@ @syntax { - @subid 2217 + @subid 3745 @assert { @@ -296,7 +296,7 @@ @syntax { - @subid 2218 + @subid 3746 @assert { diff --git a/plugins/arm/v7/opdefs/A88422_vuzp.d b/plugins/arm/v7/opdefs/A88422_vuzp.d index 70d1426..ef60869 100644 --- a/plugins/arm/v7/opdefs/A88422_vuzp.d +++ b/plugins/arm/v7/opdefs/A88422_vuzp.d @@ -23,7 +23,7 @@ @title VUZP -@id 365 +@id 382 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2219 + @subid 3747 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2220 + @subid 3748 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 2221 + @subid 3749 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 2222 + @subid 3750 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 2223 + @subid 3751 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 2224 + @subid 3752 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 2225 + @subid 3753 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 2226 + @subid 3754 @assert { @@ -219,7 +219,7 @@ @syntax { - @subid 2227 + @subid 3755 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 2228 + @subid 3756 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 2229 + @subid 3757 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 2230 + @subid 3758 @assert { diff --git a/plugins/arm/v7/opdefs/A88423_vzip.d b/plugins/arm/v7/opdefs/A88423_vzip.d index bae666e..b679623 100644 --- a/plugins/arm/v7/opdefs/A88423_vzip.d +++ b/plugins/arm/v7/opdefs/A88423_vzip.d @@ -23,7 +23,7 @@ @title VZIP -@id 366 +@id 383 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2231 + @subid 3759 @assert { @@ -59,7 +59,7 @@ @syntax { - @subid 2232 + @subid 3760 @assert { @@ -81,7 +81,7 @@ @syntax { - @subid 2233 + @subid 3761 @assert { @@ -103,7 +103,7 @@ @syntax { - @subid 2234 + @subid 3762 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 2235 + @subid 3763 @assert { @@ -147,7 +147,7 @@ @syntax { - @subid 2236 + @subid 3764 @assert { @@ -175,7 +175,7 @@ @syntax { - @subid 2237 + @subid 3765 @assert { @@ -197,7 +197,7 @@ @syntax { - @subid 2238 + @subid 3766 @assert { @@ -219,7 +219,7 @@ @syntax { - @subid 2239 + @subid 3767 @assert { @@ -241,7 +241,7 @@ @syntax { - @subid 2240 + @subid 3768 @assert { @@ -263,7 +263,7 @@ @syntax { - @subid 2241 + @subid 3769 @assert { @@ -285,7 +285,7 @@ @syntax { - @subid 2242 + @subid 3770 @assert { diff --git a/plugins/arm/v7/opdefs/A88424_wfe.d b/plugins/arm/v7/opdefs/A88424_wfe.d index 8f951a9..738eab1 100644 --- a/plugins/arm/v7/opdefs/A88424_wfe.d +++ b/plugins/arm/v7/opdefs/A88424_wfe.d @@ -23,7 +23,7 @@ @title WFE -@id 367 +@id 384 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2243 + @subid 3771 @asm wfe @@ -51,7 +51,7 @@ @syntax { - @subid 2244 + @subid 3772 @asm wfe.w @@ -65,7 +65,7 @@ @syntax { - @subid 2245 + @subid 3773 @asm wfe diff --git a/plugins/arm/v7/opdefs/A88425_wfi.d b/plugins/arm/v7/opdefs/A88425_wfi.d index 95e1fad..aea5cf2 100644 --- a/plugins/arm/v7/opdefs/A88425_wfi.d +++ b/plugins/arm/v7/opdefs/A88425_wfi.d @@ -23,7 +23,7 @@ @title WFI -@id 368 +@id 385 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2246 + @subid 3774 @asm wfi @@ -51,7 +51,7 @@ @syntax { - @subid 2247 + @subid 3775 @asm wfi.w @@ -65,7 +65,7 @@ @syntax { - @subid 2248 + @subid 3776 @asm wfi diff --git a/plugins/arm/v7/opdefs/A88426_yield.d b/plugins/arm/v7/opdefs/A88426_yield.d index eef1730..0cad28c 100644 --- a/plugins/arm/v7/opdefs/A88426_yield.d +++ b/plugins/arm/v7/opdefs/A88426_yield.d @@ -23,7 +23,7 @@ @title YIELD -@id 369 +@id 386 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2249 + @subid 3777 @asm yield @@ -51,7 +51,7 @@ @syntax { - @subid 2250 + @subid 3778 @asm yield.w @@ -65,7 +65,7 @@ @syntax { - @subid 2251 + @subid 3779 @asm yield diff --git a/plugins/arm/v7/opdefs/A931_enterx.d b/plugins/arm/v7/opdefs/A931_enterx.d index f6ca54a..50c0bec 100644 --- a/plugins/arm/v7/opdefs/A931_enterx.d +++ b/plugins/arm/v7/opdefs/A931_enterx.d @@ -23,7 +23,7 @@ @title ENTERX, LEAVEX -@id 370 +@id 387 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2252 + @subid 3780 @assert { @@ -51,7 +51,7 @@ @syntax { - @subid 2253 + @subid 3781 @assert { diff --git a/plugins/arm/v7/opdefs/B9310_msr.d b/plugins/arm/v7/opdefs/B9310_msr.d index 1dd8ad6..37aab64 100644 --- a/plugins/arm/v7/opdefs/B9310_msr.d +++ b/plugins/arm/v7/opdefs/B9310_msr.d @@ -23,7 +23,7 @@ @title MSR (Banked register) -@id 380 +@id 397 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2278 + @subid 3806 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2279 + @subid 3807 @conv { diff --git a/plugins/arm/v7/opdefs/B9311_msr.d b/plugins/arm/v7/opdefs/B9311_msr.d index a9d4f25..44689ab 100644 --- a/plugins/arm/v7/opdefs/B9311_msr.d +++ b/plugins/arm/v7/opdefs/B9311_msr.d @@ -23,7 +23,7 @@ @title MSR (immediate) -@id 381 +@id 398 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2280 + @subid 3808 @conv { diff --git a/plugins/arm/v7/opdefs/B9312_msr.d b/plugins/arm/v7/opdefs/B9312_msr.d index df86cd3..f9d6eb5 100644 --- a/plugins/arm/v7/opdefs/B9312_msr.d +++ b/plugins/arm/v7/opdefs/B9312_msr.d @@ -23,7 +23,7 @@ @title MSR (register) -@id 382 +@id 399 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2281 + @subid 3809 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2282 + @subid 3810 @conv { diff --git a/plugins/arm/v7/opdefs/B9313_rfe.d b/plugins/arm/v7/opdefs/B9313_rfe.d index ffaa207..c31317f 100644 --- a/plugins/arm/v7/opdefs/B9313_rfe.d +++ b/plugins/arm/v7/opdefs/B9313_rfe.d @@ -23,7 +23,7 @@ @title RFE -@id 383 +@id 400 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2283 + @subid 3811 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2284 + @subid 3812 @conv { @@ -79,7 +79,7 @@ @syntax { - @subid 2285 + @subid 3813 @assert { @@ -101,7 +101,7 @@ @syntax { - @subid 2286 + @subid 3814 @assert { @@ -123,7 +123,7 @@ @syntax { - @subid 2287 + @subid 3815 @assert { @@ -145,7 +145,7 @@ @syntax { - @subid 2288 + @subid 3816 @assert { diff --git a/plugins/arm/v7/opdefs/B9314_smc.d b/plugins/arm/v7/opdefs/B9314_smc.d index c20b6ca..09c62e1 100644 --- a/plugins/arm/v7/opdefs/B9314_smc.d +++ b/plugins/arm/v7/opdefs/B9314_smc.d @@ -23,7 +23,7 @@ @title SMC (previously SMI) -@id 384 +@id 401 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2289 + @subid 3817 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 2290 + @subid 3818 @conv { diff --git a/plugins/arm/v7/opdefs/B9315_srs.d b/plugins/arm/v7/opdefs/B9315_srs.d index 2e95dbc..999d7aa 100644 --- a/plugins/arm/v7/opdefs/B9315_srs.d +++ b/plugins/arm/v7/opdefs/B9315_srs.d @@ -23,7 +23,7 @@ @title SRS (Thumb) -@id 385 +@id 402 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2291 + @subid 3819 @conv { @@ -59,7 +59,7 @@ @syntax { - @subid 2292 + @subid 3820 @conv { diff --git a/plugins/arm/v7/opdefs/B9316_srs.d b/plugins/arm/v7/opdefs/B9316_srs.d index 7793314..ff8f4f9 100644 --- a/plugins/arm/v7/opdefs/B9316_srs.d +++ b/plugins/arm/v7/opdefs/B9316_srs.d @@ -23,7 +23,7 @@ @title SRS (ARM) -@id 386 +@id 403 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2293 + @subid 3821 @assert { @@ -60,7 +60,7 @@ @syntax { - @subid 2294 + @subid 3822 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 2295 + @subid 3823 @assert { @@ -106,7 +106,7 @@ @syntax { - @subid 2296 + @subid 3824 @assert { diff --git a/plugins/arm/v7/opdefs/B9317_stm.d b/plugins/arm/v7/opdefs/B9317_stm.d index 88b2f02..e497db1 100644 --- a/plugins/arm/v7/opdefs/B9317_stm.d +++ b/plugins/arm/v7/opdefs/B9317_stm.d @@ -23,7 +23,7 @@ @title STM (User registers) -@id 387 +@id 404 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2297 + @subid 3825 @assert { @@ -65,7 +65,7 @@ @syntax { - @subid 2298 + @subid 3826 @assert { @@ -93,7 +93,7 @@ @syntax { - @subid 2299 + @subid 3827 @assert { @@ -121,7 +121,7 @@ @syntax { - @subid 2300 + @subid 3828 @assert { diff --git a/plugins/arm/v7/opdefs/B9319_subs.d b/plugins/arm/v7/opdefs/B9319_subs.d index 21377a9..ece99a9 100644 --- a/plugins/arm/v7/opdefs/B9319_subs.d +++ b/plugins/arm/v7/opdefs/B9319_subs.d @@ -23,7 +23,7 @@ @title SUBS PC, LR (Thumb) -@id 389 +@id 406 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2301 + @subid 3829 @conv { diff --git a/plugins/arm/v7/opdefs/B931_cps.d b/plugins/arm/v7/opdefs/B931_cps.d index 60c19f8..598060c 100644 --- a/plugins/arm/v7/opdefs/B931_cps.d +++ b/plugins/arm/v7/opdefs/B931_cps.d @@ -23,7 +23,7 @@ @title CPS (Thumb) -@id 371 +@id 388 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2254 + @subid 3782 @assert { @@ -57,7 +57,7 @@ @syntax { - @subid 2255 + @subid 3783 @assert { @@ -83,7 +83,7 @@ @syntax { - @subid 2256 + @subid 3784 @assert { @@ -104,7 +104,7 @@ @syntax { - @subid 2257 + @subid 3785 @assert { @@ -125,7 +125,7 @@ @syntax { - @subid 2258 + @subid 3786 @assert { diff --git a/plugins/arm/v7/opdefs/B9320_subs.d b/plugins/arm/v7/opdefs/B9320_subs.d index c381676..b9acfe4 100644 --- a/plugins/arm/v7/opdefs/B9320_subs.d +++ b/plugins/arm/v7/opdefs/B9320_subs.d @@ -23,7 +23,7 @@ @title SUBS PC, LR and related instructions (ARM) -@id 390 +@id 407 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2302 + @subid 3830 @conv { @@ -65,7 +65,7 @@ @syntax { - @subid 2303 + @subid 3831 @assert { diff --git a/plugins/arm/v7/opdefs/B9321_vmrs.d b/plugins/arm/v7/opdefs/B9321_vmrs.d index f862120..e0c2e8d 100644 --- a/plugins/arm/v7/opdefs/B9321_vmrs.d +++ b/plugins/arm/v7/opdefs/B9321_vmrs.d @@ -23,7 +23,7 @@ @title VMRS -@id 391 +@id 408 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2304 + @subid 3832 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2305 + @subid 3833 @conv { diff --git a/plugins/arm/v7/opdefs/B9322_vmsr.d b/plugins/arm/v7/opdefs/B9322_vmsr.d index aac4f4b..71d98bd 100644 --- a/plugins/arm/v7/opdefs/B9322_vmsr.d +++ b/plugins/arm/v7/opdefs/B9322_vmsr.d @@ -23,7 +23,7 @@ @title VMSR -@id 392 +@id 409 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2306 + @subid 3834 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2307 + @subid 3835 @conv { diff --git a/plugins/arm/v7/opdefs/B932_cps.d b/plugins/arm/v7/opdefs/B932_cps.d index cad958f..4660dfa 100644 --- a/plugins/arm/v7/opdefs/B932_cps.d +++ b/plugins/arm/v7/opdefs/B932_cps.d @@ -23,7 +23,7 @@ @title CPS (ARM) -@id 372 +@id 389 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2259 + @subid 3787 @assert { @@ -58,7 +58,7 @@ @syntax { - @subid 2260 + @subid 3788 @assert { @@ -79,7 +79,7 @@ @syntax { - @subid 2261 + @subid 3789 @assert { diff --git a/plugins/arm/v7/opdefs/B933_eret.d b/plugins/arm/v7/opdefs/B933_eret.d index fae8572..34b2748 100644 --- a/plugins/arm/v7/opdefs/B933_eret.d +++ b/plugins/arm/v7/opdefs/B933_eret.d @@ -23,7 +23,7 @@ @title ERET -@id 373 +@id 390 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2262 + @subid 3790 @asm eret @@ -51,7 +51,7 @@ @syntax { - @subid 2263 + @subid 3791 @asm eret diff --git a/plugins/arm/v7/opdefs/B934_hvc.d b/plugins/arm/v7/opdefs/B934_hvc.d index 2a47638..beb43ee 100644 --- a/plugins/arm/v7/opdefs/B934_hvc.d +++ b/plugins/arm/v7/opdefs/B934_hvc.d @@ -23,7 +23,7 @@ @title HVC -@id 374 +@id 391 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2264 + @subid 3792 @conv { @@ -57,7 +57,7 @@ @syntax { - @subid 2265 + @subid 3793 @conv { diff --git a/plugins/arm/v7/opdefs/B935_ldm.d b/plugins/arm/v7/opdefs/B935_ldm.d index f6501d0..e68949b 100644 --- a/plugins/arm/v7/opdefs/B935_ldm.d +++ b/plugins/arm/v7/opdefs/B935_ldm.d @@ -23,7 +23,7 @@ @title LDM (exception return) -@id 375 +@id 392 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2266 + @subid 3794 @assert { @@ -66,7 +66,7 @@ @syntax { - @subid 2267 + @subid 3795 @assert { @@ -95,7 +95,7 @@ @syntax { - @subid 2268 + @subid 3796 @assert { @@ -124,7 +124,7 @@ @syntax { - @subid 2269 + @subid 3797 @assert { diff --git a/plugins/arm/v7/opdefs/B936_ldm.d b/plugins/arm/v7/opdefs/B936_ldm.d index b0e15ca..46ec6dc 100644 --- a/plugins/arm/v7/opdefs/B936_ldm.d +++ b/plugins/arm/v7/opdefs/B936_ldm.d @@ -23,7 +23,7 @@ @title LDM (User registers) -@id 376 +@id 393 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2270 + @subid 3798 @assert { @@ -65,7 +65,7 @@ @syntax { - @subid 2271 + @subid 3799 @assert { @@ -93,7 +93,7 @@ @syntax { - @subid 2272 + @subid 3800 @assert { @@ -121,7 +121,7 @@ @syntax { - @subid 2273 + @subid 3801 @assert { diff --git a/plugins/arm/v7/opdefs/B938_mrs.d b/plugins/arm/v7/opdefs/B938_mrs.d index 44fc840..cd7394d 100644 --- a/plugins/arm/v7/opdefs/B938_mrs.d +++ b/plugins/arm/v7/opdefs/B938_mrs.d @@ -23,7 +23,7 @@ @title MRS -@id 378 +@id 395 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2274 + @subid 3802 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2275 + @subid 3803 @conv { diff --git a/plugins/arm/v7/opdefs/B939_mrs.d b/plugins/arm/v7/opdefs/B939_mrs.d index 7087264..9fc8d84 100644 --- a/plugins/arm/v7/opdefs/B939_mrs.d +++ b/plugins/arm/v7/opdefs/B939_mrs.d @@ -23,7 +23,7 @@ @title MRS (Banked register) -@id 379 +@id 396 @desc { @@ -37,7 +37,7 @@ @syntax { - @subid 2276 + @subid 3804 @conv { @@ -58,7 +58,7 @@ @syntax { - @subid 2277 + @subid 3805 @conv { diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am index 877f27d..59b69a4 100644 --- a/plugins/arm/v7/opdefs/Makefile.am +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -349,6 +349,15 @@ ARMV7_DEFS = \ A88317_vfm.d \ A88318_vfnm.d \ A88319_vh.d \ + A88320_vld1.d \ + A88322_vld1.d \ + A88323_vld2.d \ + A88325_vld2.d \ + A88326_vld3.d \ + A88328_vld3.d \ + A88329_vld4.d \ + A88331_vld4.d \ + A88332_vldm.d \ A88334_vmax.d \ A88335_vmax.d \ A88336_vmla.d \ @@ -375,6 +384,8 @@ ARMV7_DEFS = \ A88364_vpaddl.d \ A88365_vpmax.d \ A88366_vpmax.d \ + A88367_vpop.d \ + A88368_vpush.d \ A88369_vqabs.d \ A88370_vqadd.d \ A88374_vqmov.d \ @@ -393,12 +404,18 @@ ARMV7_DEFS = \ A88394_vrsubhn.d \ A88396_vshl.d \ A88401_vsqrt.d \ + A88404_vst1.d \ + A88406_vst2.d \ + A88408_vst3.d \ + A88410_vst4.d \ + A88412_vstm.d \ A88413_vstr.d \ A88414_vsub.d \ A88415_vsub.d \ A88416_vsubhn.d \ A88417_vsub.d \ A88418_vswp.d \ + A88419_vtb.d \ A88420_vtrn.d \ A88421_vtst.d \ A88422_vuzp.d \ diff --git a/plugins/arm/v7/operands/maccess.c b/plugins/arm/v7/operands/maccess.c index 5359527..f5307f7 100644 --- a/plugins/arm/v7/operands/maccess.c +++ b/plugins/arm/v7/operands/maccess.c @@ -268,7 +268,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G if (!operand->post_indexed) g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); - if (operand->write_back) + if (operand->post_indexed && operand->write_back) g_buffer_line_append_text(line, BLC_ASSEMBLY, "!", 1, RTT_PUNCT, NULL); } diff --git a/plugins/arm/v7/operands/register.c b/plugins/arm/v7/operands/register.c index 4a5f852..80a3769 100644 --- a/plugins/arm/v7/operands/register.c +++ b/plugins/arm/v7/operands/register.c @@ -33,6 +33,9 @@ struct _GArmV7RegisterOperand { GRegisterOperand parent; /* Instance parente */ + unsigned int alignment; /* Eventuel alignement */ + bool has_alignment; /* Validité du champ */ + bool write_back; /* Mise à jour du registre ? */ }; @@ -223,6 +226,28 @@ GArchOperand *g_armv7_register_operand_new(GArmV7Register *reg) /****************************************************************************** * * * Paramètres : operand = opérande représentant un registre. * +* align = alignement imposé au registre. * +* * +* Description : Définit un alignement à appliquer à l'opérande de registre. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void g_armv7_register_operand_define_alignement(GArmV7RegisterOperand *operand, unsigned int align) +{ + operand->alignment = align; + + operand->has_alignment = true; + +} + + +/****************************************************************************** +* * +* Paramètres : operand = opérande représentant un registre. * * wback = indique si le registre est mis à jour après coup. * * * * Description : Détermine si le registre est mis à jour après l'opération. * @@ -288,7 +313,7 @@ static bool g_armv7_register_operand_unserialize(GArmV7RegisterOperand *operand, { bool result; /* Bilan à retourner */ GArchOperandClass *parent; /* Classe parente à consulter */ - uint8_t wback; /* Mise à jour après coup ? */ + uint8_t boolean; /* Valeur booléenne */ parent = G_ARCH_OPERAND_CLASS(g_armv7_register_operand_parent_class); @@ -296,10 +321,22 @@ static bool g_armv7_register_operand_unserialize(GArmV7RegisterOperand *operand, if (result) { - result = extract_packed_buffer(pbuf, &wback, sizeof(uint8_t), false); + result = extract_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); if (result) - operand->write_back = (wback == 1 ? true : false); + operand->has_alignment = (boolean == 1 ? true : false); + + } + + if (result && operand->has_alignment) + result = extract_packed_buffer(pbuf, &operand->alignment, sizeof(unsigned int), true); + + if (result) + { + result = extract_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + + if (result) + operand->write_back = (boolean == 1 ? true : false); } @@ -326,7 +363,7 @@ static bool g_armv7_register_operand_serialize(const GArmV7RegisterOperand *oper { bool result; /* Bilan à retourner */ GArchOperandClass *parent; /* Classe parente à consulter */ - uint8_t wback; /* Mise à jour après coup ? */ + uint8_t boolean; /* Valeur booléenne */ parent = G_ARCH_OPERAND_CLASS(g_armv7_register_operand_parent_class); @@ -334,8 +371,17 @@ static bool g_armv7_register_operand_serialize(const GArmV7RegisterOperand *oper if (result) { - wback = (operand->write_back ? 1 : 0); - result = extend_packed_buffer(pbuf, &wback, sizeof(uint8_t), false); + boolean = (operand->has_alignment ? 1 : 0); + result = extend_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); + } + + if (result && operand->has_alignment) + result = extend_packed_buffer(pbuf, &operand->alignment, sizeof(unsigned int), true); + + if (result) + { + boolean = (operand->write_back ? 1 : 0); + result = extend_packed_buffer(pbuf, &boolean, sizeof(uint8_t), false); } return result; diff --git a/plugins/arm/v7/operands/register.h b/plugins/arm/v7/operands/register.h index 4a9c0c3..4806b89 100644 --- a/plugins/arm/v7/operands/register.h +++ b/plugins/arm/v7/operands/register.h @@ -57,6 +57,9 @@ GType g_armv7_register_operand_get_type(void); /* Crée un opérande visant un registre ARMv7. */ GArchOperand *g_armv7_register_operand_new(GArmV7Register *); +/* Définit un alignement à appliquer à l'opérande de registre. */ +void g_armv7_register_operand_define_alignement(GArmV7RegisterOperand *, unsigned int); + /* Détermine si le registre est mis à jour après l'opération. */ void g_armv7_register_operand_write_back(GArmV7RegisterOperand *, bool); diff --git a/tools/d2c/args/manager.c b/tools/d2c/args/manager.c index eca3bab..8706694 100644 --- a/tools/d2c/args/manager.c +++ b/tools/d2c/args/manager.c @@ -1030,6 +1030,9 @@ bool define_arg_expr(const arg_expr_t *expr, int fd, const coding_bits *bits, co result = compute_arg_expr_size(expr, bits, list, &max_size); + if (result && expr->comp_count > 1) + dprintf(fd, "("); + for (i = 0; i < expr->comp_count && result; i++) { cname = expr->comp_items[i]; @@ -1082,6 +1085,9 @@ bool define_arg_expr(const arg_expr_t *expr, int fd, const coding_bits *bits, co } + if (result && expr->comp_count > 1) + dprintf(fd, ")"); + break; case CET_UNARY: diff --git a/tools/d2c/assert/manager.c b/tools/d2c/assert/manager.c index 2ccf468..4fe1860 100644 --- a/tools/d2c/assert/manager.c +++ b/tools/d2c/assert/manager.c @@ -63,6 +63,13 @@ struct _disass_assert }; +/* Définit le masque correspondant à une valeur booléenne. */ +static char *get_disass_assert_mask(const char *); + +/* Définit la valeur correspondant à une valeur booléenne. */ +static char *get_disass_assert_value(const char *); + + /****************************************************************************** * * @@ -301,6 +308,8 @@ bool define_disass_assert(const disass_assert *dassert, int fd, const coding_bit size_t j; /* Boucle de parcours #2 */ def_cond *cond; /* Condition à marquer */ raw_bitfield *rf; /* Champ de bits à marquer */ + char *mask; /* Eventuel masque à appliquer */ + char *expected; /* Valeur attendue */ for (i = 0; i < dassert->count; i++) { @@ -337,7 +346,22 @@ bool define_disass_assert(const disass_assert *dassert, int fd, const coding_bit } - write_raw_bitfield(rf, fd); + mask = get_disass_assert_mask(cond->value); + + if (mask == NULL) + write_raw_bitfield(rf, fd); + + else + { + dprintf(fd, "("); + + write_raw_bitfield(rf, fd); + + dprintf(fd, " & %s)", mask); + + free(mask); + + } switch (cond->op) { @@ -351,7 +375,11 @@ bool define_disass_assert(const disass_assert *dassert, int fd, const coding_bit } - dprintf(fd, "b%s", cond->value); + expected = get_disass_assert_value(cond->value); + + dprintf(fd, "%s", expected); + + free(expected); } @@ -363,3 +391,94 @@ bool define_disass_assert(const disass_assert *dassert, int fd, const coding_bit return true; } + + +/****************************************************************************** +* * +* Paramètres : value = valeur booléenne à écrire. * +* * +* Description : Définit le masque correspondant à une valeur booléenne. * +* * +* Retour : Masque à appliquer (et libérer) ou NULL si aucun. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static char *get_disass_assert_mask(const char *value) +{ + char *result; /* Masque à renvoyer */ + char *iter; /* Boucle de parcours */ + + if (strchr(value, 'x') == NULL) + result = NULL; + + else + { + result = strdup(value); + + for (iter = result; *iter != '\0'; iter++) + switch (*iter) + { + case '0': + case '1': + *iter = '1'; + break; + + case 'x': + *iter = '0'; + break; + + default: + assert(false); + break; + + } + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : value = valeur booléenne à écrire. * +* * +* Description : Définit la valeur correspondant à une valeur booléenne. * +* * +* Retour : Valeur à comparer et libérer. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static char *get_disass_assert_value(const char *value) +{ + char *result; /* Masque à renvoyer */ + char *iter; /* Boucle de parcours */ + + result = strdup(value); + + if (strchr(value, 'x') != NULL) + for (iter = result; *iter != '\0'; iter++) + switch (*iter) + { + case '0': + case '1': + break; + + case 'x': + *iter = '0'; + break; + + default: + assert(false); + break; + + } + + return result; + +} diff --git a/tools/d2c/assert/tokens.l b/tools/d2c/assert/tokens.l index 192bcc7..e455a76 100644 --- a/tools/d2c/assert/tokens.l +++ b/tools/d2c/assert/tokens.l @@ -29,7 +29,7 @@ [A-Za-z_][A-Za-z0-9_]* { yylvalp->string = strdup(yytext); return FIELD; } -[01]+ { yylvalp->string = strdup(yytext); return VALUE; } +[01x]+ { yylvalp->string = strdup(yytext); return VALUE; } . { char *msg; -- cgit v0.11.2-87-g4458