/* Chrysalide - Outil d'analyse de fichiers binaires
 * ##FILE## - traduction d'instructions ARMv7
 *
 * Copyright (C) 2017 Cyrille Bagard
 *
 *  This file is part of Chrysalide.
 *
 *  Chrysalide is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  Chrysalide is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
 */


@title VMAX, VMIN (integer)

@id 312

@desc {

	Vector Maximum compares corresponding elements in two vectors, and copies the larger of each pair into the corresponding element in the destination vector. Vector Minimum compares corresponding elements in two vectors, and copies the smaller of each pair into the corresponding element in the destination vector. The operand vector elements can be any one of: • 8-bit, 16-bit, or 32-bit signed integers • 8-bit, 16-bit, or 32-bit unsigned integers. The result vector elements are the same size as the operand vector elements. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.

}

@encoding (T1) {

	@word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 1 1 0 N(1) Q(1) M(1) op(1) Vm(4)

	@syntax {

		@subid 1373

		@assert {

			Q == 1
			op == 0
			size == 0
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.s8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1374

		@assert {

			Q == 1
			op == 0
			size == 1
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.s16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1375

		@assert {

			Q == 1
			op == 0
			size == 10
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.s32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1376

		@assert {

			Q == 1
			op == 0
			size == 0
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.u8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1377

		@assert {

			Q == 1
			op == 0
			size == 1
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.u16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1378

		@assert {

			Q == 1
			op == 0
			size == 10
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.u32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1379

		@assert {

			Q == 1
			op == 1
			size == 0
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.s8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1380

		@assert {

			Q == 1
			op == 1
			size == 1
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.s16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1381

		@assert {

			Q == 1
			op == 1
			size == 10
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.s32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1382

		@assert {

			Q == 1
			op == 1
			size == 0
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.u8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1383

		@assert {

			Q == 1
			op == 1
			size == 1
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.u16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1384

		@assert {

			Q == 1
			op == 1
			size == 10
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.u32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1385

		@assert {

			Q == 0
			op == 0
			size == 0
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.s8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1386

		@assert {

			Q == 0
			op == 0
			size == 1
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.s16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1387

		@assert {

			Q == 0
			op == 0
			size == 10
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.s32 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1388

		@assert {

			Q == 0
			op == 0
			size == 0
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.u8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1389

		@assert {

			Q == 0
			op == 0
			size == 1
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.u16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1390

		@assert {

			Q == 0
			op == 0
			size == 10
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.u32 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1391

		@assert {

			Q == 0
			op == 1
			size == 0
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.s8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1392

		@assert {

			Q == 0
			op == 1
			size == 1
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.s16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1393

		@assert {

			Q == 0
			op == 1
			size == 10
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.s32 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1394

		@assert {

			Q == 0
			op == 1
			size == 0
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.u8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1395

		@assert {

			Q == 0
			op == 1
			size == 1
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.u16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1396

		@assert {

			Q == 0
			op == 1
			size == 10
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.u32 ?dwvec_D dwvec_N dwvec_M

	}

}

@encoding (A1) {

	@word 1 1 1 U(1) 1 1 1 1 0 D(1) size(2) Vn(4) Vd(4) 0 1 1 0 N(1) Q(1) M(1) op(1) Vm(4)

	@syntax {

		@subid 1397

		@assert {

			Q == 1
			op == 0
			size == 0
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.s8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1398

		@assert {

			Q == 1
			op == 0
			size == 1
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.s16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1399

		@assert {

			Q == 1
			op == 0
			size == 10
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.s32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1400

		@assert {

			Q == 1
			op == 0
			size == 0
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.u8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1401

		@assert {

			Q == 1
			op == 0
			size == 1
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.u16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1402

		@assert {

			Q == 1
			op == 0
			size == 10
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmax.u32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1403

		@assert {

			Q == 1
			op == 1
			size == 0
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.s8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1404

		@assert {

			Q == 1
			op == 1
			size == 1
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.s16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1405

		@assert {

			Q == 1
			op == 1
			size == 10
			U == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.s32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1406

		@assert {

			Q == 1
			op == 1
			size == 0
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.u8 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1407

		@assert {

			Q == 1
			op == 1
			size == 1
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.u16 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1408

		@assert {

			Q == 1
			op == 1
			size == 10
			U == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			qwvec_N = QuadWordVector(N:Vn)
			qwvec_M = QuadWordVector(M:Vm)

		}

		@asm vmin.u32 ?qwvec_D qwvec_N qwvec_M

	}

	@syntax {

		@subid 1409

		@assert {

			Q == 0
			op == 0
			size == 0
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.s8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1410

		@assert {

			Q == 0
			op == 0
			size == 1
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.s16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1411

		@assert {

			Q == 0
			op == 0
			size == 10
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.s32 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1412

		@assert {

			Q == 0
			op == 0
			size == 0
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.u8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1413

		@assert {

			Q == 0
			op == 0
			size == 1
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.u16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1414

		@assert {

			Q == 0
			op == 0
			size == 10
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmax.u32 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1415

		@assert {

			Q == 0
			op == 1
			size == 0
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.s8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1416

		@assert {

			Q == 0
			op == 1
			size == 1
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.s16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1417

		@assert {

			Q == 0
			op == 1
			size == 10
			U == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.s32 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1418

		@assert {

			Q == 0
			op == 1
			size == 0
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.u8 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1419

		@assert {

			Q == 0
			op == 1
			size == 1
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.u16 ?dwvec_D dwvec_N dwvec_M

	}

	@syntax {

		@subid 1420

		@assert {

			Q == 0
			op == 1
			size == 10
			U == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			dwvec_N = DoubleWordVector(N:Vn)
			dwvec_M = DoubleWordVector(M:Vm)

		}

		@asm vmin.u32 ?dwvec_D dwvec_N dwvec_M

	}

}