/* Chrysalide - Outil d'analyse de fichiers binaires
 * ##FILE## - traduction d'instructions ARMv7
 *
 * Copyright (C) 2017 Cyrille Bagard
 *
 *  This file is part of Chrysalide.
 *
 *  Chrysalide is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 3 of the License, or
 *  (at your option) any later version.
 *
 *  Chrysalide is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
 */


@title VORR (immediate)

@id 331

@desc {

	This instruction takes the contents of the destination vector, performs a bitwise OR with an immediate constant, and returns the result into the destination vector. For the range of constants available, see One register and a modified immediate value on page A7-269. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288.

}

@encoding (T1) {

	@word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 0 1 imm4(4)

	@syntax {

		@subid 1663

		@assert {

			Q == 1
			cmode == 1000

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1664

		@assert {

			Q == 1
			cmode == 1001

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1665

		@assert {

			Q == 1
			cmode == 1010

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1666

		@assert {

			Q == 1
			cmode == 1011

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1667

		@assert {

			Q == 1
			cmode == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1668

		@assert {

			Q == 1
			cmode == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1669

		@assert {

			Q == 1
			cmode == 10

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1670

		@assert {

			Q == 1
			cmode == 11

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1671

		@assert {

			Q == 1
			cmode == 100

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1672

		@assert {

			Q == 1
			cmode == 101

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1673

		@assert {

			Q == 1
			cmode == 110

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1674

		@assert {

			Q == 1
			cmode == 111

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1675

		@assert {

			Q == 1
			cmode == 1100

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1676

		@assert {

			Q == 1
			cmode == 1101

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1677

		@assert {

			Q == 0
			cmode == 1000

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1678

		@assert {

			Q == 0
			cmode == 1001

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1679

		@assert {

			Q == 0
			cmode == 1010

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1680

		@assert {

			Q == 0
			cmode == 1011

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1681

		@assert {

			Q == 0
			cmode == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1682

		@assert {

			Q == 0
			cmode == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1683

		@assert {

			Q == 0
			cmode == 10

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1684

		@assert {

			Q == 0
			cmode == 11

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1685

		@assert {

			Q == 0
			cmode == 100

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1686

		@assert {

			Q == 0
			cmode == 101

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1687

		@assert {

			Q == 0
			cmode == 110

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1688

		@assert {

			Q == 0
			cmode == 111

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1689

		@assert {

			Q == 0
			cmode == 1100

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1690

		@assert {

			Q == 0
			cmode == 1101

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

}

@encoding (A1) {

	@word 1 1 1 i(1) 1 1 1 1 1 D(1) 0 0 0 imm3(3) Vd(4) cmode(4) 0 Q(1) 0 1 imm4(4)

	@syntax {

		@subid 1691

		@assert {

			Q == 1
			cmode == 1000

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1692

		@assert {

			Q == 1
			cmode == 1001

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1693

		@assert {

			Q == 1
			cmode == 1010

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1694

		@assert {

			Q == 1
			cmode == 1011

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 qwvec_D imm64

	}

	@syntax {

		@subid 1695

		@assert {

			Q == 1
			cmode == 0

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1696

		@assert {

			Q == 1
			cmode == 1

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1697

		@assert {

			Q == 1
			cmode == 10

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1698

		@assert {

			Q == 1
			cmode == 11

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1699

		@assert {

			Q == 1
			cmode == 100

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1700

		@assert {

			Q == 1
			cmode == 101

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1701

		@assert {

			Q == 1
			cmode == 110

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1702

		@assert {

			Q == 1
			cmode == 111

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1703

		@assert {

			Q == 1
			cmode == 1100

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1704

		@assert {

			Q == 1
			cmode == 1101

		}

		@conv {

			qwvec_D = QuadWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 qwvec_D imm64

	}

	@syntax {

		@subid 1705

		@assert {

			Q == 0
			cmode == 1000

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1706

		@assert {

			Q == 0
			cmode == 1001

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1707

		@assert {

			Q == 0
			cmode == 1010

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1708

		@assert {

			Q == 0
			cmode == 1011

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i16 dwvec_D imm64

	}

	@syntax {

		@subid 1709

		@assert {

			Q == 0
			cmode == 0

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1710

		@assert {

			Q == 0
			cmode == 1

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1711

		@assert {

			Q == 0
			cmode == 10

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1712

		@assert {

			Q == 0
			cmode == 11

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1713

		@assert {

			Q == 0
			cmode == 100

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1714

		@assert {

			Q == 0
			cmode == 101

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1715

		@assert {

			Q == 0
			cmode == 110

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1716

		@assert {

			Q == 0
			cmode == 111

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1717

		@assert {

			Q == 0
			cmode == 1100

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

	@syntax {

		@subid 1718

		@assert {

			Q == 0
			cmode == 1101

		}

		@conv {

			dwvec_D = DoubleWordVector(D:Vd)
			imm64 = AdvSIMDExpandImm('0', cmode, i:imm3:imm4)

		}

		@asm vorr.i32 dwvec_D imm64

	}

}