/* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * * Chrysalide is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 3 of the License, or * (at your option) any later version. * * Chrysalide is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with Chrysalide. If not, see . */ @title VQNEG @id 353 @desc { Vector Saturating Negate negates each element in a vector, and places the results in the destination vector. If any of the results overflow, they are saturated. The cumulative saturation bit, FPSCR.QC, is set if saturation occurs. For details see Pseudocode details of saturation on page A2-44. Depending on settings in the CPACR, NSACR, and HCPTR registers, and the security state and mode in which the instruction is executed, an attempt to execute the instruction might be UNDEFINED, or trapped to Hyp mode. Summary of access controls for Advanced SIMD functionality on page B1-1232 summarizes these controls. ARM deprecates the conditional execution of any Advanced SIMD instruction encoding that is not also available as a VFP instruction encoding, see Conditional execution on page A8-288. } @encoding (T1) { @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 0 0 Vd(4) 0 1 1 1 1 Q(1) M(1) 0 Vm(4) @syntax { @subid 2761 @assert { Q == 1 size == 0 } @conv { qwvec_D = QuadWordVector(D:Vd) qwvec_M = QuadWordVector(M:Vm) } @asm vqneg.s8 qwvec_D qwvec_M } @syntax { @subid 2762 @assert { Q == 1 size == 1 } @conv { qwvec_D = QuadWordVector(D:Vd) qwvec_M = QuadWordVector(M:Vm) } @asm vqneg.s16 qwvec_D qwvec_M } @syntax { @subid 2763 @assert { Q == 1 size == 10 } @conv { qwvec_D = QuadWordVector(D:Vd) qwvec_M = QuadWordVector(M:Vm) } @asm vqneg.s32 qwvec_D qwvec_M } @syntax { @subid 2764 @assert { Q == 0 size == 0 } @conv { dwvec_D = DoubleWordVector(D:Vd) dwvec_M = DoubleWordVector(M:Vm) } @asm vqneg.s8 dwvec_D dwvec_M } @syntax { @subid 2765 @assert { Q == 0 size == 1 } @conv { dwvec_D = DoubleWordVector(D:Vd) dwvec_M = DoubleWordVector(M:Vm) } @asm vqneg.s16 dwvec_D dwvec_M } @syntax { @subid 2766 @assert { Q == 0 size == 10 } @conv { dwvec_D = DoubleWordVector(D:Vd) dwvec_M = DoubleWordVector(M:Vm) } @asm vqneg.s32 dwvec_D dwvec_M } } @encoding (A1) { @word 1 1 1 1 1 1 1 1 1 D(1) 1 1 size(2) 0 0 Vd(4) 0 1 1 1 1 Q(1) M(1) 0 Vm(4) @syntax { @subid 2767 @assert { Q == 1 size == 0 } @conv { qwvec_D = QuadWordVector(D:Vd) qwvec_M = QuadWordVector(M:Vm) } @asm vqneg.s8 qwvec_D qwvec_M } @syntax { @subid 2768 @assert { Q == 1 size == 1 } @conv { qwvec_D = QuadWordVector(D:Vd) qwvec_M = QuadWordVector(M:Vm) } @asm vqneg.s16 qwvec_D qwvec_M } @syntax { @subid 2769 @assert { Q == 1 size == 10 } @conv { qwvec_D = QuadWordVector(D:Vd) qwvec_M = QuadWordVector(M:Vm) } @asm vqneg.s32 qwvec_D qwvec_M } @syntax { @subid 2770 @assert { Q == 0 size == 0 } @conv { dwvec_D = DoubleWordVector(D:Vd) dwvec_M = DoubleWordVector(M:Vm) } @asm vqneg.s8 dwvec_D dwvec_M } @syntax { @subid 2771 @assert { Q == 0 size == 1 } @conv { dwvec_D = DoubleWordVector(D:Vd) dwvec_M = DoubleWordVector(M:Vm) } @asm vqneg.s16 dwvec_D dwvec_M } @syntax { @subid 2772 @assert { Q == 0 size == 10 } @conv { dwvec_D = DoubleWordVector(D:Vd) dwvec_M = DoubleWordVector(M:Vm) } @asm vqneg.s32 dwvec_D dwvec_M } }