/* Chrysalide - Outil d'analyse de fichiers binaires
* ##FILE## - traduction d'instructions ARMv7
*
* Copyright (C) 2015 Cyrille Bagard
*
* This file is part of Chrysalide.
*
* Chrysalide is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Chrysalide is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Foobar. If not, see .
*/
@title BIC (immediate)
@desc Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result.
@encoding (T1) {
@word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8)
@syntax
@conv {
reg_D = Register(Rd)
reg_N = Register(Rn)
setflags = (S == '1')
imm32 = ThumbExpandImm_C(i:imm3:imm8, 0)
}
@rules {
if (setflags); chk_call ExtendKeyword("s")
}
}
@encoding (A1) {
@word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12)
@syntax
@conv {
reg_D = Register(Rd)
reg_N = Register(Rn)
setflags = (S == '1')
imm32 = ARMExpandImm_C(imm12, 0)
}
@rules {
if (setflags); chk_call ExtendKeyword("s")
chk_call StoreCondition(cond)
}
}