diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-30 17:15:13 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-30 17:15:13 (GMT) |
commit | c492a5c94cc20210bce8069db7235cbb7dd691e9 (patch) | |
tree | 1521acfdfdd9bb6760c618fde460a6a63dff6d7b /plugins/arm/v7/helpers.h | |
parent | ce3676d7c298c124253b32beeaebe2437a8ce8de (diff) |
Supported a few extra ARMv7 SIMD instructions.
Diffstat (limited to 'plugins/arm/v7/helpers.h')
-rw-r--r-- | plugins/arm/v7/helpers.h | 77 |
1 files changed, 51 insertions, 26 deletions
diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index 5d4db94..bf4bc5a 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -43,6 +43,7 @@ #include "registers/coproc.h" #include "registers/simd.h" #include "registers/special.h" +#include "../register.h" @@ -286,6 +287,15 @@ }) +#define Multiplication(factor, val) \ + ({ \ + GArchOperand *__result; \ + uint32_t __computed; \ + __computed = factor * val; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __computed); \ + __result; \ + }) + #define NextRegister(idx) \ ({ \ GArchOperand *__result; \ @@ -299,11 +309,13 @@ }) -#define QuadWordVector(idx) \ +#define NexSingleWordVector(prev) \ ({ \ GArchOperand *__result; \ + uint8_t __idx; \ GArchRegister *__reg; \ - __reg = g_armv7_simd_register_new(SRM_QUAD_WORD, idx); \ + __idx = g_arm_register_get_index(G_ARM_REGISTER(prev)); \ + __reg = g_armv7_simd_register_new(SRM_SINGLE_WORD, __idx + 1); \ if (__reg == NULL) \ __result = NULL; \ else \ @@ -312,31 +324,11 @@ }) -#define SignExtend(val, size, top) \ - ({ \ - GArchOperand *__result; \ - MemoryDataSize __mds; \ - uint ## size ## _t __val; \ - __mds = MDS_ ## size ## _BITS_SIGNED; \ - __val = armv7_sign_extend(val, top, size); \ - __result = g_imm_operand_new_from_value(__mds, __val); \ - __result; \ - }) - - -#define SingleRegList(t) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_reglist_operand_new(1 << t); \ - __result; \ - }) - - -#define SingleWordVector(idx) \ +#define QuadWordVector(idx) \ ({ \ GArchOperand *__result; \ GArchRegister *__reg; \ - __reg = g_armv7_simd_register_new(SRM_SINGLE_WORD, idx); \ + __reg = g_armv7_simd_register_new(SRM_QUAD_WORD, idx); \ if (__reg == NULL) \ __result = NULL; \ else \ @@ -422,11 +414,44 @@ }) -#define SpecRegAPSR() \ +#define SignExtend(val, size, top) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## size ## _t __val; \ + __mds = MDS_ ## size ## _BITS_SIGNED; \ + __val = armv7_sign_extend(val, top, size); \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ + }) + + +#define SingleRegList(t) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_reglist_operand_new(1 << t); \ + __result; \ + }) + + +#define SingleWordVector(idx) \ + ({ \ + GArchOperand *__result; \ + GArchRegister *__reg; \ + __reg = g_armv7_simd_register_new(SRM_SINGLE_WORD, idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_armv7_register_operand_new(G_ARMV7_REGISTER(__reg)); \ + __result; \ + }) + + +#define SpecReg(target) \ ({ \ GArchOperand *__result; \ GArchRegister *__reg; \ - __reg = g_armv7_special_register_new(SRT_APSR); \ + __reg = g_armv7_special_register_new(target); \ if (__reg == NULL) \ __result = NULL; \ else \ |