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author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
commit | 5311a943dffcc410739509b9215ca464f6d1e54c (patch) | |
tree | 9c34b5176606aa7bb3dcfb5970a20e3f9b27f1c3 /plugins/arm/v7/opdefs/A8885_ldrsb.d | |
parent | 9f5ed46de568d3db882c939c8ca9d0117bff3369 (diff) |
Included support for ARMv7 system instructions.
Diffstat (limited to 'plugins/arm/v7/opdefs/A8885_ldrsb.d')
-rw-r--r-- | plugins/arm/v7/opdefs/A8885_ldrsb.d | 81 |
1 files changed, 81 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A8885_ldrsb.d b/plugins/arm/v7/opdefs/A8885_ldrsb.d new file mode 100644 index 0000000..6ea8617 --- /dev/null +++ b/plugins/arm/v7/opdefs/A8885_ldrsb.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title LDRSB (literal) + +@id 79 + +@desc { + + Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) + + @syntax { + + @subid 247 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldrsb reg_T imm32 + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) + + @syntax { + + @subid 248 + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) + + } + + @asm ldrsb reg_T imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + |