diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/add_A8811.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/add_A8811.d')
-rw-r--r-- | plugins/arm/v7/opdefs/add_A8811.d | 65 |
1 files changed, 53 insertions, 12 deletions
diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/add_A8811.d index 5b6c0d1..e70c33c 100644 --- a/plugins/arm/v7/opdefs/add_A8811.d +++ b/plugins/arm/v7/opdefs/add_A8811.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title ADD (SP plus register, ARM) -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. +@id 10 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <SP> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_SP reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |