diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
commit | 2c988d3ec52cc4c949a35aca7ef335dac773df92 (patch) | |
tree | fe650d2fc8ddceb606abdf0d2e14e5ef6596be82 /plugins/arm/v7/opdefs/add_A889.d | |
parent | 23abef53590bf3dd6f88ff4dbe81e306abfa4386 (diff) |
Created a plugin for the ARM support.
Diffstat (limited to 'plugins/arm/v7/opdefs/add_A889.d')
-rw-r--r-- | plugins/arm/v7/opdefs/add_A889.d | 123 |
1 files changed, 123 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/add_A889.d b/plugins/arm/v7/opdefs/add_A889.d new file mode 100644 index 0000000..5fab17c --- /dev/null +++ b/plugins/arm/v7/opdefs/add_A889.d @@ -0,0 +1,123 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title ADD (SP plus immediate) + +@desc This instruction adds an immediate value to the SP value, and writes the result to the destination register. + +@encoding (t1) { + + @half 1 0 1 0 1 Rd(3) imm8(8) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + SP = Register(13) + + } + +} + +@encoding (t2) { + + @half 1 0 1 1 0 0 0 0 0 imm7(7) + + @syntax <SP_0> <SP_1> <imm32> + + @conv { + + imm32 = ZeroExtend(imm7:'00', 32) + SP_0 = Register(13) + SP_1 = Register(13) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm(i:imm3:imm8) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T4) { + + @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) + + @syntax "addw" <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + SP = Register(13) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) + + @syntax <reg_D> <SP> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm(imm12) + SP = Register(13) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + |