diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/cmn_A8835.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/cmn_A8835.d')
-rw-r--r-- | plugins/arm/v7/opdefs/cmn_A8835.d | 56 |
1 files changed, 37 insertions, 19 deletions
diff --git a/plugins/arm/v7/opdefs/cmn_A8835.d b/plugins/arm/v7/opdefs/cmn_A8835.d index cd228de..deeef21 100644 --- a/plugins/arm/v7/opdefs/cmn_A8835.d +++ b/plugins/arm/v7/opdefs/cmn_A8835.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMN (register) -@desc Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 34 + +@desc { + + Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm cmn reg_N reg_M } @@ -44,13 +54,17 @@ @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm cmn.w reg_N reg_M ?shift } @@ -60,19 +74,23 @@ @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm cmn reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |