diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/ldr_A8866.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/ldr_A8866.d')
-rw-r--r-- | plugins/arm/v7/opdefs/ldr_A8866.d | 100 |
1 files changed, 86 insertions, 14 deletions
diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d index b161043..6ba19f7 100644 --- a/plugins/arm/v7/opdefs/ldr_A8866.d +++ b/plugins/arm/v7/opdefs/ldr_A8866.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title LDR (register, ARM) -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. +@id 65 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |