diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/lsr_A8897.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/lsr_A8897.d')
-rw-r--r-- | plugins/arm/v7/opdefs/lsr_A8897.d | 115 |
1 files changed, 91 insertions, 24 deletions
diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/lsr_A8897.d index 070a152..fa112ec 100644 --- a/plugins/arm/v7/opdefs/lsr_A8897.d +++ b/plugins/arm/v7/opdefs/lsr_A8897.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title LSR (register) -@desc Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 96 + +@desc { + + Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) - @syntax "lsrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm lsr ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsrs.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |