diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
commit | 5311a943dffcc410739509b9215ca464f6d1e54c (patch) | |
tree | 9c34b5176606aa7bb3dcfb5970a20e3f9b27f1c3 /plugins/arm/v7/opdefs/mvn_A88116.d | |
parent | 9f5ed46de568d3db882c939c8ca9d0117bff3369 (diff) |
Included support for ARMv7 system instructions.
Diffstat (limited to 'plugins/arm/v7/opdefs/mvn_A88116.d')
-rw-r--r-- | plugins/arm/v7/opdefs/mvn_A88116.d | 166 |
1 files changed, 0 insertions, 166 deletions
diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d deleted file mode 100644 index db9e070..0000000 --- a/plugins/arm/v7/opdefs/mvn_A88116.d +++ /dev/null @@ -1,166 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title MVN (register) - -@id 115 - -@desc { - - Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. - -} - -@encoding (t1) { - - @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - - @syntax { - - @subid 346 - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - - } - - @asm mvn reg_D reg_M - - } - -} - -@encoding (T2) { - - @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax { - - @subid 347 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm mvn.w reg_D reg_M ?shift - - } - - @syntax { - - @subid 348 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) - - } - - @asm mvns.w reg_D reg_M ?shift - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 349 - - @assert { - - S == 0 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm mvn reg_D reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 350 - - @assert { - - S == 1 - - } - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - - } - - @asm mvns reg_D reg_M ?shift - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - |