diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-05-28 20:34:24 (GMT) |
commit | 5311a943dffcc410739509b9215ca464f6d1e54c (patch) | |
tree | 9c34b5176606aa7bb3dcfb5970a20e3f9b27f1c3 /plugins/arm/v7/opdefs/strd_A88211.d | |
parent | 9f5ed46de568d3db882c939c8ca9d0117bff3369 (diff) |
Included support for ARMv7 system instructions.
Diffstat (limited to 'plugins/arm/v7/opdefs/strd_A88211.d')
-rw-r--r-- | plugins/arm/v7/opdefs/strd_A88211.d | 132 |
1 files changed, 0 insertions, 132 deletions
diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/strd_A88211.d deleted file mode 100644 index 817d2f1..0000000 --- a/plugins/arm/v7/opdefs/strd_A88211.d +++ /dev/null @@ -1,132 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title STRD (register) - -@id 210 - -@desc { - - Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - - @syntax { - - @subid 643 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessOffset(reg_N, reg_M) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 644 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPreIndexed(reg_N, reg_M) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 645 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_T2 = NextRegister(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - maccess = MemAccessPostIndexed(reg_N, reg_M) - - } - - @asm strd reg_T reg_T2 maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - |