diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
commit | 2c988d3ec52cc4c949a35aca7ef335dac773df92 (patch) | |
tree | fe650d2fc8ddceb606abdf0d2e14e5ef6596be82 /plugins/arm/v7/opdefs/strex_A88212.d | |
parent | 23abef53590bf3dd6f88ff4dbe81e306abfa4386 (diff) |
Created a plugin for the ARM support.
Diffstat (limited to 'plugins/arm/v7/opdefs/strex_A88212.d')
-rw-r--r-- | plugins/arm/v7/opdefs/strex_A88212.d | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/strex_A88212.d new file mode 100644 index 0000000..65a7dfe --- /dev/null +++ b/plugins/arm/v7/opdefs/strex_A88212.d @@ -0,0 +1,68 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREX + +@desc Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + |