diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/sub_A88221.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/sub_A88221.d')
-rw-r--r-- | plugins/arm/v7/opdefs/sub_A88221.d | 91 |
1 files changed, 66 insertions, 25 deletions
diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/sub_A88221.d index 41ce6b3..365943c 100644 --- a/plugins/arm/v7/opdefs/sub_A88221.d +++ b/plugins/arm/v7/opdefs/sub_A88221.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (immediate, Thumb) -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 220 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) - @syntax "subs" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) + @asm sub ?reg_D reg_N imm32 } @@ -45,12 +55,17 @@ @half 0 0 1 1 1 Rdn(3) imm8(8) - @syntax "subs" <reg_DN> <imm32> + @syntax { - @conv { + @conv { - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm sub ?reg_D reg_N imm32 } @@ -60,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_N imm32 } @@ -84,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "subw" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm subw ?reg_D reg_N imm32 } |