diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 15:10:54 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 15:11:15 (GMT) |
commit | 43c54a8c124cb869dab993b833ed59a6f6398ee9 (patch) | |
tree | 9faeae67956bdebb0ff9982f0e9d821c16dbedb7 /plugins/arm/v7/opdefs/sub_A88226.d | |
parent | f9404bf68a067b06986cd85855c43795ec578dbd (diff) |
Included a few more ARMv7 instruction definitions.
Diffstat (limited to 'plugins/arm/v7/opdefs/sub_A88226.d')
-rw-r--r-- | plugins/arm/v7/opdefs/sub_A88226.d | 141 |
1 files changed, 141 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d new file mode 100644 index 0000000..3c6e9fd --- /dev/null +++ b/plugins/arm/v7/opdefs/sub_A88226.d @@ -0,0 +1,141 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title SUB (SP minus register) + +@id 225 + +@desc { + + This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. + +} + +@encoding (T1) { + + @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) + + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sub ?reg_D reg_SP reg_M ?shift + + } + + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm subs ?reg_D reg_SP reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) + + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sub ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm subs ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + |