diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/teq_A88239.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/teq_A88239.d')
-rw-r--r-- | plugins/arm/v7/opdefs/teq_A88239.d | 32 |
1 files changed, 22 insertions, 10 deletions
diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/teq_A88239.d index 986a7f0..76e3062 100644 --- a/plugins/arm/v7/opdefs/teq_A88239.d +++ b/plugins/arm/v7/opdefs/teq_A88239.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title TEQ (register-shifted register) -@desc Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 238 + +@desc { + + Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm teq reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |