diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/ubfx_A88246.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/ubfx_A88246.d')
-rw-r--r-- | plugins/arm/v7/opdefs/ubfx_A88246.d | 50 |
1 files changed, 33 insertions, 17 deletions
diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/ubfx_A88246.d index 1f9488e..31c3f43 100644 --- a/plugins/arm/v7/opdefs/ubfx_A88246.d +++ b/plugins/arm/v7/opdefs/ubfx_A88246.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,31 @@ @title UBFX -@desc Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. +@id 245 + +@desc { + + Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) + } + + @asm ubfx reg_D reg_N lsbit width } @@ -46,20 +57,25 @@ @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - } + } + + @asm ubfx reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |