diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/uqasx_A88260.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/uqasx_A88260.d')
-rw-r--r-- | plugins/arm/v7/opdefs/uqasx_A88260.d | 44 |
1 files changed, 29 insertions, 15 deletions
diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/uqasx_A88260.d index 174b08c..0b2047f 100644 --- a/plugins/arm/v7/opdefs/uqasx_A88260.d +++ b/plugins/arm/v7/opdefs/uqasx_A88260.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQASX -@desc Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 259 + +@desc { + + Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |