diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 11:58:42 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2018-04-02 12:39:30 (GMT) |
commit | 1db4ef323b7a76093356ae76268132f3760e1631 (patch) | |
tree | fec36ee0ec1b6b2010b62ca4177edca0e31e2114 /plugins/arm/v7/opdefs/uxth_A88276.d | |
parent | 1bc80837dde03a32b5ab185067f7bd4c499a9850 (diff) |
Rewritten the whole instruction definition format.
Diffstat (limited to 'plugins/arm/v7/opdefs/uxth_A88276.d')
-rw-r--r-- | plugins/arm/v7/opdefs/uxth_A88276.d | 57 |
1 files changed, 38 insertions, 19 deletions
diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/uxth_A88276.d index 5ae4f4f..b49360f 100644 --- a/plugins/arm/v7/opdefs/uxth_A88276.d +++ b/plugins/arm/v7/opdefs/uxth_A88276.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title UXTH -@desc Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. +@id 275 + +@desc { + + Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} @encoding (t1) { @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm uxth ?reg_D reg_M ?rotation } @@ -44,13 +55,17 @@ @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax ".W" <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxth.w ?reg_D reg_M ?rotation } @@ -60,19 +75,23 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxth ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } |