diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-22 15:43:43 (GMT) |
commit | 7577eadd4e871d467f747c4927a1b1984d6a7606 (patch) | |
tree | e72a2fd5c1619e60402a678b0559079ed267eab0 /src/arch/arm/v7/opdefs/ldrb_A8868.d | |
parent | 33aa90b022e7d711a733ca7eb62c0b285f974317 (diff) |
Extended the compiler to transform all the new ARMv7 encoding definitions.
Diffstat (limited to 'src/arch/arm/v7/opdefs/ldrb_A8868.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/ldrb_A8868.d | 64 |
1 files changed, 18 insertions, 46 deletions
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8868.d b/src/arch/arm/v7/opdefs/ldrb_A8868.d index 579db06..519c309 100644 --- a/src/arch/arm/v7/opdefs/ldrb_A8868.d +++ b/src/arch/arm/v7/opdefs/ldrb_A8868.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2015 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,59 +23,31 @@ @title LDRB (immediate, ARM) -@encoding(A11) { +@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. - @word cond(4) 0 1 0 1 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) +@encoding (A1) { - @syntax <Rgt> <access> + @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) - @conv { + @syntax <reg_T> <mem_access> - Rgt = Register(Rt) - Rgn = Register(Rn) - imm32 = ZeroExtend(imm12, 12, 32); - access = MakeMemoryAccess(Rgn, imm32, U, W) + @conv { - } + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) - @rules { + } - //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate); - //if Rn == '1111' then SEE LDRB (literal); - //if P == '1' && U == '1' && W == '0' then SEE LDRBT; - //if P == '0' && W == '0' then UNDEFINED; - //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) + @rules { - } + chk_call StoreCondition(cond) -} - -@encoding(A12) { - - @word cond(4) 0 1 0 0 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) - - @syntax <Rgt> <base> <offset> - - @conv { - - Rgt = Register(Rt) - Rgn = Register(Rn) - imm32 = ZeroExtend(imm12, 12, 32); - base = MakeMemoryNotIndexed(Rgn, W) - offset = MakeAccessOffset(U, imm32) - - } - - @rules { - - //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate); - //if Rn == '1111' then SEE LDRB (literal); - //if P == '1' && U == '1' && W == '0' then SEE LDRBT; - //if P == '0' && W == '0' then UNDEFINED; - //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE; - if (Rt == '1111'); chk_call SetInsFlag(AIF_RETURN_POINT) - - } + } } + |