diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-27 21:18:54 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-27 21:18:54 (GMT) |
commit | ac2906c17089d3f5fa3b7ef5988a3d24a8c6c542 (patch) | |
tree | 1d4087252a8ba0720407c1bffb89e61dcb0786fd /src/arch/arm/v7/opdefs/strd_A88211.d | |
parent | 1878e3ab82d8711f305e7b8bbc43c5ed21bf140b (diff) |
Handled more ARM instructions from the storing family.
Diffstat (limited to 'src/arch/arm/v7/opdefs/strd_A88211.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/strd_A88211.d | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/src/arch/arm/v7/opdefs/strd_A88211.d b/src/arch/arm/v7/opdefs/strd_A88211.d new file mode 100644 index 0000000..b30d4a5 --- /dev/null +++ b/src/arch/arm/v7/opdefs/strd_A88211.d @@ -0,0 +1,54 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRD (register) + +@desc Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + |