diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
---|---|---|
committer | Cyrille Bagard <nocbos@gmail.com> | 2017-12-02 11:04:35 (GMT) |
commit | 2c988d3ec52cc4c949a35aca7ef335dac773df92 (patch) | |
tree | fe650d2fc8ddceb606abdf0d2e14e5ef6596be82 /src/arch/arm/v7/opdefs/uxtab_A88271.d | |
parent | 23abef53590bf3dd6f88ff4dbe81e306abfa4386 (diff) |
Created a plugin for the ARM support.
Diffstat (limited to 'src/arch/arm/v7/opdefs/uxtab_A88271.d')
-rw-r--r-- | src/arch/arm/v7/opdefs/uxtab_A88271.d | 67 |
1 files changed, 0 insertions, 67 deletions
diff --git a/src/arch/arm/v7/opdefs/uxtab_A88271.d b/src/arch/arm/v7/opdefs/uxtab_A88271.d deleted file mode 100644 index fe27d4b..0000000 --- a/src/arch/arm/v7/opdefs/uxtab_A88271.d +++ /dev/null @@ -1,67 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title UXTAB - -@desc Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. - -@encoding (T1) { - - @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - - @syntax <reg_D> <reg_N> <reg_M> <?rotation> - - @conv { - - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') - - } - - @rules { - - chk_call StoreCondition(cond) - - } - -} - |