Fixed and extended the support for ARM v7 instructions.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@542 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

6 files changed, 265 insertions, 2 deletions

diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am
index 6678f0e..6207906 100644
--- a/src/arch/arm/v7/opdefs/Makefile.am
+++ b/src/arch/arm/v7/opdefs/Makefile.am
@@ -54,8 +54,10 @@ ARMV7_DEFS = 							\
 	ldr_A8864.d							\
 	ldr_A8865.d							\
 	ldrb_A8867.d						\
+	ldrb_A8868.d						\
 	ldrb_A8870.d						\
 	lsl_A8894.d							\
+	lsr_A8896.d							\
 	mla_A88100.d						\
 	mls_A88101.d						\
 	mov_A88102.d						\
@@ -82,6 +84,7 @@ ARMV7_DEFS = 							\
 	str_A88203.d						\
 	str_A88204.d						\
 	strb_A88206.d						\
+	strb_A88207.d						\
 	strb_A88208.d						\
 	sub_A88221.d						\
 	sub_A88222.d						\
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8868.d b/src/arch/arm/v7/opdefs/ldrb_A8868.d
new file mode 100644
index 0000000..fdf3049
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/ldrb_A8868.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDRB (immediate, ARM)
+
+@encoding(A11) {
+
+    @word cond(4) 0 1 0 1 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        access = MakeMemoryAccess(Rgn, imm32, U, W)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
+
+@encoding(A12) {
+
+    @word cond(4) 0 1 0 0 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <base> <offset>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        base = MakeMemoryNotIndexed(Rgn, W)
+        offset = MakeAccessOffset(U, imm32)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8870.d b/src/arch/arm/v7/opdefs/ldrb_A8870.d
index 0de0af2..868b1c9 100644
--- a/src/arch/arm/v7/opdefs/ldrb_A8870.d
+++ b/src/arch/arm/v7/opdefs/ldrb_A8870.d
@@ -25,7 +25,7 @@
 
 @encoding(t1) {
 
-    @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3)
+    @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3)
 
     @syntax <Rgt> <access>
 
diff --git a/src/arch/arm/v7/opdefs/lsr_A8896.d b/src/arch/arm/v7/opdefs/lsr_A8896.d
new file mode 100644
index 0000000..8e3f274
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/lsr_A8896.d
@@ -0,0 +1,98 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2015 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LSR (immediate)
+
+@encoding(t1) {
+
+    @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3)
+
+    @syntax <Rgd> <Rgm> <shift>
+
+    @conv {
+
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(1, imm5)
+
+    }
+
+    @rules {
+
+        if (imm5 == '00000') ; see MOV (register, Thumb)
+        //if (imm5 == '00000') ; see MOV (register)
+
+    }
+
+}
+
+@encoding(T2) {
+
+    @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4)
+
+    @syntax {s} <Rgd> <Rgm> <shift>
+
+    @conv {
+
+        S = SetFlags(S)
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(1, imm3:imm2)
+
+    }
+
+    @rules {
+
+        if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb)
+        //if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb)
+        //if (imm3:imm2) == '00000' then SEE MOV (register);
+        //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(A1) {
+
+    @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4)
+
+    @syntax {S} {c} <Rgd> <Rgm> <shift>
+
+    @conv {
+
+        S = SetFlags(S)
+        c = Condition(cond)
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(1, imm5)
+
+    }
+
+    @rules {
+
+        //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
+        //if imm5 == '00000' then SEE MOV (register);
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/strb_A88207.d b/src/arch/arm/v7/opdefs/strb_A88207.d
new file mode 100644
index 0000000..b57dbf7
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/strb_A88207.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title STRB (immediate, ARM)
+
+@encoding(A11) {
+
+    @word cond(4) 0 1 0 1 U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        access = MakeMemoryAccess(Rgn, imm32, U, W)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
+
+@encoding(A12) {
+
+    @word cond(4) 0 1 0 0 U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <base> <offset>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        base = MakeMemoryNotIndexed(Rgn, W)
+        offset = MakeAccessOffset(U, imm32)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/uxtb_A88274.d b/src/arch/arm/v7/opdefs/uxtb_A88274.d
index 97b17de..8917144 100644
--- a/src/arch/arm/v7/opdefs/uxtb_A88274.d
+++ b/src/arch/arm/v7/opdefs/uxtb_A88274.d
@@ -42,7 +42,7 @@
 
     @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4)
 
-    @syntax <Rd> <Rm> <?rotation>
+    @syntax "uxtb.W" <Rd> <Rm> <?rotation>
 
     @conv {