diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2016-05-06 21:19:50 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2016-05-06 21:19:50 (GMT) |
commit | 2fc5cc35c256d5bdbe72a1218082e91ddbc3e193 (patch) | |
tree | 2d151e3e79748d730c7f029b46dd488991915b5a /src/arch/arm/v7/thumb_32.c | |
parent | 33d49eb64654fc5dc5f617ce02ae3fffb6a75adb (diff) |
Prepared the ARMv7 SIMD instructions support.
Diffstat (limited to 'src/arch/arm/v7/thumb_32.c')
-rw-r--r-- | src/arch/arm/v7/thumb_32.c | 33 |
1 files changed, 11 insertions, 22 deletions
diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c index 9dbad13..7f6ae74 100644 --- a/src/arch/arm/v7/thumb_32.c +++ b/src/arch/arm/v7/thumb_32.c @@ -24,10 +24,10 @@ #include "thumb_32.h" -#include <assert.h> #include <stdint.h> +#include "simd.h" #include "opcodes/thumb_32_opcodes.h" #include "opcodes/opcodes_tmp_thumb_32.h" #include "../../undefined.h" @@ -182,9 +182,7 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw) result = g_undef_instruction_new(IBS_UNDEFINED); else if ((op2 & b1110001) == b0010000) - /* Advanced SIMD element or structure load/store instructions on page A7-275 */ - /*result = process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(raw);*/ - assert(false); + result = process_armv7_simd_advanced_simd_element_or_structure_load_store_instructions(raw, false); else if ((op2 & b1110000) == b0100000) result = process_armv7_thumb_32_data_processing_register(raw); @@ -988,8 +986,7 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3 result = armv7_read_thumb_32_instr_ldrsh_literal(raw); else/* if (rt == b1111)*/ - /* Unallocated memory hint (treat as NOP) */ - assert(false); + result = g_undef_instruction_new(IBS_NOP); } @@ -1044,12 +1041,10 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3 result = armv7_read_thumb_32_instr_ldrsht(raw); else if (op2 == b000000 && rt == b1111) - /* Unallocated memory hint (treat as NOP) */ - assert(false); + result = g_undef_instruction_new(IBS_NOP); else if ((op2 & b111100) == b110000 && rt == b1111) - /* Unallocated memory hint (treat as NOP) */ - assert(false); + result = g_undef_instruction_new(IBS_NOP); } @@ -1059,8 +1054,7 @@ static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint3 result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); else/* if (rt == b1111)*/ - /* Unallocated memory hint (treat as NOP) */ - assert(false); + result = g_undef_instruction_new(IBS_NOP); } @@ -2215,8 +2209,7 @@ static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_fl result = g_undef_instruction_new(IBS_UNDEFINED); else if ((op1 & b110000) == b110000) - /* Advanced SIMD data-processing instructions on page A7-261 */ - assert(false); + result = process_armv7_simd_advanced_simd_data_processing_instructions(raw, false); else if ((coproc & b1110) != b1010) { @@ -2253,22 +2246,18 @@ static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_fl else if ((coproc & b1110) == b1010) { if ((op1 & b100000) == b000000 && (op1 & b111010) != b000000) - /* Extension register load/store instructions on page A7-274 */ - assert(false); + result = process_armv7_simd_extension_register_load_store_instructions(raw, false); else if ((op1 & b111110) == b000100) - /* 64-bit transfers between ARM core and extension registers on page A7-279 */ - assert(false); + result = process_armv7_simd_64_bit_transfers_between_arm_core_and_extension_registers(raw, false); else if ((op1 & b110000) == b100000) { if (op == b0) - /* Floating-point data-processing instructions on page A7-272 */ - assert(false); + result = process_armv7_simd_floating_point_data_processing_instructions(raw, false); else/* if (op == b1)*/ - /* 8, 16, and 32-bit transfer between ARM core and extension registers on page A7-278 */ - assert(false); + result = process_armv7_simd_8_16_and_32_bit_transfer_between_arm_core_and_extension_registers(raw, false); } |