diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2016-04-21 20:14:04 (GMT) |
---|---|---|
committer | Cyrille Bagard <nocbos@gmail.com> | 2016-04-21 20:14:04 (GMT) |
commit | d062f5ffbac1250938206f4d2e15c44d8a9357f6 (patch) | |
tree | b7bf90248866925515b3c2029eb7e9bbc12e6e05 /src/arch/arm/v7/thumb_32.c | |
parent | c517a9defa6fae19007a398e0594074d08d18fd0 (diff) |
Got prepared for more ARMv7 opcodes.
Diffstat (limited to 'src/arch/arm/v7/thumb_32.c')
-rw-r--r-- | src/arch/arm/v7/thumb_32.c | 605 |
1 files changed, 543 insertions, 62 deletions
diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c index 9d9de57..c1e3f3c 100644 --- a/src/arch/arm/v7/thumb_32.c +++ b/src/arch/arm/v7/thumb_32.c @@ -24,6 +24,7 @@ #include "thumb_32.h" +#include <assert.h> #include <stdint.h> @@ -33,78 +34,65 @@ - - - -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.1. */ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immediate(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.3. */ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_immediate(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4. */ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ -static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_change_processor_state_and_hints(uint32_t); +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4b. */ +static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ -static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_miscellaneous_control_instructions(uint32_t); +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.4t. */ +static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructions(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.5. */ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t); +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.6. */ +static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(uint32_t); - -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.7. */ static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t); +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.8. */ +static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint32_t); - - -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.9. */ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.10. */ static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.11. */ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.11b. */ +static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shifts(uint32_t); + +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.12. */ static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.13. */ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_signed(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.14. */ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtraction_unsigned(uint32_t); - -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.15. */ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.16. */ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and_absolute_difference(uint32_t); -/* Désassemble une instruction ARMv7 classique. */ +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.17. */ static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accumulate_and_divide(uint32_t); - - - - - -#define process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(r) NULL -#define process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(r) NULL - -#define process_armv7_thumb_32_load_halfword_memory_hints(r) NULL -#define process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(r) NULL -#define process_armv7_thumb_32_move_register_and_immediate_shifts(r) NULL - - - - +/* Désassemble une instruction ARMv7 liées au chapitre A6.3.18. */ +static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(uint32_t); @@ -112,7 +100,7 @@ static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accu * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 en mode Thumb 32 bits. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -195,7 +183,9 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw) */ else if ((op2 & b1110001) == b0010000) - result = process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(raw); + /* Advanced SIMD element or structure load/store instructions on page A7-275 */ + /*result = process_armv7_thumb_32_advanced_simd_element_or_structure_load_store_instructions(raw);*/ + assert(false); else if ((op2 & b1110000) == b0100000) result = process_armv7_thumb_32_data_processing_register(raw); @@ -222,7 +212,7 @@ GArchInstruction *process_armv7_thumb_32_instruction_set_encoding(uint32_t raw) * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.1. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -256,6 +246,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia if (rds == b11111) result = armv7_read_thumb_32_instr_tst_immediate(raw); + else result = armv7_read_thumb_32_instr_and_immediate(raw); @@ -269,6 +260,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia if (rn == b1111) result = armv7_read_thumb_32_instr_mov_immediate(raw); + else result = armv7_read_thumb_32_instr_orr_immediate(raw); @@ -278,6 +270,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia if (rn == b1111) result = armv7_read_thumb_32_instr_mvn_immediate(raw); + else result = armv7_read_thumb_32_instr_orn_immediate(raw); @@ -287,6 +280,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia if (rds == b11111) result = armv7_read_thumb_32_instr_teq_immediate(raw); + else result = armv7_read_thumb_32_instr_eor_immediate(raw); @@ -296,6 +290,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia if (rds == b11111) result = armv7_read_thumb_32_instr_cmn_immediate(raw); + else result = armv7_read_thumb_32_instr_add_immediate_thumb(raw); @@ -313,6 +308,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia if (rds == b11111) result = armv7_read_thumb_32_instr_cmp_immediate(raw); + else result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw); @@ -333,7 +329,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.3. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -365,6 +361,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm if (rn == b1111) result = armv7_read_thumb_32_instr_adr(raw); + else result = armv7_read_thumb_32_instr_add_immediate_thumb(raw); @@ -378,6 +375,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm if (rn == b11111) result = armv7_read_thumb_32_instr_adr(raw); + else result = armv7_read_thumb_32_instr_sub_immediate_thumb(raw); @@ -392,10 +390,13 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm break; case b10010: + if ((raw & 0x000070c0) != 0) result = armv7_read_thumb_32_instr_ssat(raw); + else result = armv7_read_thumb_32_instr_ssat16(raw); + break; case b10100: @@ -406,6 +407,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm if (rn == b11111) result = armv7_read_thumb_32_instr_bfc(raw); + else result = armv7_read_thumb_32_instr_bfi(raw); @@ -416,10 +418,13 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm break; case b11010: + if ((raw & 0x000070c0) != 0) result = armv7_read_thumb_32_instr_usat(raw); + else result = armv7_read_thumb_32_instr_usat16(raw); + break; case b11100: @@ -437,7 +442,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_plain_binary_imm * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.4. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -494,10 +499,10 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr result = armv7_read_thumb_32_instr_b_msr_register(raw); else if (op == b0111010) - result = process_armv7_thumb_32_branches_and_miscellaneous_control_change_processor_state_and_hints(raw); + result = process_armv7_thumb_32_change_processor_state_and_hints(raw); else if (op == b0111011) - result = process_armv7_thumb_32_branches_and_miscellaneous_control_miscellaneous_control_instructions(raw); + result = process_armv7_thumb_32_miscellaneous_control_instructions(raw); else if (op == b0111100) result = armv7_read_thumb_32_instr_bxj(raw); @@ -542,13 +547,13 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr * * * Description : Désassemble une instruction ARMv7 classique. * * * -* Retour : Instruction mise en place ou NULL en cas d'échec. * +* Retour : Désassemble une instruction ARMv7 liées au chapitre A6.3.4b. * * * * Remarques : - * * * ******************************************************************************/ -static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_change_processor_state_and_hints(uint32_t raw) +static GArchInstruction *process_armv7_thumb_32_change_processor_state_and_hints(uint32_t raw) { GArchInstruction *result; /* Instruction à renvoyer */ uint32_t op1; /* Champ 'op1' à retrouver */ @@ -601,7 +606,7 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.4t. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -609,7 +614,7 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr * * ******************************************************************************/ -static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_control_miscellaneous_control_instructions(uint32_t raw) +static GArchInstruction *process_armv7_thumb_32_miscellaneous_control_instructions(uint32_t raw) { GArchInstruction *result; /* Instruction à renvoyer */ uint32_t op; /* Champ 'op' à retrouver */ @@ -663,7 +668,7 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.5. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -697,6 +702,7 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw if (l == b0) result = armv7_read_thumb_32_instr_srs_thumb(raw); + else result = armv7_read_thumb_32_instr_rfe(raw); @@ -711,8 +717,10 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw { if (wrn == b11101) result = armv7_read_thumb_32_instr_pop_thumb(raw); + else result = armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(raw); + } break; @@ -723,8 +731,10 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw { if (wrn == b11101) result = armv7_read_thumb_32_instr_push(raw); + else result = armv7_read_thumb_32_instr_stmdb_stmfd(raw); + } else @@ -736,6 +746,7 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw if (l == b0) result = armv7_read_thumb_32_instr_srs_thumb(raw); + else result = armv7_read_thumb_32_instr_rfe(raw); @@ -748,21 +759,124 @@ static GArchInstruction *process_armv7_thumb_32_load_store_multiple(uint32_t raw } +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.6. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_thumb_32_load_store_dual_load_store_exclusive_table_branch(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t op3; /* Champ 'op3' à retrouver */ + + /** + * Suit les directives de : + * § A6.3.6 Load/store dual, load/store exclusive, table branch + */ + + if ((raw & 0xfe400000) != 0xe8400000) return NULL; + + result = NULL; + + op1 = (raw >> 23) & 0x3; + op2 = (raw >> 20) & 0x3; + rn = (raw >> 16) & 0xf; + op3 = (raw >> 4) & 0xf; + + if (op1 == b00 && op2 == b00) + result = armv7_read_thumb_32_instr_strex(raw); + + else if (op1 == b00 && op2 == b01) + result = armv7_read_thumb_32_instr_ldrex(raw); + + else if ((op1 & b10) == b00 && op2 == b10) + result = armv7_read_thumb_32_instr_strd_immediate(raw); + + else if ((op1 & b10) == b10 && (op2 & b01) == b00) + result = armv7_read_thumb_32_instr_strd_immediate(raw); + + else if ((op1 & b10) == b00 && op2 == b11) + { + if (rn != b1111) + result = armv7_read_thumb_32_instr_ldrd_immediate(raw); + + else/* if (rn == b1111)*/ + result = armv7_read_thumb_32_instr_ldrd_literal(raw); + + } + + else if ((op1 & b10) == b10 && (op2 & b01) == b01) + { + if (rn != b1111) + result = armv7_read_thumb_32_instr_ldrd_immediate(raw); + + else/* if (rn == b1111)*/ + result = armv7_read_thumb_32_instr_ldrd_literal(raw); + + } + + else if (op1 == b01 && op2 == b00) + switch (op3) + { + case b0100: + result = armv7_read_thumb_32_instr_strexb(raw); + break; + + case b0101: + result = armv7_read_thumb_32_instr_strexh(raw); + break; + case b0111: + result = armv7_read_thumb_32_instr_strexd(raw); + break; + } + else if (op1 == b01 && op2 == b01) + switch (op3) + { + case b0000: + result = armv7_read_thumb_32_instr_tbb_tbh(raw); + break; + case b0001: + result = armv7_read_thumb_32_instr_tbb_tbh(raw); + break; + case b0100: + result = armv7_read_thumb_32_instr_ldrexb(raw); + break; + case b0101: + result = armv7_read_thumb_32_instr_ldrexh(raw); + break; + case b0111: + result = armv7_read_thumb_32_instr_ldrexd(raw); + break; + } + + return result; + +} /****************************************************************************** * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.7. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -823,22 +937,146 @@ static GArchInstruction *process_armv7_thumb_32_load_word(uint32_t raw) } +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.8. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_thumb_32_load_halfword_memory_hints(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t rt; /* Champ 'rt' à retrouver */ + uint32_t op2; /* Champ 'op2' à retrouver */ + + /** + * Suit les directives de : + * § A6.3.8 Load halfword, memory hints + */ + + if ((raw & 0xfe700000) != 0xf8300000) return NULL; + + result = NULL; + + op1 = (raw >> 23) & 0x3; + rn = (raw >> 16) & 0xf; + rt = (raw >> 12) & 0xf; + op2 = (raw >> 6) & 0x3f; + + if (rn == b1111) + { + if ((op1 & b10) == b00) + { + if (rt != b1111) + result = armv7_read_thumb_32_instr_ldrh_literal(raw); + + else/* if (rt == b1111)*/ + result = armv7_read_thumb_32_instr_pld_literal(raw); + + } + + else/* if ((op1 & b10) == b10)*/ + { + if (rt != b1111) + result = armv7_read_thumb_32_instr_ldrsh_literal(raw); + + else/* if (rt == b1111)*/ + /* Unallocated memory hint (treat as NOP) */ + assert(false); + + } + + } + + else/* if (rn != b1111)*/ + { + if (op1 == b00) + { + if ((op2 & b100100) == b100100) + result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); + else if ((op2 & b111100) == b110000 && rt != b1111) + result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); + + else if (op2 == b000000 && rt != b1111) + result = armv7_read_thumb_32_instr_ldrh_register(raw); + + else if ((op2 & b111100) == b111000) + result = armv7_read_thumb_32_instr_ldrht(raw); + else if (op2 == b000000 && rt == b1111) + result = armv7_read_thumb_32_instr_pld_pldw_register(raw); + else if ((op2 & b111100) == b110000 && rt == b1111) + result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw); + } + else if (op1 == b01) + { + if (rt != b1111) + result = armv7_read_thumb_32_instr_ldrh_immediate_thumb(raw); + else/* if (rt == b1111)*/ + result = armv7_read_thumb_32_instr_pld_pldw_immediate(raw); + } + + else if (op1 == b10) + { + if ((op2 & b100100) == b100100) + result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); + + else if ((op2 & b111100) == b110000 && rt != b1111) + result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); + + else if (op2 == b000000 && rt != b1111) + result = armv7_read_thumb_32_instr_ldrsh_register(raw); + + else if ((op2 & b111100) == b111000) + result = armv7_read_thumb_32_instr_ldrsht(raw); + else if (op2 == b000000 && rt == b1111) + /* Unallocated memory hint (treat as NOP) */ + assert(false); + else if ((op2 & b111100) == b110000 && rt == b1111) + /* Unallocated memory hint (treat as NOP) */ + assert(false); + + } + + else if (op1 == b11) + { + if (rt != b1111) + result = armv7_read_thumb_32_instr_ldrsh_immediate(raw); + + else/* if (rt == b1111)*/ + /* Unallocated memory hint (treat as NOP) */ + assert(false); + + } + + } + + return result; + +} /****************************************************************************** * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.9. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -872,16 +1110,20 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrb_register(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pld_register(raw); + } else if ((op1 & b10) == b00 && rn == b1111) { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrb_literal(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pld_literal(raw); + } else if (op1 == b00 && (op2 & b100100) == b100100 && rn != b1111) @@ -891,8 +1133,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pld_immediate(raw); + } else if (op1 == b00 && (op2 & b111100) == b111000 && rn != b1111) @@ -902,8 +1146,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrb_immediate_thumb(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pld_immediate(raw); + } if (op1 == b10 && op2 == b000000 && rn != b1111) @@ -918,8 +1164,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrsb_literal(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); + } else if (op1 == b10 && (op2 & b100100) == b100100 && rn != b1111) @@ -929,8 +1177,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); + } else if (op1 == b10 && (op2 & b111100) == b111000 && rn != b1111) @@ -940,8 +1190,10 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t { if (rt != b1111) result = armv7_read_thumb_32_instr_ldrsb_immediate(raw); + else /*if (rt == b1111) */ result = armv7_read_thumb_32_instr_pli_immediate_literal(raw); + } return result; @@ -953,7 +1205,7 @@ static GArchInstruction *process_armv7_thumb_32_load_byte_memory_hints(uint32_t * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.10. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1052,7 +1304,7 @@ static GArchInstruction *process_armv7_thumb_32_store_single_data_item(uint32_t * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.11. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1086,6 +1338,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register if (rds == b11111) result = armv7_read_thumb_32_instr_tst_register(raw); + else result = armv7_read_thumb_32_instr_and_register(raw); @@ -1099,6 +1352,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register if (rn == b11111) result = process_armv7_thumb_32_move_register_and_immediate_shifts(raw); + else result = armv7_read_thumb_32_instr_orr_register(raw); @@ -1108,6 +1362,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register if (rn == b11111) result = armv7_read_thumb_32_instr_mvn_register(raw); + else result = armv7_read_thumb_32_instr_orn_register(raw); @@ -1117,6 +1372,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register if (rds == b11111) result = armv7_read_thumb_32_instr_teq_register(raw); + else result = armv7_read_thumb_32_instr_eor_register(raw); @@ -1130,6 +1386,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register if (rds == b11111) result = armv7_read_thumb_32_instr_cmn_register(raw); + else result = armv7_read_thumb_32_instr_add_register_thumb(raw); @@ -1147,6 +1404,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register if (rds == b11111) result = armv7_read_thumb_32_instr_cmp_register(raw); + else result = armv7_read_thumb_32_instr_sub_register_thumb(raw); @@ -1167,7 +1425,75 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_shifted_register * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.11b.* +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_thumb_32_move_register_and_immediate_shifts(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t imm5; /* Champs 'imm[32]' à retrouver*/ + uint32_t type; /* Champ 'type' à retrouver */ + + /** + * Suit les directives de : + * § A6.3.11 Data-processing (shifted register) + * |-> Move register and immediate shifts + */ + + if ((raw & 0xffef0000) != 0xea4f0000) return NULL; + + result = NULL; + + imm5 = (((raw >> 12) & 0x7) << 2) | ((raw >> 6) & 0x3); + type = (raw >> 4) & 0x3; + + switch (type) + { + case b00: + + if (imm5 == b00000) + result = armv7_read_thumb_32_instr_mov_register_thumb(raw); + + else/* if (imm5 != b00000)*/ + result = armv7_read_thumb_32_instr_lsl_immediate(raw); + + break; + + case b01: + result = armv7_read_thumb_32_instr_lsr_immediate(raw); + break; + + case b10: + result = armv7_read_thumb_32_instr_asr_immediate(raw); + break; + + case b11: + + if (imm5 == b00000) + result = armv7_read_thumb_32_instr_rrx(raw); + + else/* if (imm5 != b00000)*/ + result = armv7_read_thumb_32_instr_ror_immediate(raw); + + break; + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.12. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1211,48 +1537,60 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_ { if (rn == b1111) result = armv7_read_thumb_32_instr_sxth(raw); + else result = armv7_read_thumb_32_instr_sxtah(raw); + } else if (op1 == b0001 && (op2 & b1000) == b1000) { if (rn == b1111) result = armv7_read_thumb_32_instr_uxth(raw); + else result = armv7_read_thumb_32_instr_uxtah(raw); + } else if (op1 == b0010 && (op2 & b1000) == b1000) { if (rn == b1111) result = armv7_read_thumb_32_instr_sxtb16(raw); + else result = armv7_read_thumb_32_instr_sxtab16(raw); + } else if (op1 == b0011 && (op2 & b1000) == b1000) { if (rn == b1111) result = armv7_read_thumb_32_instr_uxtb16(raw); + else result = armv7_read_thumb_32_instr_uxtab16(raw); + } else if (op1 == b0100 && (op2 & b1000) == b1000) { if (rn == b1111) result = armv7_read_thumb_32_instr_sxtb(raw); + else result = armv7_read_thumb_32_instr_sxtab(raw); + } else if (op1 == b0101 && (op2 & b1000) == b1000) { if (rn == b1111) result = armv7_read_thumb_32_instr_uxtb(raw); + else result = armv7_read_thumb_32_instr_uxtab(raw); + } else if ((op1 & b1000) == b1000 && (op2 & b1100) == b0000) @@ -1273,7 +1611,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_register(uint32_ * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.13. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1307,21 +1645,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio case b001: result = armv7_read_thumb_32_instr_sadd16(raw); break; + case b010: result = armv7_read_thumb_32_instr_sasx(raw); break; + case b110: result = armv7_read_thumb_32_instr_ssax(raw); break; + case b101: result = armv7_read_thumb_32_instr_ssub16(raw); break; + case b000: result = armv7_read_thumb_32_instr_sadd8(raw); break; + case b100: result = armv7_read_thumb_32_instr_ssub8(raw); break; + } break; @@ -1331,21 +1675,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio case b001: result = armv7_read_thumb_32_instr_sqadd16(raw); break; + case b010: result = armv7_read_thumb_32_instr_sqasx(raw); break; + case b110: result = armv7_read_thumb_32_instr_sqsax(raw); break; + case b101: result = armv7_read_thumb_32_instr_sqsub16(raw); break; + case b000: result = armv7_read_thumb_32_instr_sqadd8(raw); break; + case b100: result = armv7_read_thumb_32_instr_sqsub8(raw); break; + } break; @@ -1355,21 +1705,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio case b001: result = armv7_read_thumb_32_instr_shadd16(raw); break; + case b010: result = armv7_read_thumb_32_instr_shasx(raw); break; + case b110: result = armv7_read_thumb_32_instr_shsax(raw); break; + case b101: result = armv7_read_thumb_32_instr_shsub16(raw); break; + case b000: result = armv7_read_thumb_32_instr_shadd8(raw); break; + case b100: result = armv7_read_thumb_32_instr_shsub8(raw); break; + } break; @@ -1384,7 +1740,7 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.14. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1418,21 +1774,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio case b001: result = armv7_read_thumb_32_instr_uadd16(raw); break; + case b010: result = armv7_read_thumb_32_instr_uasx(raw); break; + case b110: result = armv7_read_thumb_32_instr_usax(raw); break; + case b101: result = armv7_read_thumb_32_instr_usub16(raw); break; + case b000: result = armv7_read_thumb_32_instr_uadd8(raw); break; + case b100: result = armv7_read_thumb_32_instr_usub8(raw); break; + } break; @@ -1442,21 +1804,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio case b001: result = armv7_read_thumb_32_instr_uqadd16(raw); break; + case b010: result = armv7_read_thumb_32_instr_uqasx(raw); break; + case b110: result = armv7_read_thumb_32_instr_uqsax(raw); break; + case b101: result = armv7_read_thumb_32_instr_uqsub16(raw); break; + case b000: result = armv7_read_thumb_32_instr_uqadd8(raw); break; + case b100: result = armv7_read_thumb_32_instr_uqsub8(raw); break; + } break; @@ -1466,21 +1834,27 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio case b001: result = armv7_read_thumb_32_instr_uhadd16(raw); break; + case b010: result = armv7_read_thumb_32_instr_uhasx(raw); break; + case b110: result = armv7_read_thumb_32_instr_uhsax(raw); break; + case b101: result = armv7_read_thumb_32_instr_uhsub16(raw); break; + case b000: result = armv7_read_thumb_32_instr_uhadd8(raw); break; + case b100: result = armv7_read_thumb_32_instr_uhsub8(raw); break; + } break; @@ -1495,7 +1869,7 @@ static GArchInstruction *process_armv7_thumb_32_parallel_addition_and_subtractio * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.15. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1529,15 +1903,19 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_ case b00: result = armv7_read_thumb_32_instr_qadd(raw); break; + case b01: result = armv7_read_thumb_32_instr_qdadd(raw); break; + case b10: result = armv7_read_thumb_32_instr_qsub(raw); break; + case b11: result = armv7_read_thumb_32_instr_qdsub(raw); break; + } break; @@ -1547,15 +1925,19 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_ case b00: result = armv7_read_thumb_32_instr_rev(raw); break; + case b01: result = armv7_read_thumb_32_instr_rev16(raw); break; + case b10: result = armv7_read_thumb_32_instr_rbit(raw); break; + case b11: result = armv7_read_thumb_32_instr_revsh(raw); break; + } break; @@ -1580,7 +1962,7 @@ static GArchInstruction *process_armv7_thumb_32_miscellaneous_operations(uint32_ * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.16. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1616,8 +1998,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and { if (ra == b1111) result = armv7_read_thumb_32_instr_mul(raw); + else result = armv7_read_thumb_32_instr_mla(raw); + } else if (op2 == b01) @@ -1629,6 +2013,7 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and if (ra == b1111) result = armv7_read_thumb_32_instr_smulbb_smulbt_smultb_smultt(raw); + else result = armv7_read_thumb_32_instr_smlabb_smlabt_smlatb_smlatt(raw); @@ -1639,8 +2024,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and { if (ra == b1111) result = armv7_read_thumb_32_instr_smuad(raw); + else result = armv7_read_thumb_32_instr_smlad(raw); + } break; @@ -1649,8 +2036,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and { if (ra == b1111) result = armv7_read_thumb_32_instr_smulwb_smulwt(raw); + else result = armv7_read_thumb_32_instr_smlawb_smlawt(raw); + } break; @@ -1659,8 +2048,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and { if (ra == b1111) result = armv7_read_thumb_32_instr_smusd(raw); + else result = armv7_read_thumb_32_instr_smlsd(raw); + } break; @@ -1669,8 +2060,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and { if (ra == b1111) result = armv7_read_thumb_32_instr_smmul(raw); + else result = armv7_read_thumb_32_instr_smmla(raw); + } break; @@ -1684,8 +2077,10 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and { if (ra == b1111) result = armv7_read_thumb_32_instr_usad8(raw); + else result = armv7_read_thumb_32_instr_usada8(raw); + } break; @@ -1700,7 +2095,7 @@ static GArchInstruction *process_armv7_thumb_32_multiply_multiply_accumulate_and * * * Paramètres : raw = donnée brute de 32 bits à désassembler. * * * -* Description : Désassemble une instruction ARMv7 classique. * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.17. * * * * Retour : Instruction mise en place ou NULL en cas d'échec. * * * @@ -1783,18 +2178,104 @@ static GArchInstruction *process_armv7_thumb_32_long_multiply_long_multiply_accu } +/****************************************************************************** +* * +* Paramètres : raw = donnée brute de 32 bits à désassembler. * +* * +* Description : Désassemble une instruction ARMv7 liées au chapitre A6.3.18. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *process_armv7_thumb_32_coprocessor_advanced_simd_and_floating_point_instructions(uint32_t raw) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint32_t op1; /* Champ 'op1' à retrouver */ + uint32_t rn; /* Champ 'rn' à retrouver */ + uint32_t coproc; /* Champ 'coproc' à retrouver */ + uint32_t op; /* Champ 'op' à retrouver */ + + /** + * Suit les directives de : + * § A6.3.18 Coprocessor, Advanced SIMD, and Floating-point instructions + */ + + if ((raw & 0xec000000) != 0xec000000) return NULL; + + result = NULL; + + op1 = (raw >> 20) & 0x3f; + rn = (raw >> 16) & 0xf; + coproc = (raw >> 8) & 0xf; + op = (raw >> 4) & 0x1; + + if ((op1 & b111110) == b000000) + /* UNDEFINED */ + assert(false); + + else if ((op1 & b110000) == b110000) + /* Advanced SIMD data-processing instructions on page A7-261 */ + assert(false); + else if ((coproc & b1110) != b1010) + { + if ((op1 & b100001) == b000000 && (op1 & b111010) != b000000) + result = armv7_read_thumb_32_instr_stc_stc2(raw); + + else if ((op1 & b100001) == b000001 && (op1 & b111010) != b000000) + { + if (rn != b1111) + result = armv7_read_thumb_32_instr_ldc_ldc2_immediate(raw); + + else/* if (rn == b1111)*/ + result = armv7_read_thumb_32_instr_ldc_ldc2_literal(raw); + + } + else if (op1 == b000100) + result = armv7_read_thumb_32_instr_mcrr_mcrr2(raw); + else if (op1 == b000101) + result = armv7_read_thumb_32_instr_mrrc_mrrc2(raw); + else if ((op1 & b110000) == b100000 && op == b0) + result = armv7_read_thumb_32_instr_cdp_cdp2(raw); + else if ((op1 & b110001) == b100000 && op == b1) + result = armv7_read_thumb_32_instr_mcr_mcr2(raw); + else if ((op1 & b110001) == b100001 && op == b1) + result = armv7_read_thumb_32_instr_mrc_mrc2(raw); + } + else if ((coproc & b1110) == b1010) + { + if ((op1 & b100000) == b000000 && (op1 & b111010) != b000000) + /* Extension register load/store instructions on page A7-274 */ + assert(false); + else if ((op1 & b111110) == b000100) + /* 64-bit transfers between ARM core and extension registers on page A7-279 */ + assert(false); + else if ((op1 & b110000) == b100000) + { + if (op == b0) + /* Floating-point data-processing instructions on page A7-272 */ + assert(false); + else/* if (op == b1)*/ + /* 8, 16, and 32-bit transfer between ARM core and extension registers on page A7-278 */ + assert(false); + } + } + return result; +} |