Fixed and extended the support for ARM v7 instructions.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@542 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

9 files changed, 631 insertions, 16 deletions

diff --git a/src/arch/arm/v7/arm.c b/src/arch/arm/v7/arm.c
index 2c0cabb..176d171 100644
--- a/src/arch/arm/v7/arm.c
+++ b/src/arch/arm/v7/arm.c
@@ -52,6 +52,23 @@ static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint
 static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uint32_t);
 
 
+
+/* Désassemble une instruction ARMv7 de données ou autre. */
+static GArchInstruction *process_armv7_arm_media_instructions(uint32_t);
+
+
+
+#define process_armv7_arm_parallel_addition_and_subtraction_signed(raw) NULL
+#define process_armv7_arm_parallel_addition_and_subtraction_unsigned(raw) NULL
+#define process_armv7_arm_signed_multiply_signed_and_unsigned_divide(raw) NULL
+
+
+
+/* Désassemble une instruction ARMv7 de données ou autre. */
+static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t);
+
+
+
 /* Désassemble une instruction ARMv7 de données ou autre. */
 static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_data_transfer(uint32_t);
 
@@ -61,7 +78,7 @@ static GArchInstruction *process_armv7_arm_branch_branch_with_link_and_block_dat
 
 //#define process_armv7_arm_load_store_word_and_unsigned_byte(raw) NULL
 //#define process_armv7_arm_load_store_word_and_unsigned_byte(raw) NULL
-#define process_armv7_arm_media_instructions(raw) NULL
+//#define process_armv7_arm_media_instructions(raw) NULL
 //#define process_armv7_arm_branch_branch_with_link_and_block_data_transfer(raw) NULL
 #define process_armv7_arm_coprocessor_instructions_and_Supervisor_call(raw) NULL
 #define process_armv7_arm_unconditional_instructions(raw) NULL
@@ -531,10 +548,10 @@ static GArchInstruction *process_armv7_arm_multiply_and_multiply_accumulate(uint
 
     result = NULL;
 
-    if ((raw & 0x0f0000f0) == 0x00000090)
+    if ((raw & 0x0f0000f0) != 0x00000090)
         return NULL;
 
-    op = (raw >> 20) & 0x1f;
+    op = (raw >> 20) & 0xf;
 
     if ((op & b1110) == b0000)
         result = armv7_read_arm_instr_mul(raw);
@@ -637,7 +654,7 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
     {
         if (a == b0)
         {
-            result = armv7_read_arm_instr_strt(raw);
+            result = armv7_read_arm_instr_ldrt(raw);
             goto a53_done;
         }
         else if (/*a == b1 && */b == b0)
@@ -657,7 +674,7 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
         }
         else if (/*a == b1 && */b == b0)
         {
-            result = armv7_read_arm_instr_str_register(raw);
+            result = armv7_read_arm_instr_ldr_register(raw);
             goto a53_done;
         }
     }
@@ -666,7 +683,7 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
     {
         if (a == b0)
         {
-            result = armv7_read_arm_instr_strt(raw);
+            result = armv7_read_arm_instr_strbt(raw);
             goto a53_done;
         }
         else if (/*a == b1 && */b == b0)
@@ -676,12 +693,12 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
     {
         if (a == b0)
         {
-            result = armv7_read_arm_instr_str_immediate_arm(raw);
+            result = armv7_read_arm_instr_strb_immediate_arm(raw);
             goto a53_done;
         }
         else if (/*a == b1 && */b == b0)
         {
-            result = armv7_read_arm_instr_str_register(raw);
+            result = armv7_read_arm_instr_strb_register(raw);
             goto a53_done;
         }
     }
@@ -690,7 +707,7 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
     {
         if (a == b0)
         {
-            result = armv7_read_arm_instr_strt(raw);
+            result = armv7_read_arm_instr_ldrbt(raw);
             goto a53_done;
         }
         else if (/*a == b1 && */b == b0)
@@ -701,16 +718,16 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
         if (a == b0)
         {
             if (rn == b1111)
-                result = armv7_read_arm_instr_ldr_literal(raw);
+                result = armv7_read_arm_instr_ldrb_literal(raw);
             else
-                result = armv7_read_arm_instr_ldr_immediate_arm(raw);
+                result = armv7_read_arm_instr_ldrb_immediate_arm(raw);
 
             goto a53_done;
 
         }
         else if (/*a == b1 && */b == b0)
         {
-            result = armv7_read_arm_instr_str_register(raw);
+            result = armv7_read_arm_instr_ldrb_register(raw);
             goto a53_done;
         }
     }
@@ -730,6 +747,311 @@ static GArchInstruction *process_armv7_arm_load_store_word_and_unsigned_byte(uin
 
 
 
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 de données ou autre.       *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_media_instructions(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t cond;                          /* Champ 'cond' à retrouver    */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t rd;                            /* Champ 'rd' à retrouver      */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+    uint32_t rn;                            /* Champ 'rn' à retrouver      */
+
+    /**
+     * Suit les directives de :
+     * § A5.4 Media instructions
+     */
+
+    result = NULL;
+
+    if ((raw & 0x0e000010) != 0x06000010)
+        return NULL;
+
+    cond = (raw >> 28) & 0xf;
+    op1 = (raw >> 20) & 0x1f;
+    rd = (raw >> 12) & 0xf;
+    op2 = (raw >> 5) & 0x7;
+    rn = (raw >> 0) & 0xf;
+
+    if ((op1 & b11100) == b00000)
+        result = process_armv7_arm_parallel_addition_and_subtraction_signed(raw);
+
+    else if ((op1 & b11100) == b00100)
+        result = process_armv7_arm_parallel_addition_and_subtraction_unsigned(raw);
+
+    else if ((op1 & b11000) == b01000)
+        result = process_armv7_arm_packing_unpacking_saturation_and_reversal(raw);
+
+    else if ((op1 & b11000) == b10000)
+        result = process_armv7_arm_signed_multiply_signed_and_unsigned_divide(raw);
+
+    else if (op1 == b11000)
+    {
+        if (op2 == b000)
+        {
+            if (rd == b1111)
+                result = armv7_read_arm_instr_usad8(raw);
+            else
+                result = armv7_read_arm_instr_usada8(raw);
+        }
+
+        goto a54_done;
+
+    }
+
+    else if ((op1 & b11110) == b11010)
+    {
+        if ((op2 & b011) == b010)
+            result = armv7_read_arm_instr_sbfx(raw);
+
+        goto a54_done;
+
+    }
+
+    else if ((op1 & b11110) == b11100)
+    {
+        if ((op2 & b011) == b000)
+        {
+            if (rn == b1111)
+                result = armv7_read_arm_instr_bfc(raw);
+            else
+                result = armv7_read_arm_instr_bfi(raw);
+        }
+
+        goto a54_done;
+
+    }
+
+    else if ((op1 & b11110) == b11110)
+    {
+        if ((op2 & b011) == b010)
+            result = armv7_read_arm_instr_ubfx(raw);
+
+        goto a54_done;
+
+    }
+
+    else if (op1 == b11111 && op2 == b111 && cond == b1110)
+        result = armv7_read_arm_instr_ubfx(raw);
+
+ a54_done:
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
+*                                                                             *
+*  Description : Désassemble une instruction ARMv7 de données ou autre.       *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL en cas d'échec.            *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+static GArchInstruction *process_armv7_arm_packing_unpacking_saturation_and_reversal(uint32_t raw)
+{
+    GArchInstruction *result;               /* Instruction à retourner     */
+    uint32_t op1;                           /* Champ 'op1' à retrouver     */
+    uint32_t a;                             /* Champ 'a' à retrouver       */
+    uint32_t op2;                           /* Champ 'op2' à retrouver     */
+
+    /**
+     * Suit les directives de :
+     * § A5.4.3 Packing, unpacking, saturation, and reversal
+     */
+
+    result = NULL;
+
+    if ((raw & 0x0f800010) != 0x06800010)
+        return NULL;
+
+    op1 = (raw >> 20) & 0x7;
+    a = (raw >> 16) & 0xf;
+    op2 = (raw >> 5) & 0x7;
+
+    if ((op1 & b111) == b000)
+    {
+        if ((op2 & b001) == b000)
+        {
+            result = armv7_read_arm_instr_pkh(raw);
+            goto a543_done;
+        }
+        else if (op2 == b011)
+        {
+            if (a == b1111)
+            {
+                result = armv7_read_arm_instr_sxtb16(raw);
+                goto a543_done;
+            }
+            else
+            {
+                result = armv7_read_arm_instr_sxtab16(raw);
+                goto a543_done;
+            }
+        }
+        else if (op2 == b101)
+        {
+            result = armv7_read_arm_instr_sel(raw);
+            goto a543_done;
+        }
+    }
+
+    else if ((op1 & b110) == b010 && (op2 & b001) == b000)
+    {
+        result = armv7_read_arm_instr_ssat(raw);
+        goto a543_done;
+    }
+
+    else if (op1 == b010)
+    {
+        if (op2 == b001)
+        {
+            result = armv7_read_arm_instr_ssat16(raw);
+            goto a543_done;
+        }
+        else if (op2 == b011)
+        {
+            if (a == b1111)
+            {
+                result = armv7_read_arm_instr_sxtb(raw);
+                goto a543_done;
+            }
+            else
+            {
+                result = armv7_read_arm_instr_sxtab(raw);
+                goto a543_done;
+            }
+        }
+    }
+
+    else if (op1 == b011)
+    {
+        if (op2 == b001)
+        {
+            result = armv7_read_arm_instr_rev(raw);
+            goto a543_done;
+        }
+        else if (op2 == b011)
+        {
+            if (a == b1111)
+            {
+                result = armv7_read_arm_instr_sxth(raw);
+                goto a543_done;
+            }
+            else
+            {
+                result = armv7_read_arm_instr_sxtah(raw);
+                goto a543_done;
+            }
+        }
+        else if (op2 == b101)
+        {
+            result = armv7_read_arm_instr_rev16(raw);
+            goto a543_done;
+        }
+    }
+
+    else if (op1 == b100 && op2 == b011)
+    {
+        if (a == b1111)
+        {
+            result = armv7_read_arm_instr_uxtb16(raw);
+            goto a543_done;
+        }
+        else
+        {
+            result = armv7_read_arm_instr_uxtab16(raw);
+            goto a543_done;
+        }
+    }
+
+    else if ((op1 & b110) == b110 && (op2 & b001) == b000)
+    {
+        result = armv7_read_arm_instr_usat(raw);
+        goto a543_done;
+    }
+
+    else if (op1 == b110)
+    {
+        if (op2 == b001)
+        {
+            result = armv7_read_arm_instr_usat16(raw);
+            goto a543_done;
+        }
+        else if (op2 == b011)
+        {
+            if (a == b1111)
+            {
+                result = armv7_read_arm_instr_uxtb(raw);
+                goto a543_done;
+            }
+            else
+            {
+                result = armv7_read_arm_instr_uxtab(raw);
+                goto a543_done;
+            }
+        }
+    }
+
+    else if (op1 == b111)
+    {
+        if (op2 == b001)
+        {
+            result = armv7_read_arm_instr_rbit(raw);
+            goto a543_done;
+        }
+        else if (op2 == b011)
+        {
+            if (a == b1111)
+            {
+                result = armv7_read_arm_instr_uxth(raw);
+                goto a543_done;
+            }
+            else
+            {
+                result = armv7_read_arm_instr_uxtah(raw);
+                goto a543_done;
+            }
+        }
+        else if (op2 == b101)
+        {
+            result = armv7_read_arm_instr_revsh(raw);
+            goto a543_done;
+        }
+    }
+
+ a543_done:
+
+    return result;
+
+}
+
+
+
+
+
+
+
+
+
+
 /******************************************************************************
 *                                                                             *
 *  Paramètres  : raw = donnée brute de 32 bits à désassembler.                *
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
index 5142648..719d3c3 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
@@ -1,19 +1,50 @@
 #ifndef arm_def_tmp_h
 #define arm_def_tmp_h
+#define armv7_read_arm_instr_bfc(r) NULL
+#define armv7_read_arm_instr_bfi(r) NULL
 #define armv7_read_arm_instr_ldmda_ldmfa(r) NULL
 #define armv7_read_arm_instr_ldmdb_ldmea(r) NULL
 #define armv7_read_arm_instr_ldm_exception_return(r) NULL
 #define armv7_read_arm_instr_ldmib_ldmed(r) NULL
 #define armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(r) NULL
 #define armv7_read_arm_instr_ldm_user_registers(r) NULL
-#define armv7_read_arm_instr_lsr_immediate(r) NULL
+#define armv7_read_arm_instr_ldrb_literal(r) NULL
+#define armv7_read_arm_instr_ldrbt(r) NULL
+#define armv7_read_arm_instr_ldr_register(r) NULL
+#define armv7_read_arm_instr_ldrt(r) NULL
+#define armv7_read_arm_instr_pkh(r) NULL
+#define armv7_read_arm_instr_rbit(r) NULL
+#define armv7_read_arm_instr_rev(r) NULL
+#define armv7_read_arm_instr_rev16(r) NULL
+#define armv7_read_arm_instr_revsh(r) NULL
 #define armv7_read_arm_instr_ror_immediate(r) NULL
 #define armv7_read_arm_instr_rrx(r) NULL
+#define armv7_read_arm_instr_sbfx(r) NULL
+#define armv7_read_arm_instr_sel(r) NULL
+#define armv7_read_arm_instr_ssat(r) NULL
+#define armv7_read_arm_instr_ssat16(r) NULL
 #define armv7_read_arm_instr_stmda_stmed(r) NULL
 #define armv7_read_arm_instr_stmdb_stmfd(r) NULL
 #define armv7_read_arm_instr_stmib_stmfa(r) NULL
 #define armv7_read_arm_instr_stm_stmia_stmea(r) NULL
 #define armv7_read_arm_instr_stm_user_registers(r) NULL
+#define armv7_read_arm_instr_strbt(r) NULL
 #define armv7_read_arm_instr_str_register(r) NULL
 #define armv7_read_arm_instr_strt(r) NULL
+#define armv7_read_arm_instr_sxtab(r) NULL
+#define armv7_read_arm_instr_sxtab16(r) NULL
+#define armv7_read_arm_instr_sxtah(r) NULL
+#define armv7_read_arm_instr_sxtb(r) NULL
+#define armv7_read_arm_instr_sxtb16(r) NULL
+#define armv7_read_arm_instr_sxth(r) NULL
+#define armv7_read_arm_instr_ubfx(r) NULL
+#define armv7_read_arm_instr_usad8(r) NULL
+#define armv7_read_arm_instr_usada8(r) NULL
+#define armv7_read_arm_instr_usat(r) NULL
+#define armv7_read_arm_instr_usat16(r) NULL
+#define armv7_read_arm_instr_uxtab(r) NULL
+#define armv7_read_arm_instr_uxtab16(r) NULL
+#define armv7_read_arm_instr_uxtah(r) NULL
+#define armv7_read_arm_instr_uxtb16(r) NULL
+#define armv7_read_arm_instr_uxth(r) NULL
 #endif
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
index 3d3aa3a..8e8572d 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
@@ -10,7 +10,6 @@
 #define armv7_read_thumb_16_instr_ldrsb_register(r) NULL
 #define armv7_read_thumb_16_instr_ldrsh_register(r) NULL
 #define armv7_read_thumb_16_instr_lsl_register(r) NULL
-#define armv7_read_thumb_16_instr_lsr_immediate(r) NULL
 #define armv7_read_thumb_16_instr_lsr_register(r) NULL
 #define armv7_read_thumb_16_instr_rev(r) NULL
 #define armv7_read_thumb_16_instr_rev16(r) NULL
diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am
index 6678f0e..6207906 100644
--- a/src/arch/arm/v7/opdefs/Makefile.am
+++ b/src/arch/arm/v7/opdefs/Makefile.am
@@ -54,8 +54,10 @@ ARMV7_DEFS = 							\
 	ldr_A8864.d							\
 	ldr_A8865.d							\
 	ldrb_A8867.d						\
+	ldrb_A8868.d						\
 	ldrb_A8870.d						\
 	lsl_A8894.d							\
+	lsr_A8896.d							\
 	mla_A88100.d						\
 	mls_A88101.d						\
 	mov_A88102.d						\
@@ -82,6 +84,7 @@ ARMV7_DEFS = 							\
 	str_A88203.d						\
 	str_A88204.d						\
 	strb_A88206.d						\
+	strb_A88207.d						\
 	strb_A88208.d						\
 	sub_A88221.d						\
 	sub_A88222.d						\
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8868.d b/src/arch/arm/v7/opdefs/ldrb_A8868.d
new file mode 100644
index 0000000..fdf3049
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/ldrb_A8868.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDRB (immediate, ARM)
+
+@encoding(A11) {
+
+    @word cond(4) 0 1 0 1 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        access = MakeMemoryAccess(Rgn, imm32, U, W)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
+
+@encoding(A12) {
+
+    @word cond(4) 0 1 0 0 U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <base> <offset>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        base = MakeMemoryNotIndexed(Rgn, W)
+        offset = MakeAccessOffset(U, imm32)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/ldrb_A8870.d b/src/arch/arm/v7/opdefs/ldrb_A8870.d
index 0de0af2..868b1c9 100644
--- a/src/arch/arm/v7/opdefs/ldrb_A8870.d
+++ b/src/arch/arm/v7/opdefs/ldrb_A8870.d
@@ -25,7 +25,7 @@
 
 @encoding(t1) {
 
-    @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3)
+    @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3)
 
     @syntax <Rgt> <access>
 
diff --git a/src/arch/arm/v7/opdefs/lsr_A8896.d b/src/arch/arm/v7/opdefs/lsr_A8896.d
new file mode 100644
index 0000000..8e3f274
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/lsr_A8896.d
@@ -0,0 +1,98 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2015 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LSR (immediate)
+
+@encoding(t1) {
+
+    @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3)
+
+    @syntax <Rgd> <Rgm> <shift>
+
+    @conv {
+
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(1, imm5)
+
+    }
+
+    @rules {
+
+        if (imm5 == '00000') ; see MOV (register, Thumb)
+        //if (imm5 == '00000') ; see MOV (register)
+
+    }
+
+}
+
+@encoding(T2) {
+
+    @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4)
+
+    @syntax {s} <Rgd> <Rgm> <shift>
+
+    @conv {
+
+        S = SetFlags(S)
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(1, imm3:imm2)
+
+    }
+
+    @rules {
+
+        if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb)
+        //if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb)
+        //if (imm3:imm2) == '00000' then SEE MOV (register);
+        //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(A1) {
+
+    @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4)
+
+    @syntax {S} {c} <Rgd> <Rgm> <shift>
+
+    @conv {
+
+        S = SetFlags(S)
+        c = Condition(cond)
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(1, imm5)
+
+    }
+
+    @rules {
+
+        //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
+        //if imm5 == '00000' then SEE MOV (register);
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/strb_A88207.d b/src/arch/arm/v7/opdefs/strb_A88207.d
new file mode 100644
index 0000000..b57dbf7
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/strb_A88207.d
@@ -0,0 +1,81 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title STRB (immediate, ARM)
+
+@encoding(A11) {
+
+    @word cond(4) 0 1 0 1 U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        access = MakeMemoryAccess(Rgn, imm32, U, W)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
+
+@encoding(A12) {
+
+    @word cond(4) 0 1 0 0 U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12)
+
+    @syntax <Rgt> <base> <offset>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        imm32 = ZeroExtend(imm12, 12, 32);
+        base = MakeMemoryNotIndexed(Rgn, W)
+        offset = MakeAccessOffset(U, imm32)
+
+    }
+
+    @rules {
+
+        //if Rt == '1111' && P == '1' && U == '0' && W == '0' then SEE PLD, PLDW (immediate);
+        //if Rn == '1111' then SEE LDRB (literal);
+        //if P == '1' && U == '1' && W == '0' then SEE LDRBT;
+        //if P == '0' && W == '0' then UNDEFINED;
+        //if t == 13 || (t == 15 && W == '1') || (wback && n == t) then UNPREDICTABLE;
+        if (Rt == '1111'); chk_call DefineAsReturn(1)
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/uxtb_A88274.d b/src/arch/arm/v7/opdefs/uxtb_A88274.d
index 97b17de..8917144 100644
--- a/src/arch/arm/v7/opdefs/uxtb_A88274.d
+++ b/src/arch/arm/v7/opdefs/uxtb_A88274.d
@@ -42,7 +42,7 @@
 
     @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4)
 
-    @syntax <Rd> <Rm> <?rotation>
+    @syntax "uxtb.W" <Rd> <Rm> <?rotation>
 
     @conv {