Supported new ARMv7 instructions.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@437 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

16 files changed, 526 insertions, 18 deletions

diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h
index 4ef7087..fee5aea 100644
--- a/src/arch/arm/v7/helpers.h
+++ b/src/arch/arm/v7/helpers.h
@@ -88,6 +88,17 @@
 
 
 
+#define DecodeImmShiftValue(imm5)                                                       \
+    ({                                                                                  \
+        GArchOperand *__result;                                                         \
+        uint32_t __shift_n;                                                             \
+        if (!armv7_decode_imm_shift(0, imm5, (SRType []) { 0 }, &__shift_n))            \
+            __result = NULL;                                                            \
+        else                                                                            \
+            __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n);   \
+        __result;                                                                       \
+    })
+
 #define DecodeImmShift(type, imm5)                                                  \
     ({                                                                              \
         GArchOperand *__result;                                                     \
@@ -156,16 +167,27 @@ return shift_t;
     g_armv7_offset_operand_new(add, off)
 
 
+#define MakeShiftedMemoryAccess(base, off, shift, wr)                               \
+    g_armv7_maccess_operand_new(base, off, shift, wr)
+
+
+#define _MakeMemoryAccess(base, off, wr)                                            \
+    MakeShiftedMemoryAccess(base, off, NULL, wr)
+
+
 #define MakeMemoryAccess(base, off, add, wr)                                        \
     ({                                                                              \
         GArchOperand *__off;                                                        \
         __off = MakeAccessOffset(add, off);                                         \
-        g_armv7_maccess_operand_new(base, __off, wr);                               \
+        _MakeMemoryAccess(base, __off, wr);                                         \
     })
 
 
 #define MakeMemoryNotIndexed(base, wr)                                              \
-    g_armv7_maccess_operand_new(base, NULL, wr)
+    _MakeMemoryAccess(base, NULL, wr)
+
+
+
 
 
 
diff --git a/src/arch/arm/v7/opcodes/Makefile.am b/src/arch/arm/v7/opcodes/Makefile.am
index 30d0e16..be437b9 100644
--- a/src/arch/arm/v7/opcodes/Makefile.am
+++ b/src/arch/arm/v7/opcodes/Makefile.am
@@ -6,13 +6,16 @@ libarcharmv7opcodes_la_SOURCES = 		\
 	arm_adc.c		\
 	arm_add.c		\
 	arm_and.c		\
+	arm_b.c			\
 	arm_bic.c		\
 	arm_bl.c		\
 	arm_bx.c		\
+	arm_cbnz.c		\
 	arm_cmn.c		\
 	arm_cmp.c		\
 	arm_eor.c		\
 	arm_ldr.c		\
+	arm_lsl.c		\
 	arm_mla.c		\
 	arm_mls.c		\
 	arm_mov.c		\
@@ -36,13 +39,16 @@ libarcharmv7opcodes_la_SOURCES = 		\
 	thumb_16_adc.c		\
 	thumb_16_add.c		\
 	thumb_16_and.c		\
+	thumb_16_b.c		\
 	thumb_16_bic.c		\
 	thumb_16_bl.c		\
 	thumb_16_bx.c		\
+	thumb_16_cbnz.c		\
 	thumb_16_cmn.c		\
 	thumb_16_cmp.c		\
 	thumb_16_eor.c		\
 	thumb_16_ldr.c		\
+	thumb_16_lsl.c		\
 	thumb_16_mla.c		\
 	thumb_16_mls.c		\
 	thumb_16_mov.c		\
@@ -66,13 +72,16 @@ libarcharmv7opcodes_la_SOURCES = 		\
 	thumb_32_adc.c		\
 	thumb_32_add.c		\
 	thumb_32_and.c		\
+	thumb_32_b.c		\
 	thumb_32_bic.c		\
 	thumb_32_bl.c		\
 	thumb_32_bx.c		\
+	thumb_32_cbnz.c		\
 	thumb_32_cmn.c		\
 	thumb_32_cmp.c		\
 	thumb_32_eor.c		\
 	thumb_32_ldr.c		\
+	thumb_32_lsl.c		\
 	thumb_32_mla.c		\
 	thumb_32_mls.c		\
 	thumb_32_mov.c		\
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
index 82590a4..1cd3e24 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
@@ -2,14 +2,12 @@
 #define arm_def_tmp_h
 #define armv7_read_arm_instr_adr(r) NULL
 #define armv7_read_arm_instr_asr_immediate(r) NULL
-#define armv7_read_arm_instr_b(r) NULL
 #define armv7_read_arm_instr_ldmda_ldmfa(r) NULL
 #define armv7_read_arm_instr_ldmdb_ldmea(r) NULL
 #define armv7_read_arm_instr_ldm_exception_return(r) NULL
 #define armv7_read_arm_instr_ldmib_ldmed(r) NULL
 #define armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(r) NULL
 #define armv7_read_arm_instr_ldm_user_registers(r) NULL
-#define armv7_read_arm_instr_lsl_immediate(r) NULL
 #define armv7_read_arm_instr_lsr_immediate(r) NULL
 #define armv7_read_arm_instr_movt(r) NULL
 #define armv7_read_arm_instr_pop_arm(r) NULL
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
index 4620f83..f9ef7d9 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
@@ -2,18 +2,14 @@
 #define thumb_16_def_tmp_h
 #define armv7_read_thumb_16_instr_adc_register(r) NULL
 #define armv7_read_thumb_16_instr_add_immediate_thumb(r) NULL
-#define armv7_read_thumb_16_instr_add_register_thumb(r) NULL
 #define armv7_read_thumb_16_instr_add_sp_plus_immediate(r) NULL
 #define armv7_read_thumb_16_instr_adr(r) NULL
 #define armv7_read_thumb_16_instr_and_register(r) NULL
 #define armv7_read_thumb_16_instr_asr_immediate(r) NULL
 #define armv7_read_thumb_16_instr_asr_register(r) NULL
-#define armv7_read_thumb_16_instr_b(r) NULL
 #define armv7_read_thumb_16_instr_bic_register(r) NULL
 #define armv7_read_thumb_16_instr_bkpt(r) NULL
 #define armv7_read_thumb_16_instr_blx_register(r) NULL
-#define armv7_read_thumb_16_instr_bx(r) NULL
-#define armv7_read_thumb_16_instr_cbnz_cbz(r) NULL
 #define armv7_read_thumb_16_instr_cmn_register(r) NULL
 #define armv7_read_thumb_16_instr_cmp_immediate(r) NULL
 #define armv7_read_thumb_16_instr_cmp_register(r) NULL
@@ -25,10 +21,8 @@
 #define armv7_read_thumb_16_instr_ldrb_register(r) NULL
 #define armv7_read_thumb_16_instr_ldrh_immediate_thumb(r) NULL
 #define armv7_read_thumb_16_instr_ldrh_register(r) NULL
-#define armv7_read_thumb_16_instr_ldr_register_thumb(r) NULL
 #define armv7_read_thumb_16_instr_ldrsb_register(r) NULL
 #define armv7_read_thumb_16_instr_ldrsh_register(r) NULL
-#define armv7_read_thumb_16_instr_lsl_immediate(r) NULL
 #define armv7_read_thumb_16_instr_lsl_register(r) NULL
 #define armv7_read_thumb_16_instr_lsr_immediate(r) NULL
 #define armv7_read_thumb_16_instr_lsr_register(r) NULL
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
index 999cd0d..966d6a2 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
@@ -1,10 +1,8 @@
 #ifndef thumb_32_def_tmp_h
 #define thumb_32_def_tmp_h
 #define armv7_read_thumb_32_instr_add_immediate_thumb(r) NULL
-#define armv7_read_thumb_32_instr_add_register_thumb(r) NULL
 #define armv7_read_thumb_32_instr_adr(r) NULL
 #define armv7_read_thumb_32_instr_asr_register(r) NULL
-#define armv7_read_thumb_32_instr_b(r) NULL
 #define armv7_read_thumb_32_instr_bfc(r) NULL
 #define armv7_read_thumb_32_instr_bfi(r) NULL
 #define armv7_read_thumb_32_instr_b_mrs(r) NULL
@@ -22,7 +20,6 @@
 #define armv7_read_thumb_32_instr_isb(r) NULL
 #define armv7_read_thumb_32_instr_ldmdb_ldmea(r) NULL
 #define armv7_read_thumb_32_instr_ldm_ldmia_ldmfd_thumb(r) NULL
-#define armv7_read_thumb_32_instr_ldr_register_thumb(r) NULL
 #define armv7_read_thumb_32_instr_ldrt(r) NULL
 #define armv7_read_thumb_32_instr_lsl_register(r) NULL
 #define armv7_read_thumb_32_instr_lsr_register(r) NULL
diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am
index 348cbf6..948c9da 100644
--- a/src/arch/arm/v7/opdefs/Makefile.am
+++ b/src/arch/arm/v7/opdefs/Makefile.am
@@ -25,13 +25,16 @@ ARMV7_DEFS = 							\
 	adc_A881.d							\
 	adc_A882.d							\
 	add_A885.d							\
+	add_A886.d							\
 	add_A887.d							\
 	and_A8813.d							\
 	and_A8814.d							\
+	b_A8818.d							\
 	bic_A8821.d							\
 	bic_A8822.d							\
 	bl_A8825.d							\
 	bx_A8827.d							\
+	cbnz_A8829.d						\
 	cmn_A8834.d							\
 	cmn_A8835.d							\
 	cmp_A8837.d							\
@@ -40,6 +43,8 @@ ARMV7_DEFS = 							\
 	eor_A8847.d							\
 	ldr_A8862.d							\
 	ldr_A8864.d							\
+	ldr_A8865.d							\
+	lsl_A8894.d							\
 	mla_A88100.d						\
 	mls_A88101.d						\
 	mov_A88102.d						\
diff --git a/src/arch/arm/v7/opdefs/add_A886.d b/src/arch/arm/v7/opdefs/add_A886.d
new file mode 100644
index 0000000..fd8f7a4
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/add_A886.d
@@ -0,0 +1,90 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title ADD (register, Thumb)
+
+@encoding(t1) {
+
+    @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3)
+
+    @syntax <Rd> <Rn> <Rm>
+
+    @conv {
+
+        Rd = Register(Rd)
+        Rn = Register(Rn)
+        Rm = Register(Rm)
+
+    }
+
+}
+
+@encoding(t2) {
+
+    @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3)
+
+    @syntax <Rdn> <Rm>
+
+    @conv {
+
+        Rdn = Register(DN:Rdn)
+        Rm = Register(Rm)
+
+    }
+
+    @rules {
+
+        //if (DN:Rdn) == '1101' || Rm == '1101' then SEE ADD (SP plus register);
+        //if n == 15 && m == 15 then UNPREDICTABLE;
+        //if d == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(T3) {
+
+    @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4)
+
+    @syntax {S} ".W" <Rd> <Rn> <Rm> <?shift>
+
+    @conv {
+
+        S = SetFlags(S)
+        Rd = Register(Rd)
+        Rn = Register(Rn)
+        Rm = Register(Rm)
+        shift = DecodeImmShift(type, imm3:imm2)
+
+    }
+
+    @rules {
+
+        //if Rd == '1111' && S == '1' then SEE CMN (register);
+        //if Rn == '1101' then SEE ADD (SP plus register);
+        //if d == 13 || (d == 15 && S == '0') || n == 15 || m IN {13,15} then UNPREDICTABLE;
+
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/b_A8818.d b/src/arch/arm/v7/opdefs/b_A8818.d
new file mode 100644
index 0000000..50600d4
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/b_A8818.d
@@ -0,0 +1,125 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title B
+
+@encoding(t1) {
+
+    @half 1 1 0 1 cond(4) top(1) imm8(7)
+
+    @syntax {c} <label>
+
+    @conv {
+
+        c = Condition(cond)
+        label = SignExtend(top:imm8:'0', top, 32)
+
+    }
+
+    @rules {
+
+        //if cond == '1110' then UNDEFINED;
+        //if cond == '1111' then SEE SVC;
+
+    }
+
+}
+
+@encoding(t2) {
+
+    @half 1 1 1 0 0 top(1) imm11(10)
+
+    @syntax <label>
+
+    @conv {
+
+        label = SignExtend(top:imm11:'0', top, 32)
+
+    }
+
+    @rules {
+
+        //if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(T3) {
+
+    @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11)
+
+    @syntax {c} ".W" <label>
+
+    @conv {
+
+        c = Condition(cond)
+        label = SignExtend(S:J2:J1:imm6:imm11:'0', S, 32)
+
+    }
+
+    @rules {
+
+        //if cond<3:1> == '111' then SEE "Related encodings";
+        //if InITBlock() then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(T4) {
+
+    @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11)
+
+    @syntax "b.W" <label>
+
+    @conv {
+
+        I1 = NOT(J1 EOR S)
+        I2 = NOT(J2 EOR S)
+        label = SignExtend(S:I1:I2:imm10:imm11:'0', S, 32)
+
+    }
+
+    @rules {
+
+        //if InITBlock() && !LastInITBlock() then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(A1) {
+
+    @word cond(4) 1 0 1 0 top(1) imm24(23)
+
+    @syntax {c} <label>
+
+    @conv {
+
+        c = Condition(cond)
+        label = SignExtend(top:imm24:'00', top, 32)
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/bx_A8827.d b/src/arch/arm/v7/opdefs/bx_A8827.d
index 5acf969..45ccfd5 100644
--- a/src/arch/arm/v7/opdefs/bx_A8827.d
+++ b/src/arch/arm/v7/opdefs/bx_A8827.d
@@ -23,7 +23,7 @@
 
 @title BX
 
-@encoding(T1) {
+@encoding(t1) {
 
 
     @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0
diff --git a/src/arch/arm/v7/opdefs/cbnz_A8829.d b/src/arch/arm/v7/opdefs/cbnz_A8829.d
new file mode 100644
index 0000000..9ecf141
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/cbnz_A8829.d
@@ -0,0 +1,54 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title CBNZ, CBZ
+
+@encoding(t11) {
+
+    @half 1 0 1 1 1 0 i(1) 1 imm5(5) Rn(3)
+
+    @syntax <Rn> <label>
+
+    @conv {
+
+        Rn = Register(Rn)
+        label = ZeroExtend(i:imm5:'0', 7, 32);
+
+    }
+
+}
+
+@encoding(t12) {
+
+    @half 1 0 1 1 0 0 i(1) 1 imm5(5) Rn(3)
+
+    @syntax "cbz" <Rn> <label>
+
+    @conv {
+
+        Rn = Register(Rn)
+        label = ZeroExtend(i:imm5:'0', 7, 32);
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/ldr_A8865.d b/src/arch/arm/v7/opdefs/ldr_A8865.d
new file mode 100644
index 0000000..11a8932
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/ldr_A8865.d
@@ -0,0 +1,73 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LDR (register, Thumb)
+
+@encoding(t1) {
+
+    @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3)
+
+    @syntax <Rgt> <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        Rgm = Register(Rm)
+        access = _MakeMemoryAccess(Rgn, Rgm, 0)
+
+    }
+
+    @rules {
+
+        //if CurrentInstrSet() == InstrSet_ThumbEE then SEE "Modified operation in ThumbEE";
+
+    }
+
+}
+
+@encoding(T2) {
+
+    @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4)
+
+    @syntax "ldr.W" <Rgt>, <access>
+
+    @conv {
+
+        Rgt = Register(Rt)
+        Rgn = Register(Rn)
+        Rgm = Register(Rm)
+        shift = DecodeImmShift(0, imm2)
+        access = MakeShiftedMemoryAccess(Rgn, Rgm, shift, 0)
+
+    }
+
+    @rules {
+
+        //if Rn == '1111' then SEE LDR (literal);
+        //if m IN {13,15} then UNPREDICTABLE;
+        //if t == 15 && InITBlock() && !LastInITBlock() then UNPREDICTABLE;
+
+    }
+
+}
diff --git a/src/arch/arm/v7/opdefs/lsl_A8894.d b/src/arch/arm/v7/opdefs/lsl_A8894.d
new file mode 100644
index 0000000..59ac3e8
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/lsl_A8894.d
@@ -0,0 +1,98 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Foobar.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title LSL (immediate)
+
+@encoding(t1) {
+
+    @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3)
+
+    @syntax <Rgd> <Rgm> <shiftv>
+
+    @conv {
+
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shiftv = DecodeImmShiftValue(imm5)
+
+    }
+
+    @rules {
+
+        if (imm5 == '00000') ; see MOV (register, Thumb)
+        //if (imm5 == '00000') ; see MOV (register)
+
+    }
+
+}
+
+@encoding(T2) {
+
+    @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4)
+
+    @syntax {s} <Rgd> <Rgm> <shiftv>
+
+    @conv {
+
+        S = SetFlags(S)
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shiftv = DecodeImmShiftValue(imm3:imm2)
+
+    }
+
+    @rules {
+
+        if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb)
+        //if ((imm3 == '000') && (imm2 == '00')) ; see MOV (register, Thumb)
+        //if (imm3:imm2) == '00000' then SEE MOV (register);
+        //if d IN {13,15} || m IN {13,15} then UNPREDICTABLE;
+
+    }
+
+}
+
+@encoding(A1) {
+
+    @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4)
+
+    @syntax {S} {c} <Rgd> <Rgm> <shiftv>
+
+    @conv {
+
+        S = SetFlags(S)
+        c = Condition(cond)
+        Rgd = Register(Rd)
+        Rgm = Register(Rm)
+        shiftv = DecodeImmShiftValue(imm5)
+
+    }
+
+    @rules {
+
+        //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
+        //if imm5 == '00000' then SEE MOV (register);
+
+    }
+
+}
diff --git a/src/arch/arm/v7/operands/maccess.c b/src/arch/arm/v7/operands/maccess.c
index 72b63d8..56ad0a3 100644
--- a/src/arch/arm/v7/operands/maccess.c
+++ b/src/arch/arm/v7/operands/maccess.c
@@ -35,6 +35,7 @@ struct _GArmV7MAccessOperand
 
     GArchOperand *base;                     /* Base de l'accès en mémoire  */
     GArchOperand *offset;                   /* Décallage pour l'adresse    */
+    GArchOperand *shift;                    /* Décallage pour le décallage */
     bool write_back;                        /* Mise à jour de la base      */
 
 };
@@ -134,6 +135,9 @@ static void g_armv7_maccess_operand_dispose(GArmV7MAccessOperand *operand)
     if (operand->offset != NULL)
         g_object_unref(G_OBJECT(operand->offset));
 
+    if (operand->shift != NULL)
+        g_object_unref(G_OBJECT(operand->shift));
+
     G_OBJECT_CLASS(g_armv7_maccess_operand_parent_class)->dispose(G_OBJECT(operand));
 
 }
@@ -162,6 +166,7 @@ static void g_armv7_maccess_operand_finalize(GArmV7MAccessOperand *operand)
 *                                                                             *
 *  Paramètres  : base   = représente le registre de la base d'accès.          *
 *                offset = détermine le décallage entre l'adresse et la base.  *
+*                shift  = opération de décallage pour jouer sur le décallage. *
 *                writeb = indique une mise à jour de la base après usage.     *
 *                                                                             *
 *  Description : Crée un accès à la mémoire depuis une base et un décallage.  *
@@ -172,7 +177,7 @@ static void g_armv7_maccess_operand_finalize(GArmV7MAccessOperand *operand)
 *                                                                             *
 ******************************************************************************/
 
-GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, bool writeb)
+GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool writeb)
 {
     GArmV7MAccessOperand *result;             /* Structure à retourner       */
 
@@ -180,6 +185,7 @@ GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offs
 
     result->base = base;
     result->offset = offset;
+    result->shift = shift;
     result->write_back = writeb;
 
     return G_ARCH_OPERAND(result);
@@ -216,6 +222,15 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G
 
     }
 
+    if (operand->shift != NULL)
+    {
+        g_buffer_line_insert_text(line, BLC_ASSEMBLY, ",", 1, RTT_PUNCT);
+        g_buffer_line_insert_text(line, BLC_ASSEMBLY, " ", 1, RTT_RAW);
+
+        g_arch_operand_print(operand->shift, line, syntax);
+
+    }
+
     g_buffer_line_insert_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK);
 
     if (operand->write_back)
@@ -266,6 +281,25 @@ GArchOperand *g_armv7_maccess_operand_get_offset(const GArmV7MAccessOperand *ope
 *                                                                             *
 *  Paramètres  : operand = opérande à consulter.                              *
 *                                                                             *
+*  Description : Founit le décallage d'un décallage pour un accès mémoire.    *
+*                                                                             *
+*  Retour      : Opérande en place.                                           *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+GArchOperand *g_armv7_maccess_operand_get_shift(const GArmV7MAccessOperand *operand)
+{
+    return operand->shift;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : operand = opérande à consulter.                              *
+*                                                                             *
 *  Description : Indique si la base est mise à jour après usage.              *
 *                                                                             *
 *  Retour      : Statut des opérations menées.                                *
diff --git a/src/arch/arm/v7/operands/maccess.h b/src/arch/arm/v7/operands/maccess.h
index 9198cfa..8684891 100644
--- a/src/arch/arm/v7/operands/maccess.h
+++ b/src/arch/arm/v7/operands/maccess.h
@@ -53,7 +53,7 @@ typedef struct _GArmV7MAccessOperandClass GArmV7MAccessOperandClass;
 GType g_armv7_maccess_operand_get_type(void);
 
 /* Crée un accès à la mémoire depuis une base et un décallage. */
-GArchOperand *g_armv7_maccess_operand_new(GArchOperand *, GArchOperand *, bool);
+GArchOperand *g_armv7_maccess_operand_new(GArchOperand *, GArchOperand *, GArchOperand *, bool);
 
 /* Founit la base d'un accès à la mémoire. */
 GArchOperand *g_armv7_maccess_operand_get_base(const GArmV7MAccessOperand *);
@@ -61,6 +61,9 @@ GArchOperand *g_armv7_maccess_operand_get_base(const GArmV7MAccessOperand *);
 /* Founit le décallage d'un accès à la mémoire depuis la base. */
 GArchOperand *g_armv7_maccess_operand_get_offset(const GArmV7MAccessOperand *);
 
+/* Founit le décallage d'un décallage pour un accès mémoire. */
+GArchOperand *g_armv7_maccess_operand_get_shift(const GArmV7MAccessOperand *);
+
 /* Indique si la base est mise à jour après usage. */
 bool g_armv7_maccess_operand_has_to_write_back(const GArmV7MAccessOperand *);
 
diff --git a/src/arch/arm/v7/thumb_16.c b/src/arch/arm/v7/thumb_16.c
index 9365708..c722f30 100644
--- a/src/arch/arm/v7/thumb_16.c
+++ b/src/arch/arm/v7/thumb_16.c
@@ -95,10 +95,10 @@ GArchInstruction *process_armv7_thumb_16_instruction_set_encoding(uint16_t raw)
         result = armv7_read_thumb_16_instr_ldr_literal(raw);
 
     else if ((opcode & b111100) == b010100)
-        result = armv7_read_thumb_16_instr_ldr_literal(raw);
+        result = process_armv7_thumb_16_load_store_single_data_item(raw);
 
     else if ((opcode & b111000) == b011000)
-        result = armv7_read_thumb_16_instr_ldr_literal(raw);
+        result = process_armv7_thumb_16_load_store_single_data_item(raw);
 
     else if ((opcode & b111000) == b100000)
         result = process_armv7_thumb_16_load_store_single_data_item(raw);
diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c
index 00b3171..04d760b 100644
--- a/src/arch/arm/v7/thumb_32.c
+++ b/src/arch/arm/v7/thumb_32.c
@@ -521,6 +521,12 @@ static GArchInstruction *process_armv7_thumb_32_branches_and_miscellaneous_contr
     else if (op1 == b010 && op == b1111111)
         result = armv7_read_thumb_32_instr_udf(raw);
 
+    else if ((op1 & b101) == b100)
+        result = armv7_read_thumb_32_instr_bl_blx_immediate(raw);
+
+    else if ((op1 & b101) == b101)
+        result = armv7_read_thumb_32_instr_bl_blx_immediate(raw);
+
     return result;
 
 }