diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2008-10-26 23:37:51 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2008-10-26 23:37:51 (GMT) |
commit | 197933fdf469ab9b8897b33c51809c128f1e3c03 (patch) | |
tree | 104d91be1a69d80eb4b59b247e4b719531bc7492 /src/arch/x86/op_add.c | |
parent | ac438e8ad47f267c9eb6f462eb5a7e2b5c017f26 (diff) |
Completed support of the 0x81 and 0xc1 opcodes.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@37 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/x86/op_add.c')
-rw-r--r-- | src/arch/x86/op_add.c | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/src/arch/x86/op_add.c b/src/arch/x86/op_add.c index f42c8f9..42e8d3b 100644 --- a/src/arch/x86/op_add.c +++ b/src/arch/x86/op_add.c @@ -76,7 +76,7 @@ asm_x86_instr *x86_read_instr_add_imm8_to_rm1632(const uint8_t *data, off_t *pos * offset = adresse virtuelle de l'instruction. * * proc = architecture ciblée par le désassemblage. * * * -* Description : Décode une instruction de type 'add' (16 ou 32 bits). * +* Description : Décode une instruction de type 'add' (8 bits). * * * * Retour : Instruction mise en place ou NULL. * * * @@ -84,18 +84,15 @@ asm_x86_instr *x86_read_instr_add_imm8_to_rm1632(const uint8_t *data, off_t *pos * * ******************************************************************************/ -asm_x86_instr *x86_read_instr_add_imm1632_to_rm1632(const uint8_t *data, off_t *pos, off_t len, uint64_t offset, const asm_x86_processor *proc) +asm_x86_instr *x86_read_instr_add_rm8_r8(const uint8_t *data, off_t *pos, off_t len, uint64_t offset, const asm_x86_processor *proc) { asm_x86_instr *result; /* Instruction à retourner */ - AsmOperandSize oprsize; /* Taille des opérandes */ result = (asm_x86_instr *)calloc(1, sizeof(asm_x86_instr)); - oprsize = switch_x86_operand_size_if_needed(proc, data, pos); - ASM_INSTRUCTION(result)->opcode = data[(*pos)++]; - if (!x86_read_two_operands(result, data, pos, len, X86_OTP_RM1632, X86_OTP_IMM1632, oprsize)) + if (!x86_read_two_operands(result, data, pos, len, X86_OTP_RM8, X86_OTP_R8)) { free(result); return NULL; @@ -114,7 +111,7 @@ asm_x86_instr *x86_read_instr_add_imm1632_to_rm1632(const uint8_t *data, off_t * * offset = adresse virtuelle de l'instruction. * * proc = architecture ciblée par le désassemblage. * * * -* Description : Décode une instruction de type 'add' (8 bits). * +* Description : Décode une instruction de type 'add' (16 ou 32 bits). * * * * Retour : Instruction mise en place ou NULL. * * * @@ -122,15 +119,18 @@ asm_x86_instr *x86_read_instr_add_imm1632_to_rm1632(const uint8_t *data, off_t * * * ******************************************************************************/ -asm_x86_instr *x86_read_instr_add_rm8_r8(const uint8_t *data, off_t *pos, off_t len, uint64_t offset, const asm_x86_processor *proc) +asm_x86_instr *x86_read_instr_add_rm1632_imm1632(const uint8_t *data, off_t *pos, off_t len, uint64_t offset, const asm_x86_processor *proc) { asm_x86_instr *result; /* Instruction à retourner */ + AsmOperandSize oprsize; /* Taille des opérandes */ result = (asm_x86_instr *)calloc(1, sizeof(asm_x86_instr)); + oprsize = switch_x86_operand_size_if_needed(proc, data, pos); + ASM_INSTRUCTION(result)->opcode = data[(*pos)++]; - if (!x86_read_two_operands(result, data, pos, len, X86_OTP_RM8, X86_OTP_R8)) + if (!x86_read_two_operands(result, data, pos, len, X86_OTP_RM1632, X86_OTP_IMM1632, oprsize)) { free(result); return NULL; |