Supported a few extra instructions (inc/dec rm8/16/32).

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@123 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

1 files changed, 12 insertions, 0 deletions

diff --git a/src/arch/x86/opcodes.h b/src/arch/x86/opcodes.h
index 93e4d5c..9ef2880 100644
--- a/src/arch/x86/opcodes.h
+++ b/src/arch/x86/opcodes.h
@@ -105,6 +105,12 @@ GArchInstruction *x86_read_instr_cmp_rm1632_r1632(const bin_t *, off_t *, off_t,
 /* Décode une instruction de type 'dec' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_dec_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
+/* Décode une instruction de type 'dec' (8 bits). */
+GArchInstruction *x86_read_instr_dec_rm8(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
+/* Décode une instruction de type 'dec' (16/32 bits). */
+GArchInstruction *x86_read_instr_dec_rm1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
 /* Décode une instruction de type 'hlt'. */
 GArchInstruction *x86_read_instr_hlt(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
@@ -117,6 +123,12 @@ GArchInstruction *x86_read_instr_imul_rm1632_imm8(const bin_t *, off_t *, off_t,
 /* Décode une instruction de type 'inc' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_inc_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
+/* Décode une instruction de type 'inc' (8 bits). */
+GArchInstruction *x86_read_instr_inc_rm8(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
+/* Décode une instruction de type 'inc' (16/32 bits). */
+GArchInstruction *x86_read_instr_inc_rm1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
 /* Décode une instruction de type 'int 3'. */
 GArchInstruction *x86_read_instr_int_3(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);