Supported some extra opcodes : popa and arpl.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@147 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

1 files changed, 6 insertions, 0 deletions

diff --git a/src/arch/x86/opcodes.h b/src/arch/x86/opcodes.h
index aaa4b55..5a6d69f 100644
--- a/src/arch/x86/opcodes.h
+++ b/src/arch/x86/opcodes.h
@@ -95,6 +95,9 @@ GArchInstruction *x86_read_instr_and_rm1632_imm1632(const bin_t *, off_t *, off_
 /* Décode une instruction de type 'and' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_and_rm1632_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
+/* Décode une instruction de type 'arpl' (16 bits). */
+GArchInstruction *x86_read_instr_arpl_rm16_r16(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
 /* Décode une instruction de type 'call'. */
 GArchInstruction *x86_read_instr_call_rel1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
@@ -317,6 +320,9 @@ GArchInstruction *x86_read_instr_or_rm8_r8(const bin_t *, off_t *, off_t, vmpa_t
 /* Décode une instruction de type 'or' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_or_rm1632_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
 
+/* Décode une instruction de type 'popa'. */
+GArchInstruction *x86_read_instr_popa(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);
+
 /* Décode une instruction de type 'pop' (16 ou 32 bits). */
 GArchInstruction *x86_read_instr_pop_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *);