diff options
author | Cyrille Bagard <nocbos@gmail.com> | 2009-06-08 08:52:12 (GMT) |
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committer | Cyrille Bagard <nocbos@gmail.com> | 2009-06-08 08:52:12 (GMT) |
commit | dd75712aac8f70d18f07787d5d484d426600edeb (patch) | |
tree | da59baffde7eb4eea2849c742321c3c96e485baa /src/arch/x86/opcodes.h | |
parent | a10960d2accb3eae5353917a7853cf0693cd081a (diff) |
Supported more x86 opcodes.
git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@71 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a
Diffstat (limited to 'src/arch/x86/opcodes.h')
-rw-r--r-- | src/arch/x86/opcodes.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/arch/x86/opcodes.h b/src/arch/x86/opcodes.h index 67858b0..e2ec5a6 100644 --- a/src/arch/x86/opcodes.h +++ b/src/arch/x86/opcodes.h @@ -108,6 +108,9 @@ GArchInstruction *x86_read_instr_dec_r1632(const bin_t *, off_t *, off_t, vmpa_t /* Décode une instruction de type 'hlt'. */ GArchInstruction *x86_read_instr_hlt(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *); +/* Décode une instruction de type 'imul' (16 ou 32 bits). */ +GArchInstruction *x86_read_instr_imul_rm1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *); + /* Décode une instruction de type 'inc' (16 ou 32 bits). */ GArchInstruction *x86_read_instr_inc_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *); @@ -319,6 +322,9 @@ GArchInstruction *x86_read_instr_test_e_ax_imm1632(const bin_t *, off_t *, off_t GArchInstruction *x86_read_instr_test_rm8_r8(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *); /* Décode une instruction de type 'test' (16 ou 32 bits). */ +GArchInstruction *x86_read_instr_test_rm1632_imm1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *); + +/* Décode une instruction de type 'test' (16 ou 32 bits). */ GArchInstruction *x86_read_instr_test_rm1632_r1632(const bin_t *, off_t *, off_t, vmpa_t, X86Prefix, const GX86Processor *); /* Décode une instruction de type 'xchg' (16 ou 32 bits). */ |