Supported more add opcodes: 0x03 and fixed 0x01.

git-svn-id: svn://svn.gna.org/svn/chrysalide/trunk@44 abbe820e-26c8-41b2-8c08-b7b2b41f8b0a

4 files changed, 47 insertions, 1 deletions

diff --git a/src/arch/x86/instruction.h b/src/arch/x86/instruction.h
index d731279..3823a90 100644
--- a/src/arch/x86/instruction.h
+++ b/src/arch/x86/instruction.h
@@ -41,6 +41,8 @@ typedef enum _X86Opcodes
     X86_OP_ADD_RM8_R8,                      /* add (0x00)                  */
     X86_OP_ADD_RM1632_R1632,                /* add ([0x66] 0x01)           */
 
+    X86_OP_ADD_R1632_RM1632,                /* add ([0x66] 0x03)           */
+
     X86_OP_SUB_R1632_RM1632,                /* sub ([0x66] 0x29)           */
 
     X86_OP_SUB_AL_IMM8,                     /* sub (0x2c)                  */
diff --git a/src/arch/x86/op_add.c b/src/arch/x86/op_add.c
index b065617..a2d6a8d 100644
--- a/src/arch/x86/op_add.c
+++ b/src/arch/x86/op_add.c
@@ -76,6 +76,44 @@ asm_x86_instr *x86_read_instr_add_imm8_to_rm1632(const uint8_t *data, off_t *pos
 *                offset = adresse virtuelle de l'instruction.                 *
 *                proc   = architecture ciblée par le désassemblage.           *
 *                                                                             *
+*  Description : Décode une instruction de type 'add' (16 ou 32 bits).        *
+*                                                                             *
+*  Retour      : Instruction mise en place ou NULL.                           *
+*                                                                             *
+*  Remarques   : -                                                            *
+*                                                                             *
+******************************************************************************/
+
+asm_x86_instr *x86_read_instr_add_r1632_rm1632(const uint8_t *data, off_t *pos, off_t len, uint64_t offset, const asm_x86_processor *proc)
+{
+    asm_x86_instr *result;                  /* Instruction à retourner     */
+    AsmOperandSize oprsize;                 /* Taille des opérandes        */
+
+    result = (asm_x86_instr *)calloc(1, sizeof(asm_x86_instr));
+
+    oprsize = switch_x86_operand_size_if_needed(proc, data, pos);
+
+    ASM_INSTRUCTION(result)->opcode = data[(*pos)++];
+
+    if (!x86_read_two_operands(result, data, pos, len, X86_OTP_R1632, X86_OTP_RM1632, oprsize))
+    {
+        free(result);
+        return NULL;
+    }
+
+    return result;
+
+}
+
+
+/******************************************************************************
+*                                                                             *
+*  Paramètres  : data   = flux de données à analyser.                         *
+*                pos    = position courante dans ce flux. [OUT]               *
+*                len    = taille totale des données à analyser.               *
+*                offset = adresse virtuelle de l'instruction.                 *
+*                proc   = architecture ciblée par le désassemblage.           *
+*                                                                             *
 *  Description : Décode une instruction de type 'add' (8 bits).               *
 *                                                                             *
 *  Retour      : Instruction mise en place ou NULL.                           *
diff --git a/src/arch/x86/opcodes.h b/src/arch/x86/opcodes.h
index 9bc5322..f7d91ac 100644
--- a/src/arch/x86/opcodes.h
+++ b/src/arch/x86/opcodes.h
@@ -43,6 +43,9 @@ asm_x86_instr *x86_read_instr_adc_rm1632_imm1632(const uint8_t *, off_t *, off_t
 /* Décode une instruction de type 'add' (16 ou 32 bits). */
 asm_x86_instr *x86_read_instr_add_imm8_to_rm1632(const uint8_t *, off_t *, off_t, uint64_t, const asm_x86_processor *);
 
+/* Décode une instruction de type 'add' (16 ou 32 bits). */
+asm_x86_instr *x86_read_instr_add_r1632_rm1632(const uint8_t *, off_t *, off_t, uint64_t, const asm_x86_processor *);
+
 /* Décode une instruction de type 'add' (8 bits). */
 asm_x86_instr *x86_read_instr_add_rm8_r8(const uint8_t *, off_t *, off_t, uint64_t, const asm_x86_processor *);
 
diff --git a/src/arch/x86/processor.c b/src/arch/x86/processor.c
index c6a116a..9bb3a23 100644
--- a/src/arch/x86/processor.c
+++ b/src/arch/x86/processor.c
@@ -239,7 +239,10 @@ AsmOperandSize switch_x86_operand_size_if_needed(const asm_x86_processor *proc,
 void x86_register_instructions(asm_x86_processor *proc)
 {
     register_opcode(proc->opcodes[X86_OP_ADD_RM8_R8], 0x00, "add", x86_read_instr_add_rm8_r8);
-    register_opcode(proc->opcodes[X86_OP_ADD_RM1632_R1632], 0x01, "add", x86_read_instr_add_rm1632_r1632);
+
+    register_opcode_1632(proc->opcodes[X86_OP_ADD_RM1632_R1632], 0x01, "add", x86_read_instr_add_rm1632_r1632);
+
+    register_opcode_1632(proc->opcodes[X86_OP_ADD_R1632_RM1632], 0x03, "add", x86_read_instr_add_r1632_rm1632);
 
     register_opcode_1632(proc->opcodes[X86_OP_SUB_R1632_RM1632], 0x29, "sub", x86_read_instr_sub_r1632_from_rm1632);