diff options
594 files changed, 21505 insertions, 7680 deletions
@@ -12,6 +12,7 @@ .libs/ ABOUT-NLS COPYING +ChangeLog INSTALL Makefile Makefile.in @@ -59,7 +60,7 @@ __pycache__ .gen/ fmk.done plugins/arm/v7/opcodes/ -plugins/dalvik/opcodes/ +plugins/dalvik/v35/opcodes/ # GLib src/glibext/chrysamarshal.* @@ -20,6 +20,7 @@ echo "timestamp" > stamp-h.in # As some Makefiles expect an external fragment built dynamically, ensure these files exist touch plugins/arm/v7/opcodes/gencode.mk touch plugins/dalvik/opcodes/gencode.mk +touch plugins/dalvik/v35/opcodes/gencode.mk touch ChangeLog diff --git a/configure.ac b/configure.ac index 84f12df..b919cb4 100644 --- a/configure.ac +++ b/configure.ac @@ -329,10 +329,11 @@ AC_CONFIG_FILES([Makefile plugins/arm/v7/opcodes/Makefile plugins/arm/v7/operands/Makefile plugins/dalvik/Makefile - plugins/dalvik/opdefs/Makefile - plugins/dalvik/opcodes/Makefile plugins/dalvik/operands/Makefile plugins/dalvik/pseudo/Makefile + plugins/dalvik/v35/Makefile + plugins/dalvik/v35/opcodes/Makefile + plugins/dalvik/v35/opdefs/Makefile plugins/devdbg/Makefile plugins/dex/Makefile plugins/dex/python/Makefile @@ -404,12 +405,15 @@ AC_CONFIG_FILES([Makefile tools/Makefile tools/d2c/Makefile tools/d2c/args/Makefile + tools/d2c/assert/Makefile tools/d2c/bits/Makefile tools/d2c/conv/Makefile + tools/d2c/desc/Makefile tools/d2c/format/Makefile tools/d2c/hooks/Makefile + tools/d2c/id/Makefile + tools/d2c/pattern/Makefile tools/d2c/rules/Makefile - tools/d2c/syntax/Makefile themes/Makefile themes/Adwaita/Makefile]) diff --git a/plugins/arm/v7/Makefile.am b/plugins/arm/v7/Makefile.am index e2fc96c..bac6841 100644 --- a/plugins/arm/v7/Makefile.am +++ b/plugins/arm/v7/Makefile.am @@ -7,7 +7,7 @@ libarmv7_la_SOURCES = \ core.h core.c \ cregister.h cregister.c \ fetch.h fetch.c \ - helpers.h helpers.c \ + helpers.h \ instruction.h instruction.c \ link.h link.c \ post.h post.c \ diff --git a/plugins/arm/v7/helpers.c b/plugins/arm/v7/helpers.c deleted file mode 100644 index 637cd9c..0000000 --- a/plugins/arm/v7/helpers.c +++ /dev/null @@ -1,277 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * helpers.c - aide à la mise en place des opérandes ARMv7 - * - * Copyright (C) 2014-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#include "helpers.h" - - -#include <arch/register.h> -#include <arch/immediate.h> -#include <common/asm.h> -#include <common/bconst.h> - - -#include "register.h" - - - -/****************************************************************************** -* * -* Paramètres : x = valeur sur 32 bits maximum à traiter. * -* shift = nombre de décalages visés. * -* * -* Description : Effectue une rotation vers la droit d'une valeur. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : Correspond à la pseudo fonction 'ROR_C'. * -* * -******************************************************************************/ - -GArchOperand *ror_armv7_imm(uint32_t x, unsigned int shift) -{ - GArchOperand *result; /* Opérande à faire remonter */ - uint32_t val32; /* Valeur sur 32 bits */ - - shift %= 32; - - val32 = (x >> shift) | (x << (32 - shift)); - - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - - return result; - -} - - - - - - - - - - - - -#if 0 - -// Shift_C() -// ========= -(bits(N), bit) Shift_C(bits(N) value, SRType type, integer amount, bit carry_in) -assert !(type == SRType_RRX && amount != 1); -if amount == 0 then -(result, carry_out) = (value, carry_in); -else -case type of - -when SRType_LSL -(result, carry_out) = LSL_C(value, amount); - -when SRType_LSR -(result, carry_out) - -when SRType_ASR -(result, carry_out) - -when SRType_ROR -(result, carry_out) - -when SRType_RRX -(result, carry_out) -= LSR_C(value, amount); -= ASR_C(value, amount); -= ROR_C(value, amount); -= RRX_C(value, carry_in); - -#endif - - - - - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* topbit = valeur du bit de poids fort manipulé. * -* size = taille de la valeur finale à constituer. * -* * -* Description : Crée un opérande de valeur immédiate avec extension de signe.* -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *sign_extend_armv7_imm(uint32_t value, bool topbit, unsigned int size) -{ - GArchOperand *result; /* Opérande à faire remonter */ - unsigned int msb; /* Position du premier bit à 1 */ - MemoryDataSize mds; /* Conversion de la taille */ - uint32_t val4; /* Valeur sur 4 bits */ - uint32_t val8; /* Valeur sur 8 bits */ - uint32_t val16; /* Valeur sur 16 bits */ - uint32_t val32; /* Valeur sur 32 bits */ - unsigned int i; /* Boucle de parcours */ - - result = NULL; - - topbit &= msb_32(value, &msb); - - switch (size) - { - -#define SIGN_EXTEND_CASE(sz) \ - case sz: \ - mds = MDS_ ## sz ## _BITS_SIGNED; \ - val ## sz = value; \ - if (topbit) \ - for (i = msb; i < sz; i++) \ - val ## sz |= (1 << i); \ - result = g_imm_operand_new_from_value(mds, val ## sz); \ - break; - - SIGN_EXTEND_CASE(4); - SIGN_EXTEND_CASE(8); - SIGN_EXTEND_CASE(16); - SIGN_EXTEND_CASE(32); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* * -* Description : Etend une valeur immédiate en mode 'Thumb' ARMv7. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchOperand *thumb_expand_armv7_imm(uint32_t value) -{ - GArchOperand *result; /* Opérande à faire remonter */ - uint8_t byte; /* Octet à reproduire */ - uint32_t val32; /* Valeur sur 32 bits */ - uint32_t unrotated; /* Transformation à décaller */ - - result = NULL; - - if (((value >> 10) & b11) == b00) - { - byte = value & 0xff; - - switch ((value >> 8) & b11) - { - case b00: - result = zero_extend_armv7_imm(byte, 32); - break; - - case b01: - if (byte == 0) return NULL; - val32 = byte << 16 | byte; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - case b10: - if (byte == 0) return NULL; - val32 = byte << 24 | byte << 8; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - case b11: - if (byte == 0) return NULL; - val32 = byte << 24 | byte << 16 | byte << 8 | byte; - result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val32); - break; - - } - - } - else - { - unrotated = 1 << 7 | (value & 0x3f); - result = ror_armv7_imm(unrotated, (value >> 7) & 0x1f); - } - - return result; - -} - - - - - - -/****************************************************************************** -* * -* Paramètres : value = valeur sur 32 bits maximum à traiter. * -* size = taille de la valeur finale à constituer. * -* * -* Description : Réalise un simple transtypage de valeur entière. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : Correspond à la pseudo fonction 'ZeroExtend'. * -* * -******************************************************************************/ - -GArchOperand *zero_extend_armv7_imm(uint32_t value, unsigned int size) -{ - GArchOperand *result; /* Opérande à faire remonter */ - MemoryDataSize mds; /* Conversion de la taille */ - uint32_t val4; /* Valeur sur 4 bits */ - uint32_t val8; /* Valeur sur 8 bits */ - uint32_t val16; /* Valeur sur 16 bits */ - uint32_t val32; /* Valeur sur 32 bits */ - - result = NULL; - - switch (size) - { - -#define ZERO_EXTEND_CASE(sz) \ - case sz: \ - mds = MDS_ ## sz ## _BITS_UNSIGNED; \ - val ## sz = value; \ - result = g_imm_operand_new_from_value(mds, val ## sz); \ - break; - - ZERO_EXTEND_CASE(4); - ZERO_EXTEND_CASE(8); - ZERO_EXTEND_CASE(16); - ZERO_EXTEND_CASE(32); - - } - - return result; - -} diff --git a/plugins/arm/v7/helpers.h b/plugins/arm/v7/helpers.h index 94b85f9..aa3de34 100644 --- a/plugins/arm/v7/helpers.h +++ b/plugins/arm/v7/helpers.h @@ -25,245 +25,265 @@ #define _PLUGINS_ARM_V7_HELPERS_H -#include <arch/operand.h> +#include <arch/immediate.h> +#include <arch/register.h> -#include "cregister.h" #include "pseudo.h" +#include "register.h" #include "operands/coproc.h" #include "operands/estate.h" -#include "operands/limitation.h" #include "operands/maccess.h" -#include "operands/offset.h" #include "operands/reglist.h" #include "operands/rotation.h" #include "operands/shift.h" -#include "../register.h" +/** + * Définitions élaborées à partir des spécifications. + */ -#define BarrierLimitation(opt) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_limitation_operand_new(opt); \ - __result; \ +#define ARMExpandImm(imm12) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_arm_expand_imm(imm12, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define BitDiff(msb, lsb) \ - ({ \ - GArchOperand *__result; \ - uint32_t __width; \ - __width = g_imm_operand_get_raw_value(G_IMM_OPERAND(msb)); \ - __width -= g_imm_operand_get_raw_value(G_IMM_OPERAND(lsb)); \ - __width += 1; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ - __result; \ +#define ARMExpandImm_C(imm12, c) \ + ({ \ + GArchOperand *__result; \ + uint32_t __val; \ + if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ + else \ + __result = NULL; \ + __result; \ }) -#define BuildImm8(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ - __result; \ +#define BitDiff(msb, lsb) \ + ({ \ + GArchOperand *__result; \ + uint32_t __width; \ + __width = msb - lsb + 1; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ + __result; \ }) -#define BuildImm16(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)val); \ - __result; \ +#define BuildRegShift(type, reg) \ + ({ \ + GArchOperand *__result; \ + SRType __shift_t; \ + if (!armv7_decode_reg_shift(type, &__shift_t)) \ + __result = NULL; \ + else \ + __result = g_armv7_shift_operand_new(__shift_t, reg); \ + __result; \ }) -#define CoProcessor(idx) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_coproc_operand_new(idx); \ - __result; \ +#define CoProcessor(idx) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_coproc_operand_new(idx); \ + __result; \ }) -#define CRegister(idx) \ - ({ \ - GArchOperand *__result; \ - GArmV7CRegister *__reg; \ - __reg = g_armv7_cregister_new(idx); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ - __result; \ +#define DecodeImmShift(type, imm5) \ + ({ \ + GArchOperand *__result; \ + SRType __shift_t; \ + uint8_t __shift_n; \ + GArchOperand *__op_n; \ + if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ + __result = NULL; \ + else \ + { \ + __op_n = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __shift_n); \ + __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ + } \ + __result; \ }) -#define IncWidth(widthm1) \ - ({ \ - GArchOperand *__result; \ - uint32_t __width; \ - __width = widthm1 + 1; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ - __result; \ +#define DecodeImmShiftAmount(type, imm5) \ + ({ \ + GArchOperand *__result; \ + uint8_t __shift_n; \ + if (!armv7_decode_imm_shift(type, imm5, (SRType []) { 0 }, &__shift_n)) \ + __result = NULL; \ + else \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __shift_n);\ + __result; \ }) -#define DecodeImmShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - SRType __shift_t; \ - uint32_t __shift_n; \ - GArchOperand *__op_n; \ - if (!armv7_decode_imm_shift(type, imm5, &__shift_t, &__shift_n)) \ - __result = NULL; \ - else \ - { \ - __op_n = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result = g_armv7_shift_operand_new(__shift_t, __op_n); \ - } \ - __result; \ +#define Endian(big) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_endian_operand_new(big); \ + __result; \ }) -#define EndianState(big) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_endian_operand_new(big); \ - __result; \ +#define FixedShift(type, imm5) \ + ({ \ + GArchOperand *__result; \ + uint8_t __shift_n; \ + __shift_n = imm5; \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __shift_n); \ + __result; \ }) -#define MakeMemoryAccess(base, off, shift, index, add, wback) \ - ({ \ - GArchOperand *__result; \ - GArchOperand *__offset; \ - if (off != NULL) \ - __offset = g_armv7_offset_operand_new(add, off); \ - else \ - __offset = NULL; \ - __result = g_armv7_maccess_operand_new(base, __offset, shift, index, wback); \ - __result; \ +#define MemAccessOffset(base, off) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, NULL, false, false); \ + __result; \ }) -#define NextRegister(prev) \ - ({ \ - GRegisterOperand *__prev_op; \ - GArchRegister *__reg; \ - uint8_t __id; \ - __prev_op = G_REGISTER_OPERAND(prev); \ - __reg = g_register_operand_get_register(__prev_op); \ - __id = g_arm_register_get_index(G_ARM_REGISTER(__reg)); \ - Register(__id + 1); \ +#define MemAccessOffsetExtended(base, off, shift) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, shift, false, false); \ + __result; \ }) -#define RawValue(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, (uint32_t)val); \ - __result; \ +#define MemAccessPreIndexed(base, off) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, NULL, false, true); \ + __result; \ }) -#define Register(idx) \ - ({ \ - GArchOperand *__result; \ - GArmV7Register *__reg; \ - __reg = g_armv7_register_new(idx); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ - __result; \ +#define MemAccessPreIndexedExtended(base, off, shift) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, shift, false, true); \ + __result; \ }) -#define RegisterShift(shift_t, rs) \ - ({ \ - GArchOperand *__result; \ - GArchOperand *__reg; \ - __reg = Register(rs); \ - if (__reg == NULL) \ - __result = NULL; \ - else \ - __result = g_armv7_shift_operand_new(shift_t, __reg); \ - __result; \ +#define MemAccessPostIndexed(base, off) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_maccess_operand_new(base, off, NULL, true, true); \ + __result; \ }) -#define Rotation(val5) \ +#define MemAccessPostIndexedExtended(base, off, shift) \ ({ \ GArchOperand *__result; \ - uint8_t __rot; \ - GArchOperand *__rot_op; \ - __rot = val5; \ - __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ - __result = g_armv7_rotation_operand_new(__rot_op); \ - if (__result == NULL) \ - g_object_unref(G_OBJECT(__rot_op)); \ + __result = g_armv7_maccess_operand_new(base, off, shift, true, true); \ __result; \ }) -#define UInt(val) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, (uint8_t)val); \ - __result; \ +#define MinusBitDiff(msb, lsb) \ + ({ \ + GArchOperand *__result; \ + uint32_t __width; \ + __width = msb - lsb + 1 + 1; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __width); \ + __result; \ }) +#define NextRegister(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__reg; \ + __reg = g_armv7_register_new(idx + 1); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ + }) -//#define DecodeImmShift(raw_type, raw_imm5); -//g_armv7_shift_operand_new(SRType type, GArchOperand *value) - - - -//#define MakeMemoryAccess(base, off, shift, index, add, wback) NULL - -//g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool writeb) +#define SignExtend(val, size, top) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## size ## _t __val; \ + __mds = MDS_ ## size ## _BITS_SIGNED; \ + __val = armv7_sign_extend(val, top, size); \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ + }) -//g_armv7_offset_operand_new(add, off) +#define SingleRegList(t) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_reglist_operand_new(1 << t); \ + __result; \ + }) +#define Register(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7Register *__reg; \ + __reg = g_armv7_register_new(idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ + }) -//////////////////// -#define Imm16(imm16) \ - ({ \ - GArchOperand *__result; \ - __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)imm16); \ - __result; \ +#define RegList(mask) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_reglist_operand_new(mask); \ + __result; \ }) -#define ARMExpandImm_C(imm12, c) \ + +#define Rotation(val5) \ ({ \ GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_arm_expand_imm_c(imm12, (bool []) { c }, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ + uint8_t __rot; \ + GArchOperand *__rot_op; \ + __rot = val5; \ + __rot_op = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __rot); \ + __result = g_armv7_rotation_operand_new(__rot_op); \ + if (__result == NULL) \ + g_object_unref(G_OBJECT(__rot_op)); \ __result; \ }) -#define ARMExpandImm(imm12) \ + +#define ThumbExpandImm(imm12) \ ({ \ GArchOperand *__result; \ uint32_t __val; \ - if (armv7_arm_expand_imm(imm12, &__val)) \ + if (armv7_thumb_expand_imm(imm12, &__val)) \ __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ else \ __result = NULL; \ __result; \ }) + #define ThumbExpandImm_C(imm12, c) \ ({ \ GArchOperand *__result; \ @@ -275,166 +295,98 @@ __result; \ }) -#define ThumbExpandImm(imm12) \ + +#define UInt(val) \ ({ \ GArchOperand *__result; \ - uint32_t __val; \ - if (armv7_thumb_expand_imm(imm12, &__val)) \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __val); \ - else \ - __result = NULL; \ + __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, val); \ __result; \ }) - - - - - -#define DecodeImmShiftValue(imm5) \ - ({ \ - GArchOperand *__result; \ - uint32_t __shift_n; \ - if (!armv7_decode_imm_shift(0, imm5, (SRType []) { 0 }, &__shift_n)) \ - __result = NULL; \ - else \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result; \ +#define UIntInc(sat4) \ + ({ \ + GArchOperand *__result; \ + uint8_t __val; \ + __val = sat4; \ + __result = g_imm_operand_new_from_value(MDS_8_BITS_UNSIGNED, __val); \ + __result; \ }) -#if 0 -// DecodeRegShift() -// ================ -SRType DecodeRegShift(bits(2) type) -case type of -when '00' shift_t = SRType_LSL; -when '01' shift_t = SRType_LSR; -when '10' shift_t = SRType_ASR; -when '11' shift_t = SRType_ROR; -return shift_t; -#endif - - - -#define ZeroExtend(x, i) \ - ({ \ - MemoryDataSize __mds; \ - uint ## i ## _t __val; \ - __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = armv7_zero_extend(x, 0/**/, i); \ - g_imm_operand_new_from_value(__mds, __val); \ +#define Zeros(i) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## i ## _t __val; \ + __mds = MDS_ ## i ## _BITS_UNSIGNED; \ + __val = 0; \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ }) - -#define Zeros(i) \ - ({ \ - MemoryDataSize __mds; \ - uint ## i ## _t __val; \ - __mds = MDS_ ## i ## _BITS_UNSIGNED; \ - __val = 0; \ - g_imm_operand_new_from_value(__mds, __val); \ +#define ZeroExtend(x, i) \ + ({ \ + GArchOperand *__result; \ + MemoryDataSize __mds; \ + uint ## i ## _t __val; \ + __mds = MDS_ ## i ## _BITS_UNSIGNED; \ + __val = armv7_zero_extend(x, -1, i); \ + __result = g_imm_operand_new_from_value(__mds, __val); \ + __result; \ }) - - - - - - /** - * Glue purement interne. + * Définitions complémentaires. */ -#define MakeAccessOffset(add, off) \ - g_armv7_offset_operand_new(add, off) - - -#define MakeShiftedMemoryAccess(base, off, shift, wr) \ - g_armv7_maccess_operand_new(base, off, shift, wr) +#define APSR_C 0 -#define _MakeMemoryAccess(base, off, wr) \ - MakeShiftedMemoryAccess(base, off, NULL, wr) - -/* -#define MakeMemoryAccess(base, off, add, wr) \ - ({ \ - GArchOperand *__off; \ - __off = MakeAccessOffset(add, off); \ - _MakeMemoryAccess(base, __off, wr); \ - }) -*/ - -#define MakeMemoryNotIndexed(base, wr) \ - _MakeMemoryAccess(base, NULL, wr) - - - - - - - - -// type == '10', pas 2 ! (FIXME) -#define FixedShift(type, imm5) \ - ({ \ - GArchOperand *__result; \ - uint32_t __shift_n; \ - __shift_n = imm5; \ - __result = g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, __shift_n); \ - __result; \ - }) +/** + * Petite glue vers le format ARM générique... + */ +#define g_armv7_instruction_extend_keyword(ins, ext) \ + g_arm_instruction_extend_keyword(G_ARM_INSTRUCTION(ins), ext) /** - * Glue purement interne pour les listes de registres. + * Vieilleries à conserver au cas où... */ -#define RegistersList(mask) \ - ({ \ - GArchOperand *__result; \ - __result = g_armv7_reglist_operand_new(); \ - if (!g_armv7_reglist_load_registers(G_ARMV7_REGLIST_OPERAND(__result), mask)) \ - { \ - g_object_unref(G_OBJECT(__result)); \ - __result = NULL; \ - } \ - __result; \ - }) - - -#define ListFromRegister(regop) \ - ({ \ - GArchOperand *__result; \ - GArmV7Register *__reg; \ - __result = g_armv7_reglist_operand_new(); \ - __reg = G_ARMV7_REGISTER(regop); \ - g_armv7_reglist_add_register(G_ARMV7_REGLIST_OPERAND(__result), __reg); \ - __result; \ - }) +#if 0 +#include "cregister.h" +#include "operands/limitation.h" -/* Effectue une rotation vers la droit d'une valeur. */ -GArchOperand *ror_armv7_imm(uint32_t, unsigned int); +#define BarrierLimitation(opt) \ + ({ \ + GArchOperand *__result; \ + __result = g_armv7_limitation_operand_new(opt); \ + __result; \ + }) -/* Crée un opérande de valeur immédiate avec extension de signe. */ -GArchOperand *sign_extend_armv7_imm(uint32_t, bool, unsigned int); -/* Etend une valeur immédiate en mode 'Thumb' ARMv7. */ -GArchOperand *thumb_expand_armv7_imm(uint32_t); +#define CRegister(idx) \ + ({ \ + GArchOperand *__result; \ + GArmV7CRegister *__reg; \ + __reg = g_armv7_cregister_new(idx); \ + if (__reg == NULL) \ + __result = NULL; \ + else \ + __result = g_register_operand_new(G_ARCH_REGISTER(__reg)); \ + __result; \ -/* Réalise un simple transtypage de valeur entière. */ -GArchOperand *zero_extend_armv7_imm(uint32_t, unsigned int); +#endif diff --git a/plugins/arm/v7/opcodes/Makefile.am b/plugins/arm/v7/opcodes/Makefile.am index a169c2b..ddaabb7 100644 --- a/plugins/arm/v7/opcodes/Makefile.am +++ b/plugins/arm/v7/opcodes/Makefile.am @@ -23,4 +23,7 @@ AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) -I$(top_srcdir)/src +CLEANFILES = $(GENERATED_FILES) + + EXTRA_DIST = opcodes_tmp_arm.h opcodes_tmp_simd.h opcodes_tmp_thumb_16.h opcodes_tmp_thumb_32.h diff --git a/plugins/arm/v7/opdefs/Makefile.am b/plugins/arm/v7/opdefs/Makefile.am index 3f69a3f..0538359 100644 --- a/plugins/arm/v7/opdefs/Makefile.am +++ b/plugins/arm/v7/opdefs/Makefile.am @@ -1,60 +1,48 @@ -include ../../../../tools/d2c/d2c.mk +include $(top_srcdir)/tools/d2c/d2c.mk -D2C_BIN = ../../../../tools/d2c/d2c -GEN_BIN = ../../../../tools/d2c/d2c_genmakefile.sh +D2C_BIN = $(top_srcdir)/tools/d2c/d2c +GEN_BIN = $(top_srcdir)/tools/d2c/d2c_genmakefile.sh -D2C_TYPE = raw -D2C_OUTDIR = $(PWD)/.. +D2C_OUTDIR = $(PWD)/../opcodes/ + +D2C_TYPE = raw -D2C_ARCH = armv7 -D2C_HEADER = _ARCH_ARM_V7 +D2C_ARCH = ARMv7 +D2C_ARCH_CN = ARMv7 +D2C_GUARD = PLUGINS_ARM_V7_OPCODES D2C_ENCODINGS = \ - -e A=arm_ \ - -e t=thumb_16_ \ - -e T=thumb_32_ + -e A=arm \ + -e t=thumb_16 \ + -e T=thumb_32 + +D2C_ID_PREFIX = AOP7 +D2C_ID_COUNT = 500 -D2C_MACROS = \ - -M SetFlags=g_armv7_instruction_define_setflags \ - -M Condition=g_arm_instruction_set_cond \ - -M "ExpandImmC32=g_imm_operand_new_from_value(MDS_32_BITS_UNSIGNED, " \ - -M SignExtend=sign_extend_armv7_imm \ - -M SetInsFlag=g_arch_instruction_set_flag \ - -M StoreCondition=g_arm_instruction_set_cond \ - -M ExtendKeyword=g_arm_instruction_extend_keyword +D2C_SPECIFIC = -D2C_OPERANDS = \ - -n BarrierLimitation \ - -n BitDiff \ - -n IncWidth \ - -n DecodeImmShift \ - -n MakeMemoryAccess \ - -n Register \ - -n RegisterShift \ - -n UInt \ - -n ZeroExtend -FIXED_C_INCLUDES = \ - \n\#include <arch/link.h> \ - \n\#include <common/bconst.h> \ - \n \ - \n\#include \"../helpers.h\" \ - \n\#include \"../instruction.h\" \ - \n\#include \"../fetch.h\" \ - \n\#include \"../link.h\" \ - \n\#include \"../post.h\" \ - \n\#include \"../../instruction.h\" \ - \n\#include \"../../link.h\" \ - \n\n +FIXED_C_INCLUDES = \ + \#include <assert.h> \ + \n \ + \n\#include <arch/link.h> \ + \n\#include <common/bconst.h> \ + \n \ + \n\#include "../helpers.h" \ + \n\#include "../instruction.h" \ + \n\#include "../fetch.h" \ + \n\#include "../link.h" \ + \n\#include "../post.h" \ + \n\#include "../../instruction.h" \ + \n\#include "../../link.h" -FIXED_H_INCLUDES = \ - \n\#include <stdint.h> \ - \n \ - \n\#include <arch/instruction.h> \ - \n\n +FIXED_H_INCLUDES = \ + \#include <stdint.h> \ + \n \ + \n\#include <arch/instruction.h> # for i in $(seq 1 426); do test -f *A88$i.d && (ls *A88$i.d | sed 's/^/\t/' | sed 's/$/\t\t\t\t\t\t\\/') ; done @@ -278,7 +266,6 @@ ARMV7_DEFS = \ wfi_A88425.d \ yield_A88426.d -# subs_B9320.d # make dist procède répertoire par répertoire. Or le répertoire opcodes utilise # le contenu du répertoire opdefs. Il faut donc générer les fichiers nécessaires @@ -295,7 +282,7 @@ dist-hook: all: $(ARMV7_DEFS:.d=.g) fmk.done d2c_final_rules fmk.done: $(ARMV7_DEFS) - $(GEN_BIN) ../opcodes/ ../opdefs/.gen ../../../../tools/d2c/globalgen.mk arm thumb_32 thumb_16 + $(GEN_BIN) $(D2C_OUTDIR) arm thumb_32 thumb_16 touch $@ clean: diff --git a/plugins/arm/v7/opdefs/adc_A881.d b/plugins/arm/v7/opdefs/adc_A881.d index 6bc66e2..5033749 100644 --- a/plugins/arm/v7/opdefs/adc_A881.d +++ b/plugins/arm/v7/opdefs/adc_A881.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ADC (immediate) -@desc Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 0 + +@desc { + + Add with Carry (immediate) adds an immediate value and the Carry flag value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + } + + @asm adc ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adcs ?reg_D reg_N imm32 } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 1 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adcs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/adc_A882.d b/plugins/arm/v7/opdefs/adc_A882.d index 27ce6ad..77b53df 100644 --- a/plugins/arm/v7/opdefs/adc_A882.d +++ b/plugins/arm/v7/opdefs/adc_A882.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ADC (register) -@desc Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 1 + +@desc { + + Add with Carry (register) adds a register value, the Carry flag value, and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3) - @syntax "adcs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm adc ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm adc.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adcs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/adc_A883.d b/plugins/arm/v7/opdefs/adc_A883.d index a9c56d8..6371445 100644 --- a/plugins/arm/v7/opdefs/adc_A883.d +++ b/plugins/arm/v7/opdefs/adc_A883.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title ADC (register-shifted register) -@desc Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 2 + +@desc { + + Add with Carry (register-shifted register) adds a register value, the Carry flag value, and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adc ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adcs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A8810.d b/plugins/arm/v7/opdefs/add_A8810.d index 2047276..c7f30b4 100644 --- a/plugins/arm/v7/opdefs/add_A8810.d +++ b/plugins/arm/v7/opdefs/add_A8810.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (SP plus register, Thumb) -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. +@id 9 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 0 1 0 0 0 1 0 0 DM(1) 1 1 0 1 Rdm(3) - @syntax <reg_DM_1> <SP> <reg_DM_2> + @syntax { + + @conv { - @conv { + reg_D = Register(DM:Rdm) + reg_SP = Register(13) + reg_M = Register(DM:Rdm) - reg_DM_1 = Register(DM:Rdm) - reg_DM_2 = Register(DM:Rdm) - SP = Register(13) + } + + @asm add ?reg_D reg_SP reg_M } @@ -45,12 +55,17 @@ @half 0 1 0 0 0 1 0 0 1 Rm(4) 1 0 1 - @syntax <SP> <reg_M> + @syntax { + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + reg_M = Register(Rm) - @conv { + } - reg_M = Register(Rm) - SP = Register(13) + @asm add ?reg_D reg_SP reg_M } @@ -60,22 +75,45 @@ @word 1 1 1 0 1 0 1 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <SP> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_SP reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_SP reg_M ?shift } diff --git a/plugins/arm/v7/opdefs/add_A8811.d b/plugins/arm/v7/opdefs/add_A8811.d index 5b6c0d1..e70c33c 100644 --- a/plugins/arm/v7/opdefs/add_A8811.d +++ b/plugins/arm/v7/opdefs/add_A8811.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title ADD (SP plus register, ARM) -@desc This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. +@id 10 + +@desc { + + This instruction adds an optionally-shifted register value to the SP value, and writes the result to the destination register. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <SP> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_SP reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_SP reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A884.d b/plugins/arm/v7/opdefs/add_A884.d index 8b624a7..f61d447 100644 --- a/plugins/arm/v7/opdefs/add_A884.d +++ b/plugins/arm/v7/opdefs/add_A884.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (immediate, Thumb) -@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 3 + +@desc { + + This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 1 0 imm3(3) Rn(3) Rd(3) - @syntax "adds" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) + @asm add ?reg_D reg_N imm32 } @@ -45,12 +55,17 @@ @half 0 0 1 1 0 Rdn(3) imm8(8) - @syntax "adds" <reg_DN> <imm32> + @syntax { - @conv { + @conv { - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm add ?reg_D reg_N imm32 } @@ -60,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm add.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm adds.w ?reg_D reg_N imm32 } @@ -84,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm addw ?reg_D reg_N imm32 } diff --git a/plugins/arm/v7/opdefs/add_A885.d b/plugins/arm/v7/opdefs/add_A885.d index 0f4a919..5bb4e6f 100644 --- a/plugins/arm/v7/opdefs/add_A885.d +++ b/plugins/arm/v7/opdefs/add_A885.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,67 @@ @title ADD (immediate, ARM) -@desc This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 4 + +@desc { + + This instruction adds an immediate value to a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 1 0 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm add ?reg_D reg_N imm32 - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm adds ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A886.d b/plugins/arm/v7/opdefs/add_A886.d index e4f9e00..c84259f 100644 --- a/plugins/arm/v7/opdefs/add_A886.d +++ b/plugins/arm/v7/opdefs/add_A886.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (register, Thumb) -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 5 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 0 0 Rm(3) Rn(3) Rd(3) - @syntax "adds" <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm add ?reg_D reg_N reg_M } @@ -45,12 +55,17 @@ @half 0 1 0 0 0 1 0 0 DN(1) Rm(4) Rdn(3) - @syntax <reg_DN> <reg_M> + @syntax { + + @conv { + + reg_D = Register(DN:Rdn) + reg_N = Register(DN:Rdn) + reg_M = Register(Rm) - @conv { + } - reg_DN = Register(DN:Rdn) - reg_M = Register(Rm) + @asm add ?reg_D reg_N reg_M } @@ -60,22 +75,45 @@ @word 1 1 1 0 1 0 1 1 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm add.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_N reg_M ?shift } diff --git a/plugins/arm/v7/opdefs/add_A887.d b/plugins/arm/v7/opdefs/add_A887.d index 18400a6..400e179 100644 --- a/plugins/arm/v7/opdefs/add_A887.d +++ b/plugins/arm/v7/opdefs/add_A887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title ADD (register, ARM) -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 6 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_N reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A888.d b/plugins/arm/v7/opdefs/add_A888.d index 5549145..0e4757b 100644 --- a/plugins/arm/v7/opdefs/add_A888.d +++ b/plugins/arm/v7/opdefs/add_A888.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title ADD (register-shifted register) -@desc Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 7 + +@desc { + + Add (register-shifted register) adds a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm add ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm adds ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/add_A889.d b/plugins/arm/v7/opdefs/add_A889.d index 5fab17c..6c6c572 100644 --- a/plugins/arm/v7/opdefs/add_A889.d +++ b/plugins/arm/v7/opdefs/add_A889.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ADD (SP plus immediate) -@desc This instruction adds an immediate value to the SP value, and writes the result to the destination register. +@id 8 + +@desc { + + This instruction adds an immediate value to the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 0 1 Rd(3) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) + } + + @asm add ?reg_D reg_SP imm32 } @@ -45,13 +55,17 @@ @half 1 0 1 1 0 0 0 0 0 imm7(7) - @syntax <SP_0> <SP_1> <imm32> + @syntax { + + @conv { + + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) - @conv { + } - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) + @asm add ?reg_D reg_SP imm32 } @@ -61,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 0 0 0 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm add.w ?reg_D reg_SP imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm adds.w ?reg_D reg_SP imm32 } @@ -85,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax "addw" <reg_D> <SP> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm addw ?reg_D reg_SP imm32 } @@ -101,21 +141,55 @@ @word cond(4) 0 0 1 0 1 0 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm add ?reg_D reg_SP imm32 + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm adds ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/adr_A8812.d b/plugins/arm/v7/opdefs/adr_A8812.d index 16615cb..ee5ed75 100644 --- a/plugins/arm/v7/opdefs/adr_A8812.d +++ b/plugins/arm/v7/opdefs/adr_A8812.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title ADR -@desc This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. +@id 11 + +@desc { + + This instruction adds an immediate value to the PC value to form a PC-relative address, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 0 0 Rd(3) imm8(8) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8:'00', 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8:'00', 32) + + } + + @asm adr reg_D imm32 } @@ -44,12 +54,16 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax ".W" <reg_D> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm adr.w reg_D imm32 } @@ -59,12 +73,16 @@ @word 1 1 1 1 0 i(1) 1 0 0 0 0 0 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax ".W" <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(i:imm3:imm8, 32) + + } + + @asm adr.w reg_D imm32 } @@ -74,18 +92,22 @@ @word cond(4) 0 0 1 0 1 0 0 0 1 1 1 1 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - } + } + + @asm adr reg_D imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -95,18 +117,22 @@ @word cond(4) 0 0 1 0 0 1 0 0 1 1 1 1 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ARMExpandImm(imm12) + reg_D = Register(Rd) + imm32 = ARMExpandImm(imm12) - } + } + + @asm adr reg_D imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/and_A8813.d b/plugins/arm/v7/opdefs/and_A8813.d index 3e1d0ed..0e303f2 100644 --- a/plugins/arm/v7/opdefs/and_A8813.d +++ b/plugins/arm/v7/opdefs/and_A8813.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title AND (immediate) -@desc This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. +@id 12 + +@desc { + + This instruction performs a bitwise AND of a register value and an immediate value, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm and ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm ands ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 0 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm and ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm ands ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/and_A8814.d b/plugins/arm/v7/opdefs/and_A8814.d index 77f7e55..94ea843 100644 --- a/plugins/arm/v7/opdefs/and_A8814.d +++ b/plugins/arm/v7/opdefs/and_A8814.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title AND (register) -@desc This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 13 + +@desc { + + This instruction performs a bitwise AND of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 0 0 Rm(3) Rdn(3) - @syntax "ands" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm and ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 0 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm and.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm ands.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm and ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm ands ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/and_A8815.d b/plugins/arm/v7/opdefs/and_A8815.d index 5ace3fa..ca44183 100644 --- a/plugins/arm/v7/opdefs/and_A8815.d +++ b/plugins/arm/v7/opdefs/and_A8815.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title AND (register-shifted register) -@desc This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 14 + +@desc { + + This instruction performs a bitwise AND of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 0 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm and ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm ands ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/asr_A8816.d b/plugins/arm/v7/opdefs/asr_A8816.d index 006a26c..87d4b3e 100644 --- a/plugins/arm/v7/opdefs/asr_A8816.d +++ b/plugins/arm/v7/opdefs/asr_A8816.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title ASR (immediate) -@desc Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 15 + +@desc { + + Arithmetic Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in copies of its sign bit, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 0 imm5(5) Rm(3) Rd(3) - @syntax "asrs" <reg_D> <reg_M> <shift_imm> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('10', imm5) + } + + @asm asr ?reg_D reg_M shift_n } @@ -45,21 +55,43 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('10', imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm3:imm2) + + } + + @asm asr.w ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm asrs.w ?reg_D reg_M shift_n } @@ -69,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 0 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('10', imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asr ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('10', imm5) + + } + + @asm asrs ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/asr_A8817.d b/plugins/arm/v7/opdefs/asr_A8817.d index 1e1e9c1..6d5b5ef 100644 --- a/plugins/arm/v7/opdefs/asr_A8817.d +++ b/plugins/arm/v7/opdefs/asr_A8817.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ASR (register) -@desc Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 16 + +@desc { + + Arithmetic Shift Right (register) shifts a register value right by a variable number of bits, shifting in copies of its sign bit, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 0 0 Rm(3) Rdn(3) - @syntax "asrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm asr ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 1 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asr.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm asrs.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm asrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/b_A8818.d b/plugins/arm/v7/opdefs/b_A8818.d index 9e27753..abd542f 100644 --- a/plugins/arm/v7/opdefs/b_A8818.d +++ b/plugins/arm/v7/opdefs/b_A8818.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,23 +23,33 @@ @title B -@desc Branch causes a branch to a target address. +@id 17 + +@desc { + + Branch causes a branch to a target address. + +} @encoding (t1) { @half 1 1 0 1 cond(4) imm8(8) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm8:'0', imm8 & 0x80, 32) + imm32 = SignExtend(imm8:'0', 32, 8) - } + } - @rules { + @asm b imm32 - chk_call StoreCondition(cond) + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -57,11 +67,15 @@ @half 1 1 1 0 0 imm11(11) - @syntax <imm32> + @syntax { + + @conv { + + imm32 = SignExtend(imm11:'0', 32, 11) - @conv { + } - imm32 = SignExtend(imm11:'0', imm11 & 0x400, 32) + @asm b imm32 } @@ -79,17 +93,22 @@ @word 1 1 1 1 0 S(1) cond(4) imm6(6) 1 0 J1(1) 0 J2(1) imm11(11) - @syntax ".W" <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', S & 0x1, 32) + imm32 = SignExtend(S:J2:J1:imm6:imm11:'0', 32, 20) - } + } + + @asm b imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + check g_armv7_instruction_extend_keyword(".W") + + } } @@ -107,13 +126,15 @@ @word 1 1 1 1 0 S(1) imm10(10) 1 0 J1(1) 1 J2(1) imm11(11) - @syntax ".W" <imm32> + @syntax { + + @conv { - @conv { + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + } + + @asm b.w imm32 } @@ -131,17 +152,21 @@ @word cond(4) 1 0 1 0 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + imm32 = SignExtend(imm24:'00', 32, 25) - } + } + + @asm b imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bfc_A8819.d b/plugins/arm/v7/opdefs/bfc_A8819.d index 0ee99c8..bb0e448 100644 --- a/plugins/arm/v7/opdefs/bfc_A8819.d +++ b/plugins/arm/v7/opdefs/bfc_A8819.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title BFC -@desc Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. +@id 18 + +@desc { + + Bit Field Clear clears any number of adjacent bits at any position in a register, without affecting the other bits in the register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 0 1 1 0 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - @syntax <reg_D> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + lsbit = UInt(imm3:imm2) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - reg_D = Register(Rd) - msbit = UInt(msb) - lsbit = UInt(imm3:imm2) - width = BitDiff(msbit, lsbit) + } + + @asm bfc reg_D lsbit width } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 1 1 1 1 - @syntax <reg_D> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - msbit = UInt(msb) - lsbit = UInt(lsb) - width = BitDiff(msbit, lsbit) + reg_D = Register(Rd) + lsbit = UInt(lsb) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - } + } + + @asm bfc reg_D lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bfi_A8820.d b/plugins/arm/v7/opdefs/bfi_A8820.d index 1d2bb2f..ac33950 100644 --- a/plugins/arm/v7/opdefs/bfi_A8820.d +++ b/plugins/arm/v7/opdefs/bfi_A8820.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title BFI -@desc Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. +@id 19 + +@desc { + + Bit Field Insert copies any number of low order bits from a register into the same number of adjacent bits at any position in the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 0 1 1 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 msb(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - msbit = UInt(msb) - lsbit = UInt(imm3:imm2) - width = BitDiff(msbit, lsbit) + } + + @asm bfi reg_D reg_N lsbit width } @@ -47,21 +57,25 @@ @word cond(4) 0 1 1 1 1 1 0 msb(5) Rd(4) lsb(5) 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - msbit = UInt(msb) - lsbit = UInt(lsb) - width = BitDiff(msbit, lsbit) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + msbit = UInt(msb) + width = BitDiff(msbit, lsbit) - } + } + + @asm bfi reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bic_A8821.d b/plugins/arm/v7/opdefs/bic_A8821.d index 9171b69..1fa6092 100644 --- a/plugins/arm/v7/opdefs/bic_A8821.d +++ b/plugins/arm/v7/opdefs/bic_A8821.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title BIC (immediate) -@desc Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 20 + +@desc { + + Bitwise Bit Clear (immediate) performs a bitwise AND of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm bic ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm bics ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 1 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm bic ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm bics ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bic_A8822.d b/plugins/arm/v7/opdefs/bic_A8822.d index 8503460..858adb8 100644 --- a/plugins/arm/v7/opdefs/bic_A8822.d +++ b/plugins/arm/v7/opdefs/bic_A8822.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title BIC (register) -@desc Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 21 + +@desc { + + Bitwise Bit Clear (register) performs a bitwise AND of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3) - @syntax "bics" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm bic ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 0 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm bic.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm bics.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm bic ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm bics ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bic_A8823.d b/plugins/arm/v7/opdefs/bic_A8823.d index e6903db..3058125 100644 --- a/plugins/arm/v7/opdefs/bic_A8823.d +++ b/plugins/arm/v7/opdefs/bic_A8823.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title BIC (register-shifted register) -@desc Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 22 + +@desc { + + Bitwise Bit Clear (register-shifted register) performs a bitwise AND of a register value and the complement of a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm bic ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm bics ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bkpt_A8824.d b/plugins/arm/v7/opdefs/bkpt_A8824.d index f0aa13a..bc034e9 100644 --- a/plugins/arm/v7/opdefs/bkpt_A8824.d +++ b/plugins/arm/v7/opdefs/bkpt_A8824.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BKPT -@desc Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. +@id 23 + +@desc { + + Breakpoint causes a software breakpoint to occur. Breakpoint is always unconditional, even when inside an IT block. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 0 imm8(8) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = ZeroExtend(imm8, 32) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm bkpt imm32 } @@ -43,11 +53,15 @@ @word cond(4) 0 0 0 1 0 0 1 0 imm12(12) 0 1 1 1 imm4(4) - @syntax <imm32> + @syntax { + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) - @conv { + } - imm32 = ZeroExtend(imm12:imm4, 32) + @asm bkpt imm32 } diff --git a/plugins/arm/v7/opdefs/bl_A8825.d b/plugins/arm/v7/opdefs/bl_A8825.d index da0def4..f584f0b 100644 --- a/plugins/arm/v7/opdefs/bl_A8825.d +++ b/plugins/arm/v7/opdefs/bl_A8825.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,27 @@ @title BL, BLX (immediate) -@desc Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. +@id 24 + +@desc { + + Branch with Link calls a subroutine at a PC-relative address. Branch with Link and Exchange Instruction Sets (immediate) calls a subroutine at a PC-relative address, and changes instruction set from ARM to Thumb, or from Thumb to ARM. + +} @encoding (T1) { @word 1 1 1 1 0 S(1) imm10(10) 1 1 J1(1) 1 J2(1) imm11(11) - @syntax <imm32> + @syntax { - @conv { + @conv { - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10:imm11:'0', S & 0x1, 32) + imm32 = SignExtend(S:J2:J1:imm10:imm11:'0', 32, 24) + + } + + @asm bl imm32 } @@ -53,13 +61,15 @@ @word 1 1 1 1 0 S(1) imm10H(10) 1 1 J1(1) 0 J2(1) imm10L(10) H(1) - @syntax "blx" <imm32> + @syntax { + + @conv { - @conv { + imm32 = SignExtend(S:J1:J2:imm10H:imm10L:'00', 32, 24) - I1 = NOT(J1 EOR S) - I2 = NOT(J2 EOR S) - imm32 = SignExtend(S:I1:I2:imm10H:imm10L:'00', S & 0x1, 32) + } + + @asm blx imm32 } @@ -77,17 +87,21 @@ @word cond(4) 1 0 1 1 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = SignExtend(imm24:'00', imm24 & 0x800000, 32) + imm32 = SignExtend(imm24:'00', 32, 25) - } + } + + @asm bl imm32 - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -105,11 +119,15 @@ @word 1 1 1 1 1 0 1 H(1) imm24(24) - @syntax "blx" <imm32> + @syntax { + + @conv { + + imm32 = SignExtend(imm24:H:'0', 32, 25) - @conv { + } - imm32 = SignExtend(imm24:H:'0', imm24 & 0x800000, 32) + @asm blx imm32 } diff --git a/plugins/arm/v7/opdefs/blx_A8826.d b/plugins/arm/v7/opdefs/blx_A8826.d index 29719fa..9a856b1 100644 --- a/plugins/arm/v7/opdefs/blx_A8826.d +++ b/plugins/arm/v7/opdefs/blx_A8826.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BLX (register) -@desc Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. +@id 25 + +@desc { + + Branch with Link and Exchange (register) calls a subroutine at an address and instruction set specified by a register. + +} @encoding (t1) { @half 0 1 0 0 0 1 1 1 1 Rm(4) 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm blx reg_M } @@ -43,17 +53,21 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm blx reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/bx_A8827.d b/plugins/arm/v7/opdefs/bx_A8827.d index f3681e7..15d6288 100644 --- a/plugins/arm/v7/opdefs/bx_A8827.d +++ b/plugins/arm/v7/opdefs/bx_A8827.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,24 +23,33 @@ @title BX -@desc Branch and Exchange causes a branch to an address and instruction set specified by a register. +@id 26 + +@desc { + + Branch and Exchange causes a branch to an address and instruction set specified by a register. + +} @encoding (t1) { @half 0 1 0 0 0 1 1 1 0 Rm(4) 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm bx reg_M } @hooks { fetch = help_fetching_with_instruction_bx_from_thumb - link = handle_armv7_conditional_branch_from_register } @@ -50,24 +59,27 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm bx reg_M - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @hooks { - fetch = help_fetching_with_instruction_bx_from_arm - link = handle_armv7_conditional_branch_from_register + fetch = help_fetching_with_instruction_bx_from_thumb } diff --git a/plugins/arm/v7/opdefs/bxj_A8828.d b/plugins/arm/v7/opdefs/bxj_A8828.d index efa2de2..0716a31 100644 --- a/plugins/arm/v7/opdefs/bxj_A8828.d +++ b/plugins/arm/v7/opdefs/bxj_A8828.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title BXJ -@desc Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. +@id 27 + +@desc { + + Branch and Exchange Jazelle attempts to change to Jazelle state. If the attempt fails, it branches to an address and instruction set specified by a register as though it were a BX instruction. In an implementation that includes the Virtualization Extensions, if HSTR.TJDBX is set to 1, execution of a BXJ instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception. For more information see Trapping accesses to Jazelle functionality on page B1-1255. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 1 0 0 Rm(4) 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 - @syntax <reg_M> + @syntax { + + @conv { - @conv { + reg_M = Register(Rm) - reg_M = Register(Rm) + } + + @asm bxj reg_M } @@ -43,17 +53,21 @@ @word cond(4) 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 0 Rm(4) - @syntax <reg_M> + @syntax { - @conv { + @conv { - reg_M = Register(Rm) + reg_M = Register(Rm) - } + } + + @asm bxj reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cb_A8829.d b/plugins/arm/v7/opdefs/cb_A8829.d index 134e0f4..3ac923a 100644 --- a/plugins/arm/v7/opdefs/cb_A8829.d +++ b/plugins/arm/v7/opdefs/cb_A8829.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,53 @@ @title CBNZ, CBZ -@desc Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. +@id 28 + +@desc { + + Compare and Branch on Nonzero and Compare and Branch on Zero compare the value in a register with zero, and conditionally branch forward a constant value. They do not affect the condition flags. + +} @encoding (t1) { @half 1 0 1 1 op(1) 0 i(1) 1 imm5(5) Rn(3) - @syntax <reg_N> <imm32> + @syntax { + + @assert { + + op == 0 + + } + + @conv { - @conv { + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm5:'0', 32) - nonzero = (op == '1') + } + + @asm cbz reg_N imm32 } - @rules { + @syntax { + + @assert { + + op == 1 + + } + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm5:'0', 32) + + } - if (nonzero); chk_call ExtendKeyword("n") - chk_call ExtendKeyword("z") + @asm cbnz reg_N imm32 } diff --git a/plugins/arm/v7/opdefs/cdp_A8830.d b/plugins/arm/v7/opdefs/cdp_A8830.d index 109b89b..6d2148d 100644 --- a/plugins/arm/v7/opdefs/cdp_A8830.d +++ b/plugins/arm/v7/opdefs/cdp_A8830.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,22 +23,32 @@ @title CDP, CDP2 -@desc Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. +@id 29 + +@desc { + + Coprocessor Data Processing tells a coprocessor to perform an operation that is independent of ARM core registers and memory. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRd, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid CDP and CDP2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. + +} @encoding (T1) { @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @syntax { - @conv { + @conv { - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } @@ -46,24 +56,22 @@ @encoding (A1) { - @word cond(4) 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - - @syntax <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @word 1 1 1 0 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @conv { + @syntax { - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @rules { + } - chk_call StoreCondition(cond) + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } @@ -73,16 +81,20 @@ @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + } + + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } @@ -92,16 +104,20 @@ @word 1 1 1 1 1 1 1 0 opc1(4) CRn(4) CRd(4) coproc(4) opc2(3) 0 CRm(4) - @syntax "cdp2" <cp> <undef_opc1> <creg_D> <creg_N> <creg_M> <undef_opc2> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + direct_CRd = UInt(CRd) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @conv { + } - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_D = CRegister(CRd) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @asm cdp cp direct_opc1 direct_CRd direct_CRn direct_CRm ?direct_opc2 } diff --git a/plugins/arm/v7/opdefs/clrex_A8832.d b/plugins/arm/v7/opdefs/clrex_A8832.d index 4f313f2..38dbca2 100644 --- a/plugins/arm/v7/opdefs/clrex_A8832.d +++ b/plugins/arm/v7/opdefs/clrex_A8832.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,35 @@ @title CLREX -@desc Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. +@id 31 + +@desc { + + Clear-Exclusive clears the local record of the executing processor that an address has had a request for an exclusive access. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 0 1 0 1 1 1 1 + @syntax { + + @asm clrex + + } + } @encoding (A1) { @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 + @syntax { + + @asm clrex + + } + } diff --git a/plugins/arm/v7/opdefs/clz_A8833.d b/plugins/arm/v7/opdefs/clz_A8833.d index d4fdac6..079e36d 100644 --- a/plugins/arm/v7/opdefs/clz_A8833.d +++ b/plugins/arm/v7/opdefs/clz_A8833.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CLZ -@desc Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. +@id 32 + +@desc { + + Count Leading Zeros returns the number of binary zero bits before the first binary one bit in a value. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm clz reg_D reg_M } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 0 1 1 0 1 1 1 1 Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm clz reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmn_A8834.d b/plugins/arm/v7/opdefs/cmn_A8834.d index fc0b19f..dbf0977 100644 --- a/plugins/arm/v7/opdefs/cmn_A8834.d +++ b/plugins/arm/v7/opdefs/cmn_A8834.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMN (immediate) -@desc Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 33 + +@desc { + + Compare Negative (immediate) adds a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) + } + + @asm cmn reg_N imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 1 1 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) - } + } + + @asm cmn reg_N imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmn_A8835.d b/plugins/arm/v7/opdefs/cmn_A8835.d index cd228de..deeef21 100644 --- a/plugins/arm/v7/opdefs/cmn_A8835.d +++ b/plugins/arm/v7/opdefs/cmn_A8835.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMN (register) -@desc Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 34 + +@desc { + + Compare Negative (register) adds a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 1 1 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm cmn reg_N reg_M } @@ -44,13 +54,17 @@ @word 1 1 1 0 1 0 1 1 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm cmn.w reg_N reg_M ?shift } @@ -60,19 +74,23 @@ @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm cmn reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmn_A8836.d b/plugins/arm/v7/opdefs/cmn_A8836.d index ad58482..44d414d 100644 --- a/plugins/arm/v7/opdefs/cmn_A8836.d +++ b/plugins/arm/v7/opdefs/cmn_A8836.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title CMN (register-shifted register) -@desc Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 35 + +@desc { + + Compare Negative (register-shifted register) adds a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 1 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm cmn reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmp_A8837.d b/plugins/arm/v7/opdefs/cmp_A8837.d index 76b7a76..bd35c57 100644 --- a/plugins/arm/v7/opdefs/cmp_A8837.d +++ b/plugins/arm/v7/opdefs/cmp_A8837.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMP (immediate) -@desc Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. +@id 36 + +@desc { + + Compare (immediate) subtracts an immediate value from a register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 0 1 0 1 Rn(3) imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { + + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) - @conv { + } - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) + @asm cmp reg_N imm32 } @@ -44,12 +54,16 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax ".W" <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm cmp.w reg_N imm32 } @@ -59,18 +73,22 @@ @word cond(4) 0 0 1 1 0 1 0 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm(imm12) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) - } + } + + @asm cmp reg_N imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmp_A8838.d b/plugins/arm/v7/opdefs/cmp_A8838.d index cd02543..4c1bf73 100644 --- a/plugins/arm/v7/opdefs/cmp_A8838.d +++ b/plugins/arm/v7/opdefs/cmp_A8838.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title CMP (register) -@desc Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. +@id 37 + +@desc { + + Compare (register) subtracts an optionally-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm cmp reg_N reg_M } @@ -44,12 +54,16 @@ @half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_N = Register(N:Rn) + reg_M = Register(Rm) - reg_N = Register(N:Rn) - reg_M = Register(Rm) + } + + @asm cmp reg_N reg_M } @@ -59,13 +73,17 @@ @word 1 1 1 0 1 0 1 1 1 0 1 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + @asm cmp.w reg_N reg_M ?shift } @@ -75,19 +93,23 @@ @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm cmp reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/cmp_A8839.d b/plugins/arm/v7/opdefs/cmp_A8839.d index 45ed0f9..4d8a8cf 100644 --- a/plugins/arm/v7/opdefs/cmp_A8839.d +++ b/plugins/arm/v7/opdefs/cmp_A8839.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title CMP (register-shifted register) -@desc Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. +@id 38 + +@desc { + + Compare (register-shifted register) subtracts a register-shifted register value from a register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 1 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm cmp reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/dbg_A8842.d b/plugins/arm/v7/opdefs/dbg_A8842.d index 62142f5..aa06c16 100644 --- a/plugins/arm/v7/opdefs/dbg_A8842.d +++ b/plugins/arm/v7/opdefs/dbg_A8842.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title DBG -@desc Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. +@id 41 + +@desc { + + Debug Hint provides a hint to debug and related systems. See their documentation for what use (if any) they make of this instruction. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 option(4) - @syntax <undef_option> + @syntax { + + @conv { - @conv { + direct_option = UInt(option) - undef_option = RawValue(option) + } + + @asm dbg direct_option } @@ -43,17 +53,21 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 option(4) - @syntax <undef_option> + @syntax { - @conv { + @conv { - undef_option = RawValue(option) + direct_option = UInt(option) - } + } + + @asm dbg direct_option + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/dmb_A8843.d b/plugins/arm/v7/opdefs/dmb_A8843.d index 34f053a..da9abdc 100644 --- a/plugins/arm/v7/opdefs/dmb_A8843.d +++ b/plugins/arm/v7/opdefs/dmb_A8843.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title DMB -@desc Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. +@id 42 + +@desc { + + Data Memory Barrier is a memory barrier that ensures the ordering of observations of memory accesses, see Data Memory Barrier (DMB) on page A3-151. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 1 option(4) - @syntax <limitation> + @syntax { - @conv { + @conv { - limitation = BarrierLimitation(option) + direct_option = UInt(option) + + } + + @asm dmb ?direct_option } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 1 option(4) - @syntax <limitation> + @syntax { + + @conv { + + direct_option = UInt(option) - @conv { + } - limitation = BarrierLimitation(option) + @asm dmb ?direct_option } diff --git a/plugins/arm/v7/opdefs/dsb_A8844.d b/plugins/arm/v7/opdefs/dsb_A8844.d index 512220c..87925ae 100644 --- a/plugins/arm/v7/opdefs/dsb_A8844.d +++ b/plugins/arm/v7/opdefs/dsb_A8844.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title DSB -@desc Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. +@id 43 + +@desc { + + Data Synchronization Barrier is a memory barrier that ensures the completion of memory accesses, see Data Synchronization Barrier (DSB) on page A3-152. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 1 1 1 1 1 1 0 0 0 1 1 1 1 0 1 0 0 option(4) - @syntax <limitation> + @syntax { - @conv { + @conv { - limitation = BarrierLimitation(option) + direct_option = UInt(option) + + } + + @asm dsb ?direct_option } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 1 0 1 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 1 0 0 option(4) - @syntax <limitation> + @syntax { + + @conv { + + direct_option = UInt(option) - @conv { + } - limitation = BarrierLimitation(option) + @asm dsb ?direct_option } diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/eor_A8846.d index 38dc858..3dc39cc 100644 --- a/plugins/arm/v7/opdefs/eor_A8846.d +++ b/plugins/arm/v7/opdefs/eor_A8846.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title EOR (immediate) -@desc Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 45 + +@desc { + + Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm eor ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm eors ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eor ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eors ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/eor_A8847.d b/plugins/arm/v7/opdefs/eor_A8847.d index 66643a1..4746ef8 100644 --- a/plugins/arm/v7/opdefs/eor_A8847.d +++ b/plugins/arm/v7/opdefs/eor_A8847.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title EOR (register) -@desc Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 46 + +@desc { + + Bitwise Exclusive OR (register) performs a bitwise Exclusive OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3) - @syntax "eors" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm eor ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm eor.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm eors.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm eor ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm eors ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/eor_A8848.d b/plugins/arm/v7/opdefs/eor_A8848.d index f38fa74..1248e43 100644 --- a/plugins/arm/v7/opdefs/eor_A8848.d +++ b/plugins/arm/v7/opdefs/eor_A8848.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title EOR (register-shifted register) -@desc Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. +@id 47 + +@desc { + + Bitwise Exclusive OR (register-shifted register) performs a bitwise Exclusive OR of a register value and a register-shifted register value. It writes the result to the destination register, and can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 0 0 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm eor ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm eors ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldr_A8862.d b/plugins/arm/v7/opdefs/ldr_A8862.d index 03df506..5672fe3 100644 --- a/plugins/arm/v7/opdefs/ldr_A8862.d +++ b/plugins/arm/v7/opdefs/ldr_A8862.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDR (immediate, Thumb) -@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 61 + +@desc { + + Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 0 1 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldr reg_T maccess } @@ -46,14 +56,18 @@ @half 1 0 0 1 1 Rt(3) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + } + + @asm ldr reg_T maccess } @@ -63,14 +77,18 @@ @word 1 1 1 1 1 0 0 0 1 1 0 1 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldr.w reg_T maccess } @@ -80,17 +98,69 @@ @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldr reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldr_A8863.d b/plugins/arm/v7/opdefs/ldr_A8863.d index 0d0ce1f..3e1b255 100644 --- a/plugins/arm/v7/opdefs/ldr_A8863.d +++ b/plugins/arm/v7/opdefs/ldr_A8863.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title LDR (immediate, ARM) -@desc Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 62 + +@desc { + + Load Register (immediate) calculates an address from a base register value and an immediate offset, loads a word from memory, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldr_A8864.d b/plugins/arm/v7/opdefs/ldr_A8864.d index 74afa2d..7c78df5 100644 --- a/plugins/arm/v7/opdefs/ldr_A8864.d +++ b/plugins/arm/v7/opdefs/ldr_A8864.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDR (literal) -@desc Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 63 + +@desc { + + Load Register (literal) calculates an address from the PC value and an immediate offset, loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 0 1 Rt(3) imm8(8) - @syntax <reg_T> <imm32> + @syntax { + + @conv { + + reg_T = Register(Rt) + imm32 = ZeroExtend(imm8:'00', 32) - @conv { + } - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) + @asm ldr reg_T imm32 } @@ -51,12 +61,16 @@ @word 1 1 1 1 1 0 0 0 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax ".W" <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) + + } + + @asm ldr.w reg_T imm32 } @@ -73,18 +87,22 @@ @word cond(4) 0 1 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - } + } + + @asm ldr reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldr_A8865.d b/plugins/arm/v7/opdefs/ldr_A8865.d index ebb4e09..e94eccb 100644 --- a/plugins/arm/v7/opdefs/ldr_A8865.d +++ b/plugins/arm/v7/opdefs/ldr_A8865.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDR (register, Thumb) -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. +@id 64 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. The Thumb form of LDR (register) does not support register writeback. + +} @encoding (t1) { @half 0 1 0 1 1 0 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldr reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, false, false) + @asm ldr.w reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d index b161043..6ba19f7 100644 --- a/plugins/arm/v7/opdefs/ldr_A8866.d +++ b/plugins/arm/v7/opdefs/ldr_A8866.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title LDR (register, ARM) -@desc Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. +@id 65 + +@desc { + + Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldr reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrb_A8867.d b/plugins/arm/v7/opdefs/ldrb_A8867.d index 2dea64e..cbfa097 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8867.d +++ b/plugins/arm/v7/opdefs/ldrb_A8867.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRB (immediate, Thumb) -@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 66 + +@desc { + + Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 1 1 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrb reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 0 1 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrb.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrb reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldrb_A8868.d b/plugins/arm/v7/opdefs/ldrb_A8868.d index 519c309..71c6c43 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8868.d +++ b/plugins/arm/v7/opdefs/ldrb_A8868.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title LDRB (immediate, ARM) -@desc Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 67 + +@desc { + + Load Register Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrb_A8869.d b/plugins/arm/v7/opdefs/ldrb_A8869.d index fb80049..37abb30 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8869.d +++ b/plugins/arm/v7/opdefs/ldrb_A8869.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRB (literal) -@desc Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 68 + +@desc { + + Load Register Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrb reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 1 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - } + } + + @asm ldrb reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrb_A8870.d b/plugins/arm/v7/opdefs/ldrb_A8870.d index 35f95ab..3324549 100644 --- a/plugins/arm/v7/opdefs/ldrb_A8870.d +++ b/plugins/arm/v7/opdefs/ldrb_A8870.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRB (register) -@desc Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 69 + +@desc { + + Load Register Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 1 1 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrb reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrb.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm ldrb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrbt_A8871.d b/plugins/arm/v7/opdefs/ldrbt_A8871.d index 0bf9c3c..f0d91fd 100644 --- a/plugins/arm/v7/opdefs/ldrbt_A8871.d +++ b/plugins/arm/v7/opdefs/ldrbt_A8871.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRBT -@desc Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 70 + +@desc { + + Load Register Byte Unprivileged loads a byte from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrbt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 1 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm ldrbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrd_A8872.d b/plugins/arm/v7/opdefs/ldrd_A8872.d index c73fdca..2b95b6d 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8872.d +++ b/plugins/arm/v7/opdefs/ldrd_A8872.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,24 +23,84 @@ @title LDRD (immediate) -@desc Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 71 + +@desc { + + Load Register Dual (immediate) calculates an address from a base register value and an immediate offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) Rt2(4) imm8(8) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { - @conv { + P == 1 + W == 1 - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess } @@ -50,24 +110,90 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { - @conv { + P == 1 + P == 1 && W == 0 - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrd_A8873.d b/plugins/arm/v7/opdefs/ldrd_A8873.d index 828e4a3..fd64c78 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8873.d +++ b/plugins/arm/v7/opdefs/ldrd_A8873.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LDRD (literal) -@desc Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. +@id 72 + +@desc { + + Load Register Dual (literal) calculates an address from the PC value and an immediate offset, loads two words from memory, and writes them to two registers. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) Rt2(4) imm8(8) - @syntax <reg_T> <reg_T2> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + imm32 = ZeroExtend(imm8:'00', 32) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - imm32 = ZeroExtend(imm8:'00', 32) + } + + @asm ldrd reg_T reg_T2 imm32 } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 U(1) 1 0 0 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <reg_T2> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrd reg_T reg_T2 imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrd_A8874.d b/plugins/arm/v7/opdefs/ldrd_A8874.d index ed055a6..abf8143 100644 --- a/plugins/arm/v7/opdefs/ldrd_A8874.d +++ b/plugins/arm/v7/opdefs/ldrd_A8874.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title LDRD (register) -@desc Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 73 + +@desc { + + Load Register Dual (register) calculates an address from a base register value and a register offset, loads two words from memory, and writes them to two registers. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrex_A8875.d b/plugins/arm/v7/opdefs/ldrex_A8875.d index b915061..b30ae86 100644 --- a/plugins/arm/v7/opdefs/ldrex_A8875.d +++ b/plugins/arm/v7/opdefs/ldrex_A8875.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDREX -@desc Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 74 + +@desc { + + Load Register Exclusive calculates an address from a base register value and an immediate offset, loads a word from memory, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 1 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + } + + @asm ldrex reg_T maccess } @@ -46,19 +56,24 @@ @word cond(4) 0 0 0 1 1 0 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) - } + } + + @asm ldrex reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrexb_A8876.d b/plugins/arm/v7/opdefs/ldrexb_A8876.d index e398ef2..8827994 100644 --- a/plugins/arm/v7/opdefs/ldrexb_A8876.d +++ b/plugins/arm/v7/opdefs/ldrexb_A8876.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LDREXB -@desc Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 75 + +@desc { + + Load Register Exclusive Byte derives an address from a base register value, loads a byte from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm ldrexb reg_T maccess } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm ldrexb reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrexd_A8877.d b/plugins/arm/v7/opdefs/ldrexd_A8877.d index 0188cb7..16f6ea6 100644 --- a/plugins/arm/v7/opdefs/ldrexd_A8877.d +++ b/plugins/arm/v7/opdefs/ldrexd_A8877.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDREXD -@desc Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 76 + +@desc { + + Load Register Exclusive Doubleword derives an address from a base register value, loads a 64-bit doubleword from memory, writes it to two registers and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) Rt2(4) 0 1 1 1 1 1 1 1 - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm ldrexd reg_T reg_T2 maccess } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 1 1 0 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm ldrexd reg_T reg_T2 maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrexh_A8878.d b/plugins/arm/v7/opdefs/ldrexh_A8878.d index 8e9366f..637a6c9 100644 --- a/plugins/arm/v7/opdefs/ldrexh_A8878.d +++ b/plugins/arm/v7/opdefs/ldrexh_A8878.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LDREXH -@desc Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 77 + +@desc { + + Load Register Exclusive Halfword derives an address from a base register value, loads a halfword from memory, zero-extends it to form a 32-bit word, writes it to a register and: • if the address has the Shared Memory attribute, marks the physical address as exclusive access for the executing processor in a global monitor • causes the executing processor to indicate an active exclusive access in the local monitor. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 1 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm ldrexh reg_T maccess } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 1 1 1 1 Rn(4) Rt(4) 1 1 1 1 1 0 0 1 1 1 1 1 - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm ldrexh reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrh_A8879.d b/plugins/arm/v7/opdefs/ldrh_A8879.d index 3b57bf8..4c21348 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8879.d +++ b/plugins/arm/v7/opdefs/ldrh_A8879.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRH (immediate, Thumb) -@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 78 + +@desc { + + Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 1 0 0 0 1 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrh reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm ldrh.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrh reg_T maccess } diff --git a/plugins/arm/v7/opdefs/ldrh_A8880.d b/plugins/arm/v7/opdefs/ldrh_A8880.d index f5f7ab0..17c2bee 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8880.d +++ b/plugins/arm/v7/opdefs/ldrh_A8880.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title LDRH (immediate, ARM) -@desc Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 79 + +@desc { + + Load Register Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrh_A8881.d b/plugins/arm/v7/opdefs/ldrh_A8881.d index 59005e4..3828d51 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8881.d +++ b/plugins/arm/v7/opdefs/ldrh_A8881.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRH (literal) -@desc Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 80 + +@desc { + + Load Register Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrh reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 1 1 1 1 Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrh reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrh_A8882.d b/plugins/arm/v7/opdefs/ldrh_A8882.d index 823bf24..3994a53 100644 --- a/plugins/arm/v7/opdefs/ldrh_A8882.d +++ b/plugins/arm/v7/opdefs/ldrh_A8882.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRH (register) -@desc Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 81 + +@desc { + + Load Register Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 1 0 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrh reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrh.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrht_A8883.d b/plugins/arm/v7/opdefs/ldrht_A8883.d index 8f8f015..d096d4e 100644 --- a/plugins/arm/v7/opdefs/ldrht_A8883.d +++ b/plugins/arm/v7/opdefs/ldrht_A8883.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRHT -@desc Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 82 + +@desc { + + Load Register Halfword Unprivileged loads a halfword from memory, zero-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrht reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm ldrht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsb_A8884.d b/plugins/arm/v7/opdefs/ldrsb_A8884.d index fc41134..05a0372 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8884.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8884.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSB (immediate) -@desc Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 83 + +@desc { + + Load Register Signed Byte (immediate) calculates an address from a base register value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 1 0 0 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess } @@ -46,17 +56,69 @@ @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrsb reg_T maccess } @@ -66,23 +128,87 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsb_A8885.d b/plugins/arm/v7/opdefs/ldrsb_A8885.d index 6cb1d34..46c7b35 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8885.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8885.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRSB (literal) -@desc Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 84 + +@desc { + + Load Register Signed Byte (literal) calculates an address from the PC value and an immediate offset, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 U(1) 0 0 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrsb reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrsb reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsb_A8886.d b/plugins/arm/v7/opdefs/ldrsb_A8886.d index 4a66278..e7da94f 100644 --- a/plugins/arm/v7/opdefs/ldrsb_A8886.d +++ b/plugins/arm/v7/opdefs/ldrsb_A8886.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSB (register) -@desc Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 85 + +@desc { + + Load Register Signed Byte (register) calculates an address from a base register value and an offset register value, loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 1 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrsb reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrsb.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsbt_A8887.d b/plugins/arm/v7/opdefs/ldrsbt_A8887.d index b545f32..3182168 100644 --- a/plugins/arm/v7/opdefs/ldrsbt_A8887.d +++ b/plugins/arm/v7/opdefs/ldrsbt_A8887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSBT -@desc Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 86 + +@desc { + + Load Register Signed Byte Unprivileged loads a byte from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 0 0 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrsbt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 0 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrsbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 0 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm ldrsbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsh_A8888.d b/plugins/arm/v7/opdefs/ldrsh_A8888.d index f01024c..a6f62b6 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8888.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8888.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSH (immediate) -@desc Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 87 + +@desc { + + Load Register Signed Halfword (immediate) calculates an address from a base register value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 1 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess } @@ -46,17 +56,69 @@ @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm ldrsh reg_T maccess } @@ -66,23 +128,87 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsh_A8889.d b/plugins/arm/v7/opdefs/ldrsh_A8889.d index 074cd5c..ae8e458 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8889.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8889.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title LDRSH (literal) -@desc Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. +@id 88 + +@desc { + + Load Register Signed Halfword (literal) calculates an address from the PC value and an immediate offset, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 U(1) 0 1 1 1 1 1 1 Rt(4) imm12(12) - @syntax <reg_T> <imm32> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + imm32 = ZeroExtend(imm12, 32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm12, 32) + } + + @asm ldrsh reg_T imm32 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 0 1 U(1) 1 0 1 1 1 1 1 Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <imm32> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - imm32 = ZeroExtend(imm4H:imm4L, 32) + reg_T = Register(Rt) + imm32 = ZeroExtend(imm4H:imm4L, 32) - } + } + + @asm ldrsh reg_T imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsh_A8890.d b/plugins/arm/v7/opdefs/ldrsh_A8890.d index eac6c09..6e4feeb 100644 --- a/plugins/arm/v7/opdefs/ldrsh_A8890.d +++ b/plugins/arm/v7/opdefs/ldrsh_A8890.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSH (register) -@desc Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 89 + +@desc { + + Load Register Signed Halfword (register) calculates an address from a base register value and an offset register value, loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 1 1 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm ldrsh reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm ldrsh.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm ldrsh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrsht_A8891.d b/plugins/arm/v7/opdefs/ldrsht_A8891.d index 355178b..2a00b3a 100644 --- a/plugins/arm/v7/opdefs/ldrsht_A8891.d +++ b/plugins/arm/v7/opdefs/ldrsht_A8891.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRSHT -@desc Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 90 + +@desc { + + Load Register Signed Halfword Unprivileged loads a halfword from memory, sign-extends it to form a 32-bit word, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRSHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 1 0 0 1 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrsht reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 1 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrsht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 1 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm ldrsht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ldrt_A8892.d b/plugins/arm/v7/opdefs/ldrt_A8892.d index e13f0e7..aa92cad 100644 --- a/plugins/arm/v7/opdefs/ldrt_A8892.d +++ b/plugins/arm/v7/opdefs/ldrt_A8892.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title LDRT -@desc Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 91 + +@desc { + + Load Register Unprivileged loads a word from memory, and writes it to a register. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. LDRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 1 0 1 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm ldrt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 0 1 1 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm ldrt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 0 1 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm ldrt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsl_A8894.d b/plugins/arm/v7/opdefs/lsl_A8894.d index 89924c6..e5e8dc8 100644 --- a/plugins/arm/v7/opdefs/lsl_A8894.d +++ b/plugins/arm/v7/opdefs/lsl_A8894.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LSL (immediate) -@desc Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 93 + +@desc { + + Logical Shift Left (immediate) shifts a register value left by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 0 0 imm5(5) Rm(3) Rd(3) - @syntax "lsls" <reg_D> <reg_M> <shift_imm> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('00', imm5) + } + + @asm lsl ?reg_D reg_M shift_n } @@ -45,21 +55,43 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('00', imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm3:imm2) + + } + + @asm lsl.w ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsls.w ?reg_D reg_M shift_n } @@ -69,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('00', imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsl ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('00', imm5) + + } + + @asm lsls ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsl_A8895.d b/plugins/arm/v7/opdefs/lsl_A8895.d index 4ac5ab6..8a7da49 100644 --- a/plugins/arm/v7/opdefs/lsl_A8895.d +++ b/plugins/arm/v7/opdefs/lsl_A8895.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title LSL (register) -@desc Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 94 + +@desc { + + Logical Shift Left (register) shifts a register value left by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 1 0 Rm(3) Rdn(3) - @syntax "lsls" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm lsl ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 0 0 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsl.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsls.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsl ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsls ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsr_A8896.d b/plugins/arm/v7/opdefs/lsr_A8896.d index acb9e25..3ee0473 100644 --- a/plugins/arm/v7/opdefs/lsr_A8896.d +++ b/plugins/arm/v7/opdefs/lsr_A8896.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title LSR (immediate) -@desc Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 95 + +@desc { + + Logical Shift Right (immediate) shifts a register value right by an immediate number of bits, shifting in zeros, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 0 1 imm5(5) Rm(3) Rd(3) - @syntax "lsrs" <reg_D> <reg_M> <shift_imm> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) - reg_D = Register(Rd) - reg_M = Register(Rm) - shift_imm = DecodeImmShift('01', imm5) + } + + @asm lsr ?reg_D reg_M shift_n } @@ -45,21 +55,43 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 0 1 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('01', imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm3:imm2) + + } + + @asm lsr.w ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsrs.w ?reg_D reg_M shift_n } @@ -69,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 0 1 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('01', imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsr ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('01', imm5) + + } + + @asm lsrs ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/lsr_A8897.d b/plugins/arm/v7/opdefs/lsr_A8897.d index 070a152..fa112ec 100644 --- a/plugins/arm/v7/opdefs/lsr_A8897.d +++ b/plugins/arm/v7/opdefs/lsr_A8897.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title LSR (register) -@desc Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 96 + +@desc { + + Logical Shift Right (register) shifts a register value right by a variable number of bits, shifting in zeros, and writes the result to the destination register. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 0 1 1 Rm(3) Rdn(3) - @syntax "lsrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm lsr ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 0 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm lsrs.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 0 1 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm lsrs ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mcr_A8898.d b/plugins/arm/v7/opdefs/mcr_A8898.d index f710d5d..b0ece52 100644 --- a/plugins/arm/v7/opdefs/mcr_A8898.d +++ b/plugins/arm/v7/opdefs/mcr_A8898.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,22 +23,32 @@ @title MCR, MCR2 -@desc Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. +@id 97 + +@desc { + + Move to Coprocessor from ARM core register passes the value of an ARM core register to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCR and MCR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCR pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -46,24 +56,22 @@ @encoding (A1) { - @word cond(4) 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @word 1 1 1 0 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @rules { + } - chk_call StoreCondition(cond) + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -73,16 +81,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + } + + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -92,16 +104,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 0 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mcr2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @conv { + } - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @asm mcr cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } diff --git a/plugins/arm/v7/opdefs/mcrr_A8899.d b/plugins/arm/v7/opdefs/mcrr_A8899.d index f643826..31e0f34 100644 --- a/plugins/arm/v7/opdefs/mcrr_A8899.d +++ b/plugins/arm/v7/opdefs/mcrr_A8899.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title MCRR, MCRR2 -@desc Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. +@id 98 + +@desc { + + Move to Coprocessor from two ARM core registers passes the values of two ARM core registers to a coprocessor. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MCRR and MCRR2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MCRR accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MCRR instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MCRR pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -45,23 +55,21 @@ @encoding (A1) { - @word cond(4) 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @word 1 1 1 0 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @rules { + } - chk_call StoreCondition(cond) + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -71,15 +79,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + } + + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -89,15 +101,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 0 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mcrr2" <cp> <undef_opc1> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @conv { + } - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_M = CRegister(CRm) + @asm mcrr cp direct_opc1 reg_T reg_T2 direct_CRm } diff --git a/plugins/arm/v7/opdefs/mla_A88100.d b/plugins/arm/v7/opdefs/mla_A88100.d index 5d4b4e4..654ae37 100644 --- a/plugins/arm/v7/opdefs/mla_A88100.d +++ b/plugins/arm/v7/opdefs/mla_A88100.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title MLA -@desc Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 99 + +@desc { + + Multiply Accumulate multiplies two register values, and adds a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. In an ARM instruction, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + @asm mla reg_D reg_N reg_M reg_A } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 0 0 1 S(1) Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } - @conv { + @asm mla reg_D reg_N reg_M reg_A - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm mlas reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mls_A88101.d b/plugins/arm/v7/opdefs/mls_A88101.d index 4d10be8..bdb9073 100644 --- a/plugins/arm/v7/opdefs/mls_A88101.d +++ b/plugins/arm/v7/opdefs/mls_A88101.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title MLS -@desc Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. +@id 100 + +@desc { + + Multiply and Subtract multiplies two register values, and subtracts the product from a third register value. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + } + + @asm mls reg_D reg_N reg_M reg_A } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 0 0 1 1 0 Rd(4) Ra(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - } + } + + @asm mls reg_D reg_N reg_M reg_A + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d index d96baab..e38442b 100644 --- a/plugins/arm/v7/opdefs/mov_A88102.d +++ b/plugins/arm/v7/opdefs/mov_A88102.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOV (immediate) -@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. +@id 101 + +@desc { + + Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (t1) { @half 0 0 1 0 0 Rd(3) imm8(8) - @syntax "movs" <reg_D> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm8, 32) + } + + @asm mov reg_D imm32 } @@ -44,20 +54,41 @@ @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm mov.w reg_D const } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm movs.w reg_D const } @@ -67,12 +98,16 @@ @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "movw" <reg_D> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) + } + + @asm movw reg_D imm32 } @@ -82,20 +117,53 @@ @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mov reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm movs reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -105,18 +173,22 @@ @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) - @syntax "movw" <reg_D> <imm32> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm32 = ZeroExtend(imm4:imm12, 32) + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) - } + } + + @asm movw reg_D imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mov_A88103.d b/plugins/arm/v7/opdefs/mov_A88103.d index cd3d75a..8a25367 100644 --- a/plugins/arm/v7/opdefs/mov_A88103.d +++ b/plugins/arm/v7/opdefs/mov_A88103.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOV (register, Thumb) -@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. +@id 102 + +@desc { + + Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (t1) { @half 0 1 0 0 0 1 1 0 D(1) Rm(4) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(D:Rd) + reg_M = Register(Rm) - reg_D = Register(D:Rd) - reg_M = Register(Rm) + } + + @asm mov reg_D reg_M } @@ -44,12 +54,16 @@ @half 0 0 0 0 0 0 0 0 0 0 Rm(3) Rd(3) - @syntax "movs" <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm movs reg_D reg_M } @@ -59,20 +73,41 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { + + S == 0 - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mov.w reg_D reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm movs.w reg_D reg_M } diff --git a/plugins/arm/v7/opdefs/mov_A88104.d b/plugins/arm/v7/opdefs/mov_A88104.d index d164983..9335076 100644 --- a/plugins/arm/v7/opdefs/mov_A88104.d +++ b/plugins/arm/v7/opdefs/mov_A88104.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,65 @@ @title MOV (register, ARM) -@desc Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. +@id 103 + +@desc { + + Move (register) copies a value from a register to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm mov reg_D reg_M - @conv { + @rules { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm movs reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/movt_A88106.d b/plugins/arm/v7/opdefs/movt_A88106.d index 265d008..58ba83c 100644 --- a/plugins/arm/v7/opdefs/movt_A88106.d +++ b/plugins/arm/v7/opdefs/movt_A88106.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MOVT -@desc Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. +@id 105 + +@desc { + + Move Top writes an immediate value to the top halfword of the destination register. It does not affect the contents of the bottom halfword. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm16> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + imm16 = UInt(imm4:i:imm3:imm8) - reg_D = Register(Rd) - imm16 = BuildImm16(imm4:i:imm3:imm8) + } + + @asm movt reg_D imm16 } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12) - @syntax <reg_D> <imm16> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - imm16 = BuildImm16(imm4:imm12) + reg_D = Register(Rd) + imm16 = UInt(imm4:imm12) - } + } + + @asm movt reg_D imm16 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mrc_A88107.d b/plugins/arm/v7/opdefs/mrc_A88107.d index fb9714c..9faecaa 100644 --- a/plugins/arm/v7/opdefs/mrc_A88107.d +++ b/plugins/arm/v7/opdefs/mrc_A88107.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,22 +23,32 @@ @title MRC, MRC2 -@desc Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. +@id 106 + +@desc { + + Move to ARM core register from Coprocessor causes a coprocessor to transfer a value to an ARM core register or to the condition flags. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1, opc2, CRn, and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRC and MRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRC pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) + + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -46,24 +56,22 @@ @encoding (A1) { - @word cond(4) 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - - @syntax <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @word 1 1 1 0 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @rules { + } - chk_call StoreCondition(cond) + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -73,16 +81,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + } + + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } @@ -92,16 +104,20 @@ @word 1 1 1 1 1 1 1 0 opc1(3) 1 CRn(4) Rt(4) coproc(4) opc2(3) 1 CRm(4) - @syntax "mrc2" <cp> <undef_opc1> <reg_T> <creg_N> <creg_M> <?undef_opc2> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + direct_CRn = UInt(CRn) + direct_CRm = UInt(CRm) + direct_opc2 = UInt(opc2) - @conv { + } - reg_T = Register(Rt) - cp = CoProcessor(coproc) - undef_opc1 = RawValue(opc1) - creg_N = CRegister(CRn) - creg_M = CRegister(CRm) - undef_opc2 = RawValue(opc2) + @asm mrc cp direct_opc1 reg_T direct_CRn direct_CRm ?direct_opc2 } diff --git a/plugins/arm/v7/opdefs/mrrc_A88108.d b/plugins/arm/v7/opdefs/mrrc_A88108.d index 026c0ef..d981e93 100644 --- a/plugins/arm/v7/opdefs/mrrc_A88108.d +++ b/plugins/arm/v7/opdefs/mrrc_A88108.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title MRRC, MRRC2 -@desc Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. +@id 107 + +@desc { + + Move to two ARM core registers from Coprocessor causes a coprocessor to transfer values to two ARM core registers. If no coprocessor can execute the instruction, an Undefined Instruction exception is generated. This is a generic coprocessor instruction. Some of the fields have no functionality defined by the architecture and are free for use by the coprocessor instruction set designer. These are the opc1 and CRm fields. However, coprocessors CP8-CP15 are reserved for use by ARM, and this manual defines the valid MRRC and MRRC2 instructions when coproc is in the range p8-p15. For more information see Coprocessor support on page A2-94. In an implementation that includes the Virtualization Extensions, MRRC accesses to system control registers can be trapped to Hyp mode, meaning that an attempt to execute an MRRC instruction in a Non-secure mode other than Hyp mode, that would be permitted in the absence of the Hyp trap controls, generates a Hyp Trap exception. For more information, see Traps to the hypervisor on page B1-1247. Note Because of the range of possible traps to Hyp mode, the MRRC pseudocode does not show these possible traps. + +} @encoding (T1) { @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) + + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -45,23 +55,21 @@ @encoding (A1) { - @word cond(4) 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - - @syntax <cp> <opc> <reg_T> <reg_T2> <creg_M> + @word 1 1 1 0 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @conv { + @syntax { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + @conv { - } + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @rules { + } - chk_call StoreCondition(cond) + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -71,15 +79,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { - @conv { + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + } + + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } @@ -89,15 +101,19 @@ @word 1 1 1 1 1 1 0 0 0 1 0 1 Rt2(4) Rt(4) coproc(4) opc1(4) CRm(4) - @syntax "mrrc2" <cp> <opc> <reg_T> <reg_T2> <creg_M> + @syntax { + + @conv { + + cp = CoProcessor(coproc) + direct_opc1 = UInt(opc1) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + direct_CRm = UInt(CRm) - @conv { + } - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - cp = CoProcessor(coproc) - opc = RawValue(opc1) - creg_M = CRegister(CRm) + @asm mrrc cp direct_opc1 reg_T reg_T2 direct_CRm } diff --git a/plugins/arm/v7/opdefs/mul_A88114.d b/plugins/arm/v7/opdefs/mul_A88114.d index fa250b7..25e6736 100644 --- a/plugins/arm/v7/opdefs/mul_A88114.d +++ b/plugins/arm/v7/opdefs/mul_A88114.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title MUL -@desc Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. +@id 113 + +@desc { + + Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination register. These 32 bits do not depend on whether the source register values are considered to be signed values or unsigned values. Optionally, it can update the condition flags based on the result. In the Thumb instruction set, this option is limited to only a few forms of the instruction. Use of this option adversely affects performance on many processor implementations. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 0 1 Rn(3) Rdm(3) - @syntax "muls" <reg_DM_1> <reg_N> <reg_DM_2> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_DM_1 = Register(Rdm) - reg_DM_2 = Register(Rdm) + reg_D = Register(Rdm) + reg_N = Register(Rn) + reg_M = Register(Rdm) + + } + + @asm mul reg_D reg_N ?reg_M } @@ -45,13 +55,17 @@ @word 1 1 1 1 1 0 1 1 0 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm mul reg_D reg_N ?reg_M } @@ -61,21 +75,55 @@ @word cond(4) 0 0 0 0 0 0 0 S(1) Rd(4) 0 0 0 0 Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @asm mul reg_D reg_N ?reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm muls reg_D reg_N ?reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/mvn_A88115.d index 2955439..c27b3a5 100644 --- a/plugins/arm/v7/opdefs/mvn_A88115.d +++ b/plugins/arm/v7/opdefs/mvn_A88115.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,53 @@ @title MVN (immediate) -@desc Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. +@id 114 + +@desc { + + Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm mvn reg_D const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm mvns reg_D const } @@ -51,20 +79,53 @@ @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvn reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvns reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mvn_A88116.d b/plugins/arm/v7/opdefs/mvn_A88116.d index 1f3f390..38ef06e 100644 --- a/plugins/arm/v7/opdefs/mvn_A88116.d +++ b/plugins/arm/v7/opdefs/mvn_A88116.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title MVN (register) -@desc Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. +@id 115 + +@desc { + + Bitwise NOT (register) writes the bitwise inverse of a register value to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3) - @syntax "mvns" <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm mvn reg_D reg_M } @@ -44,21 +54,43 @@ @word 1 1 1 0 1 0 1 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm mvn.w reg_D reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm mvns.w reg_D reg_M ?shift } @@ -68,21 +100,55 @@ @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvn reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm mvns reg_D reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/mvn_A88117.d b/plugins/arm/v7/opdefs/mvn_A88117.d index cc6ef16..6556020 100644 --- a/plugins/arm/v7/opdefs/mvn_A88117.d +++ b/plugins/arm/v7/opdefs/mvn_A88117.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,71 @@ @title MVN (register-shifted register) -@desc Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. +@id 116 + +@desc { + + Bitwise NOT (register-shifted register) writes the bitwise inverse of a register-shifted register value to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 1 1 S(1) 0 0 0 0 Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm mvn reg_D reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm mvns reg_D reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/nop_A88119.d b/plugins/arm/v7/opdefs/nop_A88119.d index 84c495a..1f9b82f 100644 --- a/plugins/arm/v7/opdefs/nop_A88119.d +++ b/plugins/arm/v7/opdefs/nop_A88119.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title NOP -@desc No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. +@id 118 + +@desc { + + No Operation does nothing. This instruction can be used for instruction alignment purposes. See Pre-UAL pseudo-instruction NOP on page AppxH-2472 for details of NOP before the introduction of UAL and the ARMv6K and ARMv6T2 architecture variants. Note The timing effects of including a NOP instruction in a program are not guaranteed. It can increase execution time, leave it unchanged, or even reduce it. Therefore, NOP instructions are not suitable for timing loops. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 + @syntax { + + @asm nop + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - @syntax ".W" + @syntax { + + @asm nop.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 - @rules { + @syntax { + + @asm nop + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/orn_A88120.d b/plugins/arm/v7/opdefs/orn_A88120.d index b823b6c..339dd5d 100644 --- a/plugins/arm/v7/opdefs/orn_A88120.d +++ b/plugins/arm/v7/opdefs/orn_A88120.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ORN (immediate) -@desc Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 119 + +@desc { + + Bitwise OR NOT (immediate) performs a bitwise (inclusive) OR of a register value and the complement of an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm orn ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } - if (setflags); chk_call ExtendKeyword("s") + @asm orns ?reg_D reg_N const } diff --git a/plugins/arm/v7/opdefs/orn_A88121.d b/plugins/arm/v7/opdefs/orn_A88121.d index f1523ec..5b32f94 100644 --- a/plugins/arm/v7/opdefs/orn_A88121.d +++ b/plugins/arm/v7/opdefs/orn_A88121.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title ORN (register) -@desc Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 120 + +@desc { + + Bitwise OR NOT (register) performs a bitwise (inclusive) OR of a register value and the complement of an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm orn ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") + @asm orns ?reg_D reg_N reg_M ?shift } diff --git a/plugins/arm/v7/opdefs/orr_A88122.d b/plugins/arm/v7/opdefs/orr_A88122.d index 766b5ee..8b159ad 100644 --- a/plugins/arm/v7/opdefs/orr_A88122.d +++ b/plugins/arm/v7/opdefs/orr_A88122.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ORR (immediate) -@desc Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 121 + +@desc { + + Bitwise OR (immediate) performs a bitwise (inclusive) OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm orr ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm orrs ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 1 1 0 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm orr ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm orrs ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/orr_A88123.d b/plugins/arm/v7/opdefs/orr_A88123.d index 2395c89..1549d28 100644 --- a/plugins/arm/v7/opdefs/orr_A88123.d +++ b/plugins/arm/v7/opdefs/orr_A88123.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ORR (register) -@desc Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 122 + +@desc { + + Bitwise OR (register) performs a bitwise (inclusive) OR of a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 1 0 0 Rm(3) Rdn(3) - @syntax "orrs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm orr ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 0 0 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm orr.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm orrs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm orr ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm orrs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/orr_A88124.d b/plugins/arm/v7/opdefs/orr_A88124.d index f4d78b9..85648ed 100644 --- a/plugins/arm/v7/opdefs/orr_A88124.d +++ b/plugins/arm/v7/opdefs/orr_A88124.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title ORR (register-shifted register) -@desc Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 123 + +@desc { + + Bitwise OR (register-shifted register) performs a bitwise (inclusive) OR of a register value and a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 1 0 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm orr ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm orrs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/pop_A88131.d b/plugins/arm/v7/opdefs/pop_A88131.d index 2dee09a..1169729 100644 --- a/plugins/arm/v7/opdefs/pop_A88131.d +++ b/plugins/arm/v7/opdefs/pop_A88131.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title POP (Thumb) -@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. +@id 130 + +@desc { + + Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +} @encoding (t1) { @half 1 0 1 1 1 1 0 P(1) register_list(8) - @syntax <registers> + @syntax { + + @conv { - @conv { + registers = RegList(P:'0000000':register_list) - registers = RegistersList(P:'0000000':register_list) + } + + @asm pop registers } @@ -49,11 +59,15 @@ @word 1 1 1 0 1 0 0 0 1 0 1 1 1 1 0 1 P(1) M(1) 0 register_list(13) - @syntax ".W" <registers> + @syntax { + + @conv { + + registers = RegList(P:M:'0':register_list) - @conv { + } - registers = RegistersList(P:M:'0':register_list) + @asm pop.w registers } @@ -69,11 +83,15 @@ @word 1 1 1 1 1 0 0 0 0 1 0 1 1 1 0 1 Rt(4) 1 0 1 1 0 0 0 0 0 1 0 0 - @syntax ".W" <registers> + @syntax { + + @conv { + + registers = SingleRegList(Rt) - @conv { + } - registers = RegistersList(1 << Rt) + @asm pop.w registers } diff --git a/plugins/arm/v7/opdefs/pop_A88132.d b/plugins/arm/v7/opdefs/pop_A88132.d index 27bbf3b..276bad4 100644 --- a/plugins/arm/v7/opdefs/pop_A88132.d +++ b/plugins/arm/v7/opdefs/pop_A88132.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,23 +23,33 @@ @title POP (ARM) -@desc Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. +@id 131 + +@desc { + + Pop Multiple Registers loads multiple registers from the stack, loading from consecutive memory locations starting at the address in SP, and updates SP to point just above the loaded data. + +} @encoding (A1) { @word cond(4) 1 0 0 0 1 0 1 1 1 1 0 1 register_list(16) - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList(register_list) + registers = RegList(register_list) - } + } - @rules { + @asm pop registers - chk_call StoreCondition(cond) + @rules { + + check g_arm_instruction_set_cond(cond) + + } } @@ -55,17 +65,21 @@ @word cond(4) 0 1 0 0 1 0 0 1 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList(1 << Rt) + registers = SingleRegList(Rt) - } + } + + @asm pop registers + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/push_A88133.d b/plugins/arm/v7/opdefs/push_A88133.d index 14fc3e9..aa7fe56 100644 --- a/plugins/arm/v7/opdefs/push_A88133.d +++ b/plugins/arm/v7/opdefs/push_A88133.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title PUSH -@desc Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. +@id 132 + +@desc { + + Push Multiple Registers stores multiple registers to the stack, storing to consecutive memory locations ending just below the address in SP, and updates SP to point to the start of the stored data. + +} @encoding (t1) { @half 1 0 1 1 0 1 0 M(1) register_list(8) - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList('0':M:'000000':register_list) + registers = RegList('0':M:'000000':register_list) + + } + + @asm push registers } @@ -43,11 +53,15 @@ @word 1 1 1 0 1 0 0 1 0 0 1 0 1 1 0 1 0 M(1) 0 register_list(13) - @syntax ".W" <registers> + @syntax { + + @conv { + + registers = RegList('0':M:'0':register_list) - @conv { + } - registers = RegistersList('0':M:'0':register_list) + @asm push.w registers } @@ -57,11 +71,15 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 1 1 0 1 Rt(4) 1 1 0 1 0 0 0 0 0 1 0 0 - @syntax ".W" <registers> + @syntax { - @conv { + @conv { - registers = Zeros(16) + registers = SingleRegList(Rt) + + } + + @asm push.w registers } @@ -71,17 +89,21 @@ @word cond(4) 1 0 0 1 0 0 1 0 1 1 0 1 register_list(16) - @syntax <registers> + @syntax { - @conv { + @conv { - registers = RegistersList(register_list) + registers = RegList(register_list) - } + } + + @asm push registers - @rules { + @rules { - chk_call StoreCondition(cond) + check g_arm_instruction_set_cond(cond) + + } } @@ -91,17 +113,21 @@ @word cond(4) 0 1 0 1 0 0 1 0 1 1 0 1 Rt(4) 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax <registers> + @syntax { - @conv { + @conv { - registers = Zeros(16) + registers = SingleRegList(Rt) - } + } + + @asm push registers + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qadd16_A88135.d b/plugins/arm/v7/opdefs/qadd16_A88135.d index 15af29d..bc7366e 100644 --- a/plugins/arm/v7/opdefs/qadd16_A88135.d +++ b/plugins/arm/v7/opdefs/qadd16_A88135.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QADD16 -@desc Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 134 + +@desc { + + Saturating Add 16 performs two 16-bit integer additions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qadd8_A88136.d b/plugins/arm/v7/opdefs/qadd8_A88136.d index a71b251..2128a39 100644 --- a/plugins/arm/v7/opdefs/qadd8_A88136.d +++ b/plugins/arm/v7/opdefs/qadd8_A88136.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QADD8 -@desc Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. +@id 135 + +@desc { + + Saturating Add 8 performs four 8-bit integer additions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qadd_A88134.d b/plugins/arm/v7/opdefs/qadd_A88134.d index f932983..37a22ba 100644 --- a/plugins/arm/v7/opdefs/qadd_A88134.d +++ b/plugins/arm/v7/opdefs/qadd_A88134.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QADD -@desc Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. +@id 133 + +@desc { + + Saturating Add adds two register values, saturates the result to the 32-bit signed integer range –231 to (231 – 1), and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qadd ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qadd ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qasx_A88137.d b/plugins/arm/v7/opdefs/qasx_A88137.d index 68251ca..5063f8e 100644 --- a/plugins/arm/v7/opdefs/qasx_A88137.d +++ b/plugins/arm/v7/opdefs/qasx_A88137.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QASX -@desc Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 136 + +@desc { + + Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qdadd_A88138.d b/plugins/arm/v7/opdefs/qdadd_A88138.d index c40cdcd..1f915b8 100644 --- a/plugins/arm/v7/opdefs/qdadd_A88138.d +++ b/plugins/arm/v7/opdefs/qdadd_A88138.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QDADD -@desc Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. +@id 137 + +@desc { + + Saturating Double and Add adds a doubled register value to another register value, and writes the result to the destination register. Both the doubling and the addition have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qdadd ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 1 0 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qdadd ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qdsub_A88139.d b/plugins/arm/v7/opdefs/qdsub_A88139.d index 87bd083..b726b6d 100644 --- a/plugins/arm/v7/opdefs/qdsub_A88139.d +++ b/plugins/arm/v7/opdefs/qdsub_A88139.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QDSUB -@desc Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. +@id 138 + +@desc { + + Saturating Double and Subtract subtracts a doubled register value from another register value, and writes the result to the destination register. Both the doubling and the subtraction have their results saturated to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1. If saturation occurs in either operation, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qdsub ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 1 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qdsub ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsax_A88140.d b/plugins/arm/v7/opdefs/qsax_A88140.d index df24cf8..1a9d204 100644 --- a/plugins/arm/v7/opdefs/qsax_A88140.d +++ b/plugins/arm/v7/opdefs/qsax_A88140.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSAX -@desc Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 139 + +@desc { + + Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer subtraction and one 16-bit addition, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsub16_A88142.d b/plugins/arm/v7/opdefs/qsub16_A88142.d index 5b2c96b..ca28003 100644 --- a/plugins/arm/v7/opdefs/qsub16_A88142.d +++ b/plugins/arm/v7/opdefs/qsub16_A88142.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSUB16 -@desc Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. +@id 141 + +@desc { + + Saturating Subtract 16 performs two 16-bit integer subtractions, saturates the results to the 16-bit signed integer range –215 ≤ x ≤ 215 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsub8_A88143.d b/plugins/arm/v7/opdefs/qsub8_A88143.d index 270a99d..8ec9a11 100644 --- a/plugins/arm/v7/opdefs/qsub8_A88143.d +++ b/plugins/arm/v7/opdefs/qsub8_A88143.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSUB8 -@desc Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. +@id 142 + +@desc { + + Saturating Subtract 8 performs four 8-bit integer subtractions, saturates the results to the 8-bit signed integer range –27 ≤ x ≤ 27 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm qsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/qsub_A88141.d b/plugins/arm/v7/opdefs/qsub_A88141.d index c60ec57..6a3b19f 100644 --- a/plugins/arm/v7/opdefs/qsub_A88141.d +++ b/plugins/arm/v7/opdefs/qsub_A88141.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title QSUB -@desc Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. +@id 140 + +@desc { + + Saturating Subtract subtracts one register value from another register value, saturates the result to the 32-bit signed integer range –231 ≤ x ≤ 231 – 1, and writes the result to the destination register. If saturation occurs, it sets the Q flag in the APSR. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm qsub ?reg_D reg_M reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 1 0 Rn(4) Rd(4) 0 0 0 0 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_M> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + reg_N = Register(Rn) - } + } + + @asm qsub ?reg_D reg_M reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rbit_A88144.d b/plugins/arm/v7/opdefs/rbit_A88144.d index 7f2bdb6..9d1c149 100644 --- a/plugins/arm/v7/opdefs/rbit_A88144.d +++ b/plugins/arm/v7/opdefs/rbit_A88144.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title RBIT -@desc Reverse Bits reverses the bit order in a 32-bit register. +@id 143 + +@desc { + + Reverse Bits reverses the bit order in a 32-bit register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) + } + + @asm rbit reg_D reg_M } @@ -44,18 +54,22 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm rbit reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rev16_A88146.d b/plugins/arm/v7/opdefs/rev16_A88146.d index 53b9a82..3bf8266 100644 --- a/plugins/arm/v7/opdefs/rev16_A88146.d +++ b/plugins/arm/v7/opdefs/rev16_A88146.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title REV16 -@desc Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. +@id 145 + +@desc { + + Byte-Reverse Packed Halfword reverses the byte order in each16-bit halfword of a 32-bit register. + +} @encoding (t1) { @half 1 0 1 1 1 0 1 0 0 1 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm rev16 reg_D reg_M } @@ -44,12 +54,16 @@ @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 1 Rm(4) - @syntax ".W" <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev16.w reg_D reg_M } @@ -59,18 +73,22 @@ @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm rev16 reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rev_A88145.d b/plugins/arm/v7/opdefs/rev_A88145.d index 2fe305d..0a96df9 100644 --- a/plugins/arm/v7/opdefs/rev_A88145.d +++ b/plugins/arm/v7/opdefs/rev_A88145.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title REV -@desc Byte-Reverse Word reverses the byte order in a 32-bit register. +@id 144 + +@desc { + + Byte-Reverse Word reverses the byte order in a 32-bit register. + +} @encoding (t1) { @half 1 0 1 1 1 0 1 0 0 0 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm rev reg_D reg_M } @@ -44,12 +54,16 @@ @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax ".W" <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rev.w reg_D reg_M } @@ -59,18 +73,22 @@ @word cond(4) 0 1 1 0 1 0 1 1 1 1 1 1 Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm rev reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/revsh_A88147.d b/plugins/arm/v7/opdefs/revsh_A88147.d index 551582c..bd290cc 100644 --- a/plugins/arm/v7/opdefs/revsh_A88147.d +++ b/plugins/arm/v7/opdefs/revsh_A88147.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title REVSH -@desc Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. +@id 146 + +@desc { + + Byte-Reverse Signed Halfword reverses the byte order in the lower 16-bit halfword of a 32-bit register, and sign-extends the result to 32 bits. + +} @encoding (t1) { @half 1 0 1 1 1 0 1 0 1 1 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm revsh reg_D reg_M } @@ -44,12 +54,16 @@ @word 1 1 1 1 1 0 1 0 1 0 0 1 Rm(4) 1 1 1 1 Rd(4) 1 0 1 1 Rm(4) - @syntax ".W" <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm revsh.w reg_D reg_M } @@ -59,18 +73,22 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_M = Register(Rm) - } + } + + @asm revsh reg_D reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ror_A88149.d b/plugins/arm/v7/opdefs/ror_A88149.d index 7e061c6..0717a95 100644 --- a/plugins/arm/v7/opdefs/ror_A88149.d +++ b/plugins/arm/v7/opdefs/ror_A88149.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title ROR (immediate) -@desc Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. +@id 148 + +@desc { + + Rotate Right (immediate) provides the value of the contents of a register rotated by a constant value. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm2(2) 1 1 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm3:imm2) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('11', imm3:imm2) + } + + @asm ror ?reg_D reg_M shift_n } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm3:imm2) + + } + + @asm rors ?reg_D reg_M shift_n } @@ -52,21 +81,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm5(5) 1 1 0 Rm(4) - @syntax <reg_D> <reg_M> <shift_imm> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift_imm = DecodeImmShift('11', imm5) + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm5) + + } + + @asm ror ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + shift_n = DecodeImmShiftAmount('11', imm5) + + } + + @asm rors ?reg_D reg_M shift_n + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ror_A88150.d b/plugins/arm/v7/opdefs/ror_A88150.d index c046bf7..57bbbb7 100644 --- a/plugins/arm/v7/opdefs/ror_A88150.d +++ b/plugins/arm/v7/opdefs/ror_A88150.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title ROR (register) -@desc Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. +@id 149 + +@desc { + + Rotate Right (register) provides the value of the contents of a register rotated by a variable number of bits. The bits that are rotated off the right end are inserted into the vacated bit positions on the left. The variable number of bits is read from the bottom byte of a register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 1 1 Rm(3) Rdn(3) - @syntax "rors" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm ror ?reg_D reg_N reg_M } @@ -44,21 +55,43 @@ @word 1 1 1 1 1 0 1 0 0 1 1 S(1) Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ror.w ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm rors.w ?reg_D reg_N reg_M } @@ -68,21 +101,55 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) Rm(4) 0 1 1 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm ror ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm rors ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rrx_A88151.d b/plugins/arm/v7/opdefs/rrx_A88151.d index 4debd42..d73570b 100644 --- a/plugins/arm/v7/opdefs/rrx_A88151.d +++ b/plugins/arm/v7/opdefs/rrx_A88151.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,53 @@ @title RRX -@desc Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. +@id 150 + +@desc { + + Rotate Right with Extend provides the value of the contents of a register shifted right by one place, with the Carry flag shifted into bit[31]. RRX can optionally update the condition flags based on the result. In that case, bit[0] is shifted into the Carry flag. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 0 1 0 S(1) 1 1 1 1 0 0 0 0 Rd(4) 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + } + + @asm rrx ?reg_D reg_M } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrxs ?reg_D reg_M } @@ -51,20 +79,53 @@ @word cond(4) 0 0 0 1 1 0 1 S(1) 0 0 0 0 Rd(4) 0 0 0 0 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_M> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrx ?reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + + } + + @asm rrxs ?reg_D reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsb_A88152.d b/plugins/arm/v7/opdefs/rsb_A88152.d index ea53373..0bf4eee 100644 --- a/plugins/arm/v7/opdefs/rsb_A88152.d +++ b/plugins/arm/v7/opdefs/rsb_A88152.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title RSB (immediate) -@desc Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 151 + +@desc { + + Reverse Subtract (immediate) subtracts a register value from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3) - @syntax "rsbs" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = Zeros(32) - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = Zeros(32) + } + + @asm rsb ?reg_D reg_N imm32 } @@ -45,21 +55,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm rsb.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm rsbs.w ?reg_D reg_N imm32 } @@ -69,21 +101,55 @@ @word cond(4) 0 0 1 0 0 1 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsb ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsbs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsb_A88153.d b/plugins/arm/v7/opdefs/rsb_A88153.d index f4a6d61..3f13bfa 100644 --- a/plugins/arm/v7/opdefs/rsb_A88153.d +++ b/plugins/arm/v7/opdefs/rsb_A88153.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title RSB (register) -@desc Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 152 + +@desc { + + Reverse Subtract (register) subtracts a register value from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 1 1 1 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm rsb ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm rsbs ?reg_D reg_N reg_M ?shift } @@ -53,22 +83,57 @@ @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsb ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsbs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsb_A88154.d b/plugins/arm/v7/opdefs/rsb_A88154.d index 9ccf559..74f084e 100644 --- a/plugins/arm/v7/opdefs/rsb_A88154.d +++ b/plugins/arm/v7/opdefs/rsb_A88154.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title RSB (register-shifted register) -@desc Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 153 + +@desc { + + Reverse Subtract (register-shifted register) subtracts a register value from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 0 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsb ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsbs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsc_A88155.d b/plugins/arm/v7/opdefs/rsc_A88155.d index fc5f8b6..dd8954c 100644 --- a/plugins/arm/v7/opdefs/rsc_A88155.d +++ b/plugins/arm/v7/opdefs/rsc_A88155.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,67 @@ @title RSC (immediate) -@desc Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 154 + +@desc { + + Reverse Subtract with Carry (immediate) subtracts a register value and the value of NOT (Carry flag) from an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 1 0 1 1 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rsc ?reg_D reg_N imm32 - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm rscs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsc_A88156.d b/plugins/arm/v7/opdefs/rsc_A88156.d index 70829cd..615aa99 100644 --- a/plugins/arm/v7/opdefs/rsc_A88156.d +++ b/plugins/arm/v7/opdefs/rsc_A88156.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title RSC (register) -@desc Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 155 + +@desc { + + Reverse Subtract with Carry (register) subtracts a register value and the value of NOT (Carry flag) from an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rsc ?reg_D reg_N reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm rscs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/rsc_A88157.d b/plugins/arm/v7/opdefs/rsc_A88157.d index 4fa276d..d95992b 100644 --- a/plugins/arm/v7/opdefs/rsc_A88157.d +++ b/plugins/arm/v7/opdefs/rsc_A88157.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title RSC (register-shifted register) -@desc Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 156 + +@desc { + + Reverse Subtract (register-shifted register) subtracts a register value and the value of NOT (Carry flag) from a register-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 1 1 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rsc ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm rscs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sadd16_A88158.d b/plugins/arm/v7/opdefs/sadd16_A88158.d index 51ad948..ee8d6d3 100644 --- a/plugins/arm/v7/opdefs/sadd16_A88158.d +++ b/plugins/arm/v7/opdefs/sadd16_A88158.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SADD16 -@desc Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 157 + +@desc { + + Signed Add 16 performs two 16-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sadd8_A88159.d b/plugins/arm/v7/opdefs/sadd8_A88159.d index 463c968..6c6c4a6 100644 --- a/plugins/arm/v7/opdefs/sadd8_A88159.d +++ b/plugins/arm/v7/opdefs/sadd8_A88159.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SADD8 -@desc Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 158 + +@desc { + + Signed Add 8 performs four 8-bit signed integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sasx_A88160.d b/plugins/arm/v7/opdefs/sasx_A88160.d index a0529cb..d655002 100644 --- a/plugins/arm/v7/opdefs/sasx_A88160.d +++ b/plugins/arm/v7/opdefs/sasx_A88160.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SASX -@desc Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. +@id 159 + +@desc { + + Signed Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one 16-bit integer addition and one 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbc_A88161.d b/plugins/arm/v7/opdefs/sbc_A88161.d index 4ea776a..d085e28 100644 --- a/plugins/arm/v7/opdefs/sbc_A88161.d +++ b/plugins/arm/v7/opdefs/sbc_A88161.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title SBC (immediate) -@desc Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 160 + +@desc { + + Subtract with Carry (immediate) subtracts an immediate value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + } + + @asm sbc ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sbcs ?reg_D reg_N imm32 } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 1 1 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sbc ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sbcs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbc_A88162.d b/plugins/arm/v7/opdefs/sbc_A88162.d index b6e660a..1ba7592 100644 --- a/plugins/arm/v7/opdefs/sbc_A88162.d +++ b/plugins/arm/v7/opdefs/sbc_A88162.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title SBC (register) -@desc Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 161 + +@desc { + + Subtract with Carry (register) subtracts an optionally-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 0 1 1 0 Rm(3) Rdn(3) - @syntax "sbcs" <reg_DN> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rdn) + reg_N = Register(Rdn) + reg_M = Register(Rm) - reg_DN = Register(Rdn) - reg_M = Register(Rm) + } + + @asm sbc ?reg_D reg_N reg_M } @@ -44,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 0 1 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sbc.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm sbcs.w ?reg_D reg_N reg_M ?shift } @@ -69,22 +103,57 @@ @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbc ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sbcs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbc_A88163.d b/plugins/arm/v7/opdefs/sbc_A88163.d index 0500edc..d534ed5 100644 --- a/plugins/arm/v7/opdefs/sbc_A88163.d +++ b/plugins/arm/v7/opdefs/sbc_A88163.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,73 @@ @title SBC (register-shifted register) -@desc Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 162 + +@desc { + + Subtract with Carry (register-shifted register) subtracts a register-shifted register value and the value of NOT (Carry flag) from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sbc ?reg_D reg_N reg_M shift - @conv { + @rules { - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) + + } + + @asm sbcs ?reg_D reg_N reg_M shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sbfx_A88164.d b/plugins/arm/v7/opdefs/sbfx_A88164.d index 486db3c..d834bca 100644 --- a/plugins/arm/v7/opdefs/sbfx_A88164.d +++ b/plugins/arm/v7/opdefs/sbfx_A88164.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,31 @@ @title SBFX -@desc Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. +@id 163 + +@desc { + + Signed Bit Field Extract extracts any number of adjacent bits at any position from a register, sign-extends them to 32 bits, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 0 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) + } + + @asm sbfx reg_D reg_N lsbit width } @@ -46,20 +57,25 @@ @word cond(4) 0 1 1 1 1 0 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - } + } + + @asm sbfx reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sdiv_A88165.d b/plugins/arm/v7/opdefs/sdiv_A88165.d index 19ebfa9..762b49a 100644 --- a/plugins/arm/v7/opdefs/sdiv_A88165.d +++ b/plugins/arm/v7/opdefs/sdiv_A88165.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SDIV -@desc Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. +@id 164 + +@desc { + + Signed Divide divides a 32-bit signed integer register value by a 32-bit signed integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sdiv ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 1 0 0 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sdiv ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sel_A88166.d b/plugins/arm/v7/opdefs/sel_A88166.d index cb32ed6..0239ee6 100644 --- a/plugins/arm/v7/opdefs/sel_A88166.d +++ b/plugins/arm/v7/opdefs/sel_A88166.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SEL -@desc Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. +@id 165 + +@desc { + + Select Bytes selects each byte of its result from either its first operand or its second operand, according to the values of the GE flags. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 1 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sel ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm sel ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/setend_A88167.d b/plugins/arm/v7/opdefs/setend_A88167.d index e549c50..ee07bd9 100644 --- a/plugins/arm/v7/opdefs/setend_A88167.d +++ b/plugins/arm/v7/opdefs/setend_A88167.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title SETEND -@desc Set Endianness writes a new value to ENDIANSTATE. +@id 166 + +@desc { + + Set Endianness writes a new value to ENDIANSTATE. + +} @encoding (t1) { @half 1 0 1 1 0 1 1 0 0 1 0 1 E(1) 0 0 0 - @syntax <set_bigend> + @syntax { - @conv { + @conv { - set_bigend = EndianState(E == '1') + endian_specifier = Endian(E) + + } + + @asm setend endian_specifier } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 E(1) 0 0 0 0 0 0 0 0 0 - @syntax <set_bigend> + @syntax { + + @conv { + + endian_specifier = Endian(E) - @conv { + } - set_bigend = EndianState(E == '1') + @asm setend endian_specifier } diff --git a/plugins/arm/v7/opdefs/sev_A88168.d b/plugins/arm/v7/opdefs/sev_A88168.d index 2bd9af4..cfbebe0 100644 --- a/plugins/arm/v7/opdefs/sev_A88168.d +++ b/plugins/arm/v7/opdefs/sev_A88168.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title SEV -@desc Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. +@id 167 + +@desc { + + Send Event is a hint instruction. It causes an event to be signaled to all processors in the multiprocessor system. For more information, see Wait For Event and Send Event on page B1-1199. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 1 0 0 0 0 0 0 + @syntax { + + @asm sev + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 - @syntax ".W" + @syntax { + + @asm sev.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 - @rules { + @syntax { + + @asm sev + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shadd16_A88169.d b/plugins/arm/v7/opdefs/shadd16_A88169.d index 22baa05..8453f4b 100644 --- a/plugins/arm/v7/opdefs/shadd16_A88169.d +++ b/plugins/arm/v7/opdefs/shadd16_A88169.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHADD16 -@desc Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. +@id 168 + +@desc { + + Signed Halving Add 16 performs two signed 16-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shadd8_A88170.d b/plugins/arm/v7/opdefs/shadd8_A88170.d index bfc3031..8623ac9 100644 --- a/plugins/arm/v7/opdefs/shadd8_A88170.d +++ b/plugins/arm/v7/opdefs/shadd8_A88170.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHADD8 -@desc Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. +@id 169 + +@desc { + + Signed Halving Add 8 performs four signed 8-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shasx_A88171.d b/plugins/arm/v7/opdefs/shasx_A88171.d index 71d241b..9a931cb 100644 --- a/plugins/arm/v7/opdefs/shasx_A88171.d +++ b/plugins/arm/v7/opdefs/shasx_A88171.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHASX -@desc Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. +@id 170 + +@desc { + + Signed Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer addition and one signed 16-bit subtraction, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shsax_A88172.d b/plugins/arm/v7/opdefs/shsax_A88172.d index 8794738..69369d5 100644 --- a/plugins/arm/v7/opdefs/shsax_A88172.d +++ b/plugins/arm/v7/opdefs/shsax_A88172.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHSAX -@desc Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. +@id 171 + +@desc { + + Signed Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one signed 16-bit integer subtraction and one signed 16-bit addition, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shsub16_A88173.d b/plugins/arm/v7/opdefs/shsub16_A88173.d index f7099f2..db35320 100644 --- a/plugins/arm/v7/opdefs/shsub16_A88173.d +++ b/plugins/arm/v7/opdefs/shsub16_A88173.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHSUB16 -@desc Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 172 + +@desc { + + Signed Halving Subtract 16 performs two signed 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/shsub8_A88174.d b/plugins/arm/v7/opdefs/shsub8_A88174.d index 99af65d..0d1b93c 100644 --- a/plugins/arm/v7/opdefs/shsub8_A88174.d +++ b/plugins/arm/v7/opdefs/shsub8_A88174.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SHSUB8 -@desc Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 173 + +@desc { + + Signed Halving Subtract 8 performs four signed 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 0 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm shsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 0 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm shsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlad_A88177.d b/plugins/arm/v7/opdefs/smlad_A88177.d index 3eabaa9..da02029 100644 --- a/plugins/arm/v7/opdefs/smlad_A88177.d +++ b/plugins/arm/v7/opdefs/smlad_A88177.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLAD -@desc Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. +@id 176 + +@desc { + + Signed Multiply Accumulate Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @asm smlad reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smladx reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 M(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + M == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlad reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smladx reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlal_A88178.d b/plugins/arm/v7/opdefs/smlal_A88178.d index 03da53c..0b79de9 100644 --- a/plugins/arm/v7/opdefs/smlal_A88178.d +++ b/plugins/arm/v7/opdefs/smlal_A88178.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title SMLAL -@desc Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 177 + +@desc { + + Signed Multiply Accumulate Long multiplies two signed 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm smlal reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 1 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm smlal reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlals reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlald_A88180.d b/plugins/arm/v7/opdefs/smlald_A88180.d index fa6a473..16353d2 100644 --- a/plugins/arm/v7/opdefs/smlald_A88180.d +++ b/plugins/arm/v7/opdefs/smlald_A88180.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLALD -@desc Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. +@id 179 + +@desc { + + Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @asm smlald reg_DLO reg_DHI reg_N reg_M } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaldx reg_DLO reg_DHI reg_N reg_M } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + M == 0 - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlald reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlaldx reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlsd_A88182.d b/plugins/arm/v7/opdefs/smlsd_A88182.d index d458fa8..5808518 100644 --- a/plugins/arm/v7/opdefs/smlsd_A88182.d +++ b/plugins/arm/v7/opdefs/smlsd_A88182.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLSD -@desc Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. +@id 181 + +@desc { + + Signed Multiply Subtract Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 32-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the accumulate operation overflows. Overflow cannot occur during the multiplications or subtraction. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 0 0 Rn(4) Ra(4) Rd(4) 0 0 0 M(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @asm smlsd reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsdx reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) Ra(4) Rm(4) 0 1 M(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + M == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - m_swap = (M == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsd reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smlsdx reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smlsld_A88183.d b/plugins/arm/v7/opdefs/smlsld_A88183.d index 9f64eed..995fb6f 100644 --- a/plugins/arm/v7/opdefs/smlsld_A88183.d +++ b/plugins/arm/v7/opdefs/smlsld_A88183.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMLSLD -@desc Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. +@id 182 + +@desc { + + Signed Multiply Subtract Long Dual performs two signed 16 × 16-bit multiplications. It adds the difference of the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 0 1 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @asm smlsld reg_DLO reg_DHI reg_N reg_M } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsldx reg_DLO reg_DHI reg_N reg_M } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 1 M(1) 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + M == 0 - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsld reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smlsldx reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smmla_A88184.d b/plugins/arm/v7/opdefs/smmla_A88184.d index a4d29b8..40bd005 100644 --- a/plugins/arm/v7/opdefs/smmla_A88184.d +++ b/plugins/arm/v7/opdefs/smmla_A88184.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMMLA -@desc Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. +@id 183 + +@desc { + + Signed Most Significant Word Multiply Accumulate multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and adds an accumulate value. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + R == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @asm smmla reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + R == 1 + + } - if (round); chk_call ExtendKeyword("r") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlar reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 0 0 R(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + R == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmla reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlar reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smmls_A88185.d b/plugins/arm/v7/opdefs/smmls_A88185.d index d59617b..9bc5396 100644 --- a/plugins/arm/v7/opdefs/smmls_A88185.d +++ b/plugins/arm/v7/opdefs/smmls_A88185.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,57 @@ @title SMMLS -@desc Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. +@id 184 + +@desc { + + Signed Most Significant Word Multiply Subtract multiplies two signed 32-bit values, subtracts the result from a 32-bit accumulate value that is shifted left by 32 bits, and extracts the most significant 32 bits of the result of that subtraction. Optionally, the instruction can specify that the result of the instruction is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the result of the subtraction before the high word is extracted. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 1 0 Rn(4) Ra(4) Rd(4) 0 0 0 R(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { + + R == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @asm smmls reg_D reg_N reg_M reg_A } - @rules { + @syntax { + + @assert { + + R == 1 + + } - if (round); chk_call ExtendKeyword("r") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlsr reg_D reg_N reg_M reg_A } @@ -53,22 +83,57 @@ @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) Ra(4) Rm(4) 1 1 R(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @assert { - @conv { + R == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) - round = (R == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmls reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) + + } + + @asm smmlsr reg_D reg_N reg_M reg_A + + @rules { + + check g_arm_instruction_set_cond(cond) - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smmul_A88186.d b/plugins/arm/v7/opdefs/smmul_A88186.d index e02ca52..44a8b9b 100644 --- a/plugins/arm/v7/opdefs/smmul_A88186.d +++ b/plugins/arm/v7/opdefs/smmul_A88186.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title SMMUL -@desc Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. +@id 185 + +@desc { + + Signed Most Significant Word Multiply multiplies two signed 32-bit values, extracts the most significant 32 bits of the result, and writes those bits to the destination register. Optionally, the instruction can specify that the result is rounded instead of being truncated. In this case, the constant 0x80000000 is added to the product before the high word is extracted. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 R(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + R == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - round = (R == '1') + } + + @asm smmul ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + R == 1 + + } - if (round); chk_call ExtendKeyword("r") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmulr ?reg_D reg_N reg_M } @@ -52,21 +81,55 @@ @word cond(4) 0 1 1 1 0 1 0 1 Rd(4) 1 1 1 1 Rm(4) 0 0 R(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + R == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - round = (R == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmul ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + R == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smmulr ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (round); chk_call ExtendKeyword("r") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smuad_A88187.d b/plugins/arm/v7/opdefs/smuad_A88187.d index 324e257..a10c279 100644 --- a/plugins/arm/v7/opdefs/smuad_A88187.d +++ b/plugins/arm/v7/opdefs/smuad_A88187.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title SMUAD -@desc Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. +@id 186 + +@desc { + + Signed Dual Multiply Add performs two signed 16 × 16-bit multiplications. It adds the products together, and writes the result to the destination register. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. This instruction sets the Q flag if the addition overflows. The multiplications cannot overflow. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 0 0 M(1) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { + + M == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @asm smuad ?reg_D reg_N reg_M } - @rules { + @syntax { + + @assert { + + M == 1 + + } - if (m_swap); chk_call ExtendKeyword("x") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuadx ?reg_D reg_N reg_M } @@ -52,21 +81,55 @@ @word cond(4) 0 1 1 1 0 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 M(1) 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @assert { - @conv { + M == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - m_swap = (M == '1') + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuad ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + M == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smuadx ?reg_D reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (m_swap); chk_call ExtendKeyword("x") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/smull_A88189.d b/plugins/arm/v7/opdefs/smull_A88189.d index 5ab1c54..c0a186e 100644 --- a/plugins/arm/v7/opdefs/smull_A88189.d +++ b/plugins/arm/v7/opdefs/smull_A88189.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title SMULL -@desc Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 188 + +@desc { + + Signed Multiply Long multiplies two 32-bit signed values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 0 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm smull reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 1 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm smull reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm smulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/str_A88203.d b/plugins/arm/v7/opdefs/str_A88203.d index e3feaf7..f8b4958 100644 --- a/plugins/arm/v7/opdefs/str_A88203.d +++ b/plugins/arm/v7/opdefs/str_A88203.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STR (immediate, Thumb) -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 202 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 0 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -46,14 +56,18 @@ @half 1 0 0 1 0 Rt(3) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(13) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - imm32 = ZeroExtend(imm8:'00', 32) - SP = Register(13) - mem_access = MakeMemoryAccess(SP, imm32, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -63,14 +77,18 @@ @word 1 1 1 1 1 0 0 0 1 1 0 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm str.w reg_T maccess } @@ -80,17 +98,69 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm str reg_T maccess } diff --git a/plugins/arm/v7/opdefs/str_A88204.d b/plugins/arm/v7/opdefs/str_A88204.d index d780ae3..0818631 100644 --- a/plugins/arm/v7/opdefs/str_A88204.d +++ b/plugins/arm/v7/opdefs/str_A88204.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title STR (immediate, ARM) -@desc Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 203 + +@desc { + + Store Register (immediate) calculates an address from a base register value and an immediate offset, and stores a word from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/str_A88205.d b/plugins/arm/v7/opdefs/str_A88205.d index 55f154c..e4eb6fb 100644 --- a/plugins/arm/v7/opdefs/str_A88205.d +++ b/plugins/arm/v7/opdefs/str_A88205.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STR (register) -@desc Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 204 + +@desc { + + Store Register (register) calculates an address from a base register value and an offset register value, stores a word from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 0 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm str reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm str.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm str reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strb_A88206.d b/plugins/arm/v7/opdefs/strb_A88206.d index 2caf94c..ed21cc9 100644 --- a/plugins/arm/v7/opdefs/strb_A88206.d +++ b/plugins/arm/v7/opdefs/strb_A88206.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRB (immediate, Thumb) -@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 205 + +@desc { + + Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 1 1 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strb reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 0 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strb.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm strb reg_T maccess } diff --git a/plugins/arm/v7/opdefs/strb_A88207.d b/plugins/arm/v7/opdefs/strb_A88207.d index 4e893fb..e495ea8 100644 --- a/plugins/arm/v7/opdefs/strb_A88207.d +++ b/plugins/arm/v7/opdefs/strb_A88207.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title STRB (immediate, ARM) -@desc Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 206 + +@desc { + + Store Register Byte (immediate) calculates an address from a base register value and an immediate offset, and stores a byte from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 1 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strb_A88208.d b/plugins/arm/v7/opdefs/strb_A88208.d index 36f6134..11d5931 100644 --- a/plugins/arm/v7/opdefs/strb_A88208.d +++ b/plugins/arm/v7/opdefs/strb_A88208.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRB (register) -@desc Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. +@id 207 + +@desc { + + Store Register Byte (register) calculates an address from a base register value and an offset register value, and stores a byte from a register to memory. The offset register value can optionally be shifted. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 1 0 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm strb reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm strb.w reg_T maccess } @@ -64,24 +78,90 @@ @word cond(4) 0 1 1 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) + + } + + @asm strb reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strbt_A88209.d b/plugins/arm/v7/opdefs/strbt_A88209.d index 2bcb260..034b4ad 100644 --- a/plugins/arm/v7/opdefs/strbt_A88209.d +++ b/plugins/arm/v7/opdefs/strbt_A88209.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRBT -@desc Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 208 + +@desc { + + Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm strbt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm strbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm strbt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strd_A88210.d b/plugins/arm/v7/opdefs/strd_A88210.d index 437bcb3..93608eb 100644 --- a/plugins/arm/v7/opdefs/strd_A88210.d +++ b/plugins/arm/v7/opdefs/strd_A88210.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,24 +23,84 @@ @title STRD (immediate) -@desc Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 209 + +@desc { + + Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { - @conv { + P == 1 + W == 1 - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess } @@ -50,24 +110,90 @@ @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { - @conv { + P == 1 + P == 1 && W == 0 - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strd_A88211.d b/plugins/arm/v7/opdefs/strd_A88211.d index b30d4a5..1f0dc14 100644 --- a/plugins/arm/v7/opdefs/strd_A88211.d +++ b/plugins/arm/v7/opdefs/strd_A88211.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,30 +23,102 @@ @title STRD (register) -@desc Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 210 + +@desc { + + Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strd reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strex_A88212.d b/plugins/arm/v7/opdefs/strex_A88212.d index 65a7dfe..0631064 100644 --- a/plugins/arm/v7/opdefs/strex_A88212.d +++ b/plugins/arm/v7/opdefs/strex_A88212.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title STREX -@desc Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 211 + +@desc { + + Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8:'00', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + } + + @asm strex reg_D reg_T maccess } @@ -47,20 +57,25 @@ @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = Zeros(32) + maccess = MemAccessOffset(reg_N, imm32) - } + } + + @asm strex reg_D reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strexb_A88213.d b/plugins/arm/v7/opdefs/strexb_A88213.d index 0197d6c..af0a005 100644 --- a/plugins/arm/v7/opdefs/strexb_A88213.d +++ b/plugins/arm/v7/opdefs/strexb_A88213.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STREXB -@desc Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 212 + +@desc { + + Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm strexb reg_D reg_T maccess } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm strexb reg_D reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strexd_A88214.d b/plugins/arm/v7/opdefs/strexd_A88214.d index 2867cea..3da8f64 100644 --- a/plugins/arm/v7/opdefs/strexd_A88214.d +++ b/plugins/arm/v7/opdefs/strexd_A88214.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,21 +23,31 @@ @title STREXD -@desc Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 213 + +@desc { + + Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) - @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm strexd reg_D reg_T reg_T2 maccess } @@ -47,21 +57,25 @@ @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_T2 = NextRegister(reg_T) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = NextRegister(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm strexd reg_D reg_T reg_T2 maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strexh_A88215.d b/plugins/arm/v7/opdefs/strexh_A88215.d index 4ca0b6f..4341851 100644 --- a/plugins/arm/v7/opdefs/strexh_A88215.d +++ b/plugins/arm/v7/opdefs/strexh_A88215.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STREXH -@desc Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. +@id 214 + +@desc { + + Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (T1) { @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + } + + @asm strexh reg_D reg_T maccess } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) - @syntax <reg_D> <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_T = Register(Rt) - reg_N = Register(Rn) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) - } + } + + @asm strexh reg_D reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strh_A88216.d b/plugins/arm/v7/opdefs/strh_A88216.d index 624b483..05b7b12 100644 --- a/plugins/arm/v7/opdefs/strh_A88216.d +++ b/plugins/arm/v7/opdefs/strh_A88216.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRH (immediate, Thumb) -@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 215 + +@desc { + + Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm5:'0', 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strh reg_T maccess } @@ -46,14 +56,18 @@ @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessOffset(reg_N, imm32) - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + } + + @asm strh.w reg_T maccess } @@ -63,17 +77,69 @@ @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + + @syntax { + + @assert { + + P == 1 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + } + + @syntax { + + @assert { + + P == 0 + W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - index = (P == '1') - add = (U == '1') - wback = (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + @asm strh reg_T maccess } diff --git a/plugins/arm/v7/opdefs/strh_A88217.d b/plugins/arm/v7/opdefs/strh_A88217.d index 3b5f97c..5b7fa38 100644 --- a/plugins/arm/v7/opdefs/strh_A88217.d +++ b/plugins/arm/v7/opdefs/strh_A88217.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,29 +23,99 @@ @title STRH (immediate, ARM) -@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. +@id 216 + +@desc { + + Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (A1) { @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessOffset(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { - @conv { + @assert { - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm4H:imm4L, 32) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPreIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strh_A88218.d b/plugins/arm/v7/opdefs/strh_A88218.d index 1e9dc1f..149ba8d 100644 --- a/plugins/arm/v7/opdefs/strh_A88218.d +++ b/plugins/arm/v7/opdefs/strh_A88218.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRH (register) -@desc Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. +@id 217 + +@desc { + + Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +} @encoding (t1) { @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { - @conv { + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + } + + @asm strh reg_T maccess } @@ -46,15 +56,19 @@ @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) - @syntax ".W" <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = FixedShift(SRType_LSL, imm2) + maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(0, imm2) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + @asm strh.w reg_T maccess } @@ -64,23 +78,87 @@ @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { + + @assert { + + P == 1 + P == 1 && W == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessOffset(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + + @syntax { + + @assert { + + P == 1 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPreIndexed(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - index = (P == '1') - add = (U == '1') - wback = (P == '0') || (W == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + } } - @rules { + @syntax { + + @assert { + + P == 0 + P == 0 || W == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) + + } + + @asm strh reg_T maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strht_A88219.d b/plugins/arm/v7/opdefs/strht_A88219.d index 3811572..f7fb37f 100644 --- a/plugins/arm/v7/opdefs/strht_A88219.d +++ b/plugins/arm/v7/opdefs/strht_A88219.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRHT -@desc Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. +@id 218 + +@desc { + + Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm strht reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm4H:imm4L, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm strht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,21 +83,24 @@ @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + maccess = MemAccessPostIndexed(reg_N, reg_M) - } + } + + @asm strht reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/strt_A88220.d b/plugins/arm/v7/opdefs/strt_A88220.d index 794a0fa..dd1c03a 100644 --- a/plugins/arm/v7/opdefs/strt_A88220.d +++ b/plugins/arm/v7/opdefs/strt_A88220.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title STRT -@desc Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. +@id 219 + +@desc { + + Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +} @encoding (T1) { @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) - @syntax <reg_T> <mem_access> + @syntax { + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + maccess = MemAccessOffset(reg_N, imm32) - @conv { + } - reg_T = Register(Rt) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm8, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + @asm strt reg_T maccess } @@ -46,21 +56,24 @@ @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - add = (U == '1') - imm32 = ZeroExtend(imm12, 32) - mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + maccess = MemAccessPostIndexed(reg_N, imm32) - } + } + + @asm strt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } @@ -70,22 +83,25 @@ @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_T> <mem_access> + @syntax { - @conv { + @conv { - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - add = (U == '1') - shift = DecodeImmShift(type, imm5) - mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - } + } + + @asm strt reg_T maccess + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88221.d b/plugins/arm/v7/opdefs/sub_A88221.d index 41ce6b3..365943c 100644 --- a/plugins/arm/v7/opdefs/sub_A88221.d +++ b/plugins/arm/v7/opdefs/sub_A88221.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (immediate, Thumb) -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 220 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 1 1 imm3(3) Rn(3) Rd(3) - @syntax "subs" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm3, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(imm3, 32) + @asm sub ?reg_D reg_N imm32 } @@ -45,12 +55,17 @@ @half 0 0 1 1 1 Rdn(3) imm8(8) - @syntax "subs" <reg_DN> <imm32> + @syntax { - @conv { + @conv { - reg_DN = Register(Rdn) - imm32 = ZeroExtend(imm8, 32) + reg_D = Register(Rdn) + reg_N = Register(Rdn) + imm32 = ZeroExtend(imm8, 32) + + } + + @asm sub ?reg_D reg_N imm32 } @@ -60,21 +75,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_N imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_N imm32 } @@ -84,13 +121,17 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax "subw" <reg_D> <reg_N> <imm32> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ZeroExtend(i:imm3:imm8, 32) - @conv { + } - reg_D = Register(Rd) - reg_N = Register(Rn) - imm32 = ZeroExtend(i:imm3:imm8, 32) + @asm subw ?reg_D reg_N imm32 } diff --git a/plugins/arm/v7/opdefs/sub_A88222.d b/plugins/arm/v7/opdefs/sub_A88222.d index ef326b8..289d045 100644 --- a/plugins/arm/v7/opdefs/sub_A88222.d +++ b/plugins/arm/v7/opdefs/sub_A88222.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,27 +23,67 @@ @title SUB (immediate, ARM) -@desc This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 221 + +@desc { + + This instruction subtracts an immediate value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 1 0 0 1 0 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_N imm32 - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_N imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88223.d b/plugins/arm/v7/opdefs/sub_A88223.d index a629250..b3b9ef6 100644 --- a/plugins/arm/v7/opdefs/sub_A88223.d +++ b/plugins/arm/v7/opdefs/sub_A88223.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (register) -@desc This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 222 + +@desc { + + This instruction subtracts an optionally-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (t1) { @half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3) - @syntax "subs" <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm sub ?reg_D reg_N reg_M } @@ -45,22 +55,45 @@ @word 1 1 1 0 1 0 1 1 1 0 1 S(1) Rn(4) 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm sub.w ?reg_D reg_N reg_M ?shift } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @asm subs.w ?reg_D reg_N reg_M ?shift } @@ -70,22 +103,57 @@ @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @assert { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm sub ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm subs ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88225.d b/plugins/arm/v7/opdefs/sub_A88225.d index dc54c6b..96708b9 100644 --- a/plugins/arm/v7/opdefs/sub_A88225.d +++ b/plugins/arm/v7/opdefs/sub_A88225.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title SUB (SP minus immediate) -@desc This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. +@id 224 + +@desc { + + This instruction subtracts an immediate value from the SP value, and writes the result to the destination register. + +} @encoding (t1) { @half 1 0 1 1 0 0 0 0 1 imm7(7) - @syntax <SP_0> <SP_1> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(13) + reg_SP = Register(13) + imm32 = ZeroExtend(imm7:'00', 32) - imm32 = ZeroExtend(imm7:'00', 32) - SP_0 = Register(13) - SP_1 = Register(13) + } + + @asm sub ?reg_D reg_SP imm32 } @@ -45,21 +55,43 @@ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } - @conv { + @conv { - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm(i:imm3:imm8) - SP = Register(13) + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm sub.w ?reg_D reg_SP imm32 } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") - chk_call ExtendKeyword(".w") + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ThumbExpandImm(i:imm3:imm8) + + } + + @asm subs.w ?reg_D reg_SP imm32 } @@ -69,13 +101,17 @@ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8) - @syntax "subw" <reg_D> <SP> <imm32> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ZeroExtend(i:imm3:imm8, 32) - reg_D = Register(Rd) - imm32 = ZeroExtend(i:imm3:imm8, 32) - SP = Register(13) + } + + @asm subw ?reg_D reg_SP imm32 } @@ -85,21 +121,55 @@ @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12) - @syntax <reg_D> <SP> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm sub ?reg_D reg_SP imm32 + + @rules { - @conv { + check g_arm_instruction_set_cond(cond) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm(imm12) - SP = Register(13) + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_SP = Register(13) + imm32 = ARMExpandImm(imm12) + + } + + @asm subs ?reg_D reg_SP imm32 + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/sub_A88226.d b/plugins/arm/v7/opdefs/sub_A88226.d deleted file mode 100644 index 02ecada..0000000 --- a/plugins/arm/v7/opdefs/sub_A88226.d +++ /dev/null @@ -1,76 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title SUB (SP minus register) - -@desc This instruction subtracts an optionally-shifted register value from the SP value, and writes the result to the destination register. - -@encoding (T1) { - - @word 1 1 1 0 1 0 1 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm2(2) type(2) Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm3:imm2) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - - } - -} - -@encoding (A1) { - - @word cond(4) 0 0 0 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm5(5) type(2) 0 Rm(4) - - @syntax <reg_D> <SP> <reg_M> <?shift> - - @conv { - - reg_D = Register(Rd) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) - SP = Register(13) - - } - - @rules { - - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - - } - -} - diff --git a/plugins/arm/v7/opdefs/svc_A88228.d b/plugins/arm/v7/opdefs/svc_A88228.d index be48545..0ddc95f 100644 --- a/plugins/arm/v7/opdefs/svc_A88228.d +++ b/plugins/arm/v7/opdefs/svc_A88228.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title SVC (previously SWI) -@desc Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. +@id 227 + +@desc { + + Supervisor Call, previously called Software Interrupt, causes a Supervisor Call exception. For more information, see Supervisor Call (SVC) exception on page B1-1209. Software can use this instruction as a call to an operating system to provide a service. In the following cases, the Supervisor Call exception generated by the SVC instruction is taken to Hyp mode: • If the SVC is executed in Hyp mode. • If HCR.TGE is set to 1, and the SVC is executed in Non-secure User mode. For more information, see Supervisor Call exception, when HCR.TGE is set to 1 on page B1-1191 In these cases, the HSR identifies that the exception entry was caused by a Supervisor Call exception, EC value 0x11, see Use of the HSR on page B3-1424. The immediate field in the HSR: • if the SVC is unconditional: — for the Thumb instruction, is the zero-extended value of the imm8 field — for the ARM instruction, is the least-significant 16 bits the imm24 field • if the SVC is conditional, is UNKNOWN. + +} @encoding (t1) { @half 1 1 0 1 1 1 1 1 imm8(8) - @syntax <imm32> + @syntax { + + @conv { - @conv { + imm32 = ZeroExtend(imm8, 32) - imm32 = ZeroExtend(imm8, 32) + } + + @asm svc imm32 } @@ -43,17 +53,21 @@ @word cond(4) 1 1 1 1 imm24(24) - @syntax <imm32> + @syntax { - @conv { + @conv { - imm32 = ZeroExtend(imm24, 32) + imm32 = ZeroExtend(imm24, 32) - } + } + + @asm svc imm32 + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/swp_A88229.d b/plugins/arm/v7/opdefs/swp_A88229.d index 2e39015..b901462 100644 --- a/plugins/arm/v7/opdefs/swp_A88229.d +++ b/plugins/arm/v7/opdefs/swp_A88229.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title SWP, SWPB -@desc SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rt2> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rt2> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — LDREXB/STREXB in preference to SWPB. — • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. +@id 228 + +@desc { + + SWP (Swap) swaps a word between registers and memory. SWP loads a word from the memory address given by the value of register <Rn>. The value of register <Rt2> is then stored to the memory address given by the value of <Rn>, and the original loaded value is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the register and the value at the memory address. SWPB (Swap Byte) swaps a byte between registers and memory. SWPB loads a byte from the memory address given by the value of register <Rn>. The value of the least significant byte of register <Rt2> is stored to the memory address given by <Rn>, the original loaded value is zero-extended to a 32-bit word, and the word is written to register <Rt>. If the same register is specified for <Rt> and <Rt2>, this instruction swaps the value of the least significant byte of the register and the byte value at the memory address, and clears the most significant three bytes of the register. For both instructions, the memory system ensures that no other memory access can occur to the memory location between the load access and the store access. Note • The SWP and SWPB instructions rely on the properties of the system beyond the processor to ensure that no stores from other observers can occur between the load access and the store access, and this might not be implemented for all regions of memory on some system implementations. In all cases, SWP and SWPB do ensure that no stores from the processor that executed the SWP or SWPB instruction can occur between the load access and the store access of the SWP or SWPB. • ARM deprecates the use of SWP and SWPB, and strongly recommends that new software uses: LDREX/STREX in preference to SWP — — LDREXB/STREXB in preference to SWPB. • If the translation table entries that relate to a memory location accessed by the SWP or SWPB instruction change, or are seen to change by the executing processor as a result of TLB eviction, this might mean that the translation table attributes, permissions or addresses for the load are different to those for the store. In this case, the architecture makes no guarantee that no memory access occur to these memory locations between the load and store. The Virtualization Extensions make the SWP and SWPB instructions OPTIONAL and deprecated: • If an implementation does not include the SWP and SWPB instructions, the ID_ISAR0.Swap_instrs and ID_ISAR4.SWP_frac fields are zero, see About the Instruction Set Attribute registers on page B7-1950. • In an implementation that includes SWP and SWPB, both instructions are UNDEFINED in Hyp mode. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 B(1) 0 0 Rn(4) Rt(4) 0 0 0 0 1 0 0 1 Rt2(4) - @syntax <reg_T> <reg_T2> <mem_access> + @syntax { + + @assert { + + B == 0 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm swp reg_T reg_T2 maccess - @conv { + @rules { - reg_T = Register(Rt) - reg_T2 = Register(Rt2) - reg_N = Register(Rn) - size = (B != 4) - mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + B == 1 + + } + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + maccess = MemAccessOffset(reg_N, NULL) + + } + + @asm swpb reg_T reg_T2 maccess + + @rules { + + check g_arm_instruction_set_cond(cond) - if (size); chk_call ExtendKeyword("b") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/teq_A88237.d b/plugins/arm/v7/opdefs/teq_A88237.d index 89073f6..7b431a3 100644 --- a/plugins/arm/v7/opdefs/teq_A88237.d +++ b/plugins/arm/v7/opdefs/teq_A88237.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TEQ (immediate) -@desc Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 236 + +@desc { + + Test Equivalence (immediate) performs a bitwise exclusive OR operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm teq reg_N const } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 0 1 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) - } + } + + @asm teq reg_N const + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/teq_A88238.d b/plugins/arm/v7/opdefs/teq_A88238.d index 8187d81..9e80034 100644 --- a/plugins/arm/v7/opdefs/teq_A88238.d +++ b/plugins/arm/v7/opdefs/teq_A88238.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title TEQ (register) -@desc Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 237 + +@desc { + + Test Equivalence (register) performs a bitwise exclusive OR operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 0 1 0 1 0 1 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + } + + @asm teq reg_N reg_M ?shift } @@ -45,19 +55,23 @@ @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm teq reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/teq_A88239.d b/plugins/arm/v7/opdefs/teq_A88239.d index 986a7f0..76e3062 100644 --- a/plugins/arm/v7/opdefs/teq_A88239.d +++ b/plugins/arm/v7/opdefs/teq_A88239.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title TEQ (register-shifted register) -@desc Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 238 + +@desc { + + Test Equivalence (register-shifted register) performs a bitwise exclusive OR operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 0 1 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm teq reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/tst_A88240.d b/plugins/arm/v7/opdefs/tst_A88240.d index 0ff5121..50c0507 100644 --- a/plugins/arm/v7/opdefs/tst_A88240.d +++ b/plugins/arm/v7/opdefs/tst_A88240.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TST (immediate) -@desc Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. +@id 239 + +@desc { + + Test (immediate) performs a bitwise AND operation on a register value and an immediate value. It updates the condition flags based on the result, and discards the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm8(8) - @syntax <reg_N> <imm32> + @syntax { + + @conv { - @conv { + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_N = Register(Rn) - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm tst reg_N const } @@ -44,18 +54,22 @@ @word cond(4) 0 0 1 1 0 0 0 1 Rn(4) 0 0 0 0 imm12(12) - @syntax <reg_N> <imm32> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - imm32 = ARMExpandImm_C(imm12, 0) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) - } + } + + @asm tst reg_N const + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/tst_A88241.d b/plugins/arm/v7/opdefs/tst_A88241.d index 8777d06..ac1d843 100644 --- a/plugins/arm/v7/opdefs/tst_A88241.d +++ b/plugins/arm/v7/opdefs/tst_A88241.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,28 @@ @title TST (register) -@desc Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 240 + +@desc { + + Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (t1) { @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) - @syntax <reg_N> <reg_M> + @syntax { + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm tst reg_N reg_M } @@ -44,13 +54,17 @@ @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) - @syntax ".W" <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm3:imm2) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm tst.w reg_N reg_M ?shift } @@ -60,19 +74,23 @@ @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) - @syntax <reg_N> <reg_M> <?shift> + @syntax { - @conv { + @conv { - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) - } + } + + @asm tst reg_N reg_M ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/tst_A88242.d b/plugins/arm/v7/opdefs/tst_A88242.d index d3fdd9c..7ffb302 100644 --- a/plugins/arm/v7/opdefs/tst_A88242.d +++ b/plugins/arm/v7/opdefs/tst_A88242.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,37 @@ @title TST (register-shifted register) -@desc Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. +@id 241 + +@desc { + + Test (register-shifted register) performs a bitwise AND operation on a register value and a register-shifted register value. It updates the condition flags based on the result, and discards the result. + +} @encoding (A1) { @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 Rs(4) 0 type(2) 1 Rm(4) - @syntax <reg_N> <reg_M> <reg_shift> + @syntax { - @conv { + @conv { - reg_shift = RegisterShift(type, Rs) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift_t = UInt(type) + reg_S = Register(Rs) + shift = BuildRegShift(shift_t, reg_S) - } + } + + @asm tst reg_N reg_M shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uadd16_A88243.d b/plugins/arm/v7/opdefs/uadd16_A88243.d index fcaadee..9e6ec47 100644 --- a/plugins/arm/v7/opdefs/uadd16_A88243.d +++ b/plugins/arm/v7/opdefs/uadd16_A88243.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UADD16 -@desc Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 242 + +@desc { + + Unsigned Add 16 performs two 16-bit unsigned integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uadd8_A88244.d b/plugins/arm/v7/opdefs/uadd8_A88244.d index 451ca79..1cd1b79 100644 --- a/plugins/arm/v7/opdefs/uadd8_A88244.d +++ b/plugins/arm/v7/opdefs/uadd8_A88244.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UADD8 -@desc Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. +@id 243 + +@desc { + + Unsigned Add 8 performs four unsigned 8-bit integer additions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the additions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uasx_A88245.d b/plugins/arm/v7/opdefs/uasx_A88245.d index f968527..ada4b7a 100644 --- a/plugins/arm/v7/opdefs/uasx_A88245.d +++ b/plugins/arm/v7/opdefs/uasx_A88245.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UASX -@desc Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. +@id 244 + +@desc { + + Unsigned Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/ubfx_A88246.d b/plugins/arm/v7/opdefs/ubfx_A88246.d index 1f9488e..31c3f43 100644 --- a/plugins/arm/v7/opdefs/ubfx_A88246.d +++ b/plugins/arm/v7/opdefs/ubfx_A88246.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,31 @@ @title UBFX -@desc Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. +@id 245 + +@desc { + + Unsigned Bit Field Extract extracts any number of adjacent bits at any position from a register, zero-extends them to 32 bits, and writes the result to the destination register. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 1 0 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 widthm1(5) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(imm3:imm2) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(imm3:imm2) - width = IncWidth(widthm1) + } + + @asm ubfx reg_D reg_N lsbit width } @@ -46,20 +57,25 @@ @word cond(4) 0 1 1 1 1 1 1 widthm1(5) Rd(4) lsb(5) 1 0 1 Rn(4) - @syntax <reg_D> <reg_N> <lsbit> <width> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - lsbit = UInt(lsb) - width = IncWidth(widthm1) + reg_D = Register(Rd) + reg_N = Register(Rn) + lsbit = UInt(lsb) + widthminus1 = UInt(widthm1) + width = MinusBitDiff(widthminus1, lsbit) - } + } + + @asm ubfx reg_D reg_N lsbit width + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/udf_A88247.d b/plugins/arm/v7/opdefs/udf_A88247.d index 38f818c..db8fc28 100644 --- a/plugins/arm/v7/opdefs/udf_A88247.d +++ b/plugins/arm/v7/opdefs/udf_A88247.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,17 +23,27 @@ @title UDF -@desc Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. +@id 246 + +@desc { + + Permanently Undefined generates an Undefined Instruction exception. The encodings for UDF used in this section are defined as permanently UNDEFINED in the versions of the architecture specified in this section. Issue C.a of this manual first defines an assembler mnemonic for these encodings. However: • with the Thumb instruction set, ARM deprecates using the UDF instruction in an IT block • in the ARM instruction set, UDF is not conditional. + +} @encoding (t1) { @half 1 1 0 1 1 1 1 0 imm8(8) - @syntax <imm32> + @syntax { + + @conv { - @conv { + imm32 = ZeroExtend(imm8, 32) - imm32 = ZeroExtend(imm8, 32) + } + + @asm udf imm32 } @@ -43,11 +53,15 @@ @word 1 1 1 1 0 1 1 1 1 1 1 1 imm4(4) 1 0 1 0 imm12(12) - @syntax ".W" <imm32> + @syntax { + + @conv { + + imm32 = ZeroExtend(imm4:imm12, 32) - @conv { + } - imm32 = ZeroExtend(imm4:imm12, 32) + @asm udf.w imm32 } @@ -57,11 +71,15 @@ @word 1 1 1 0 0 1 1 1 1 1 1 1 imm12(12) 1 1 1 1 imm4(4) - @syntax <imm32> + @syntax { + + @conv { + + imm32 = ZeroExtend(imm12:imm4, 32) - @conv { + } - imm32 = ZeroExtend(imm12:imm4, 32) + @asm udf imm32 } diff --git a/plugins/arm/v7/opdefs/udiv_A88248.d b/plugins/arm/v7/opdefs/udiv_A88248.d index eea7947..411e323 100644 --- a/plugins/arm/v7/opdefs/udiv_A88248.d +++ b/plugins/arm/v7/opdefs/udiv_A88248.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UDIV -@desc Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. +@id 247 + +@desc { + + Unsigned Divide divides a 32-bit unsigned integer register value by a 32-bit unsigned integer register value, and writes the result to the destination register. The condition flags are not affected. See ARMv7 implementation requirements and options for the divide instructions on page A4-172 for more information about this instruction. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm udiv ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 1 0 0 1 1 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm udiv ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhadd16_A88249.d b/plugins/arm/v7/opdefs/uhadd16_A88249.d index 54da5b0..e335f3c 100644 --- a/plugins/arm/v7/opdefs/uhadd16_A88249.d +++ b/plugins/arm/v7/opdefs/uhadd16_A88249.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHADD16 -@desc Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. +@id 248 + +@desc { + + Unsigned Halving Add 16 performs two unsigned 16-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhadd8_A88250.d b/plugins/arm/v7/opdefs/uhadd8_A88250.d index 759a0a7..f392b5e 100644 --- a/plugins/arm/v7/opdefs/uhadd8_A88250.d +++ b/plugins/arm/v7/opdefs/uhadd8_A88250.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHADD8 -@desc Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. +@id 249 + +@desc { + + Unsigned Halving Add 8 performs four unsigned 8-bit integer additions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhasx_A88251.d b/plugins/arm/v7/opdefs/uhasx_A88251.d index 3751394..b5c4153 100644 --- a/plugins/arm/v7/opdefs/uhasx_A88251.d +++ b/plugins/arm/v7/opdefs/uhasx_A88251.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHASX -@desc Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. +@id 250 + +@desc { + + Unsigned Halving Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhsax_A88252.d b/plugins/arm/v7/opdefs/uhsax_A88252.d index f06b2ba..7b793f4 100644 --- a/plugins/arm/v7/opdefs/uhsax_A88252.d +++ b/plugins/arm/v7/opdefs/uhsax_A88252.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHSAX -@desc Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. +@id 251 + +@desc { + + Unsigned Halving Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhsub16_A88253.d b/plugins/arm/v7/opdefs/uhsub16_A88253.d index 93f92f7..482ac1d 100644 --- a/plugins/arm/v7/opdefs/uhsub16_A88253.d +++ b/plugins/arm/v7/opdefs/uhsub16_A88253.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHSUB16 -@desc Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 252 + +@desc { + + Unsigned Halving Subtract 16 performs two unsigned 16-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uhsub8_A88254.d b/plugins/arm/v7/opdefs/uhsub8_A88254.d index 198a095..c5349e4 100644 --- a/plugins/arm/v7/opdefs/uhsub8_A88254.d +++ b/plugins/arm/v7/opdefs/uhsub8_A88254.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UHSUB8 -@desc Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. +@id 253 + +@desc { + + Unsigned Halving Subtract 8 performs four unsigned 8-bit integer subtractions, halves the results, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 1 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uhsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uhsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/umaal_A88255.d b/plugins/arm/v7/opdefs/umaal_A88255.d index 34cb707..10a823a 100644 --- a/plugins/arm/v7/opdefs/umaal_A88255.d +++ b/plugins/arm/v7/opdefs/umaal_A88255.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UMAAL -@desc Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. +@id 254 + +@desc { + + Unsigned Multiply Accumulate Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, adds two unsigned 32-bit values, and writes the 64-bit result to two registers. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 1 1 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm umaal reg_DLO reg_DHI reg_N reg_M } @@ -46,20 +56,24 @@ @word cond(4) 0 0 0 0 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm umaal reg_DLO reg_DHI reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/umlal_A88256.d b/plugins/arm/v7/opdefs/umlal_A88256.d index 00d1903..83af10c 100644 --- a/plugins/arm/v7/opdefs/umlal_A88256.d +++ b/plugins/arm/v7/opdefs/umlal_A88256.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UMLAL -@desc Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 255 + +@desc { + + Unsigned Multiply Accumulate Long multiplies two unsigned 32-bit values to produce a 64-bit value, and accumulates this with a 64-bit value. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 1 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm umlal reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 0 1 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm umlal reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umlals reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/umull_A88257.d b/plugins/arm/v7/opdefs/umull_A88257.d index d2cc321..2164bb4 100644 --- a/plugins/arm/v7/opdefs/umull_A88257.d +++ b/plugins/arm/v7/opdefs/umull_A88257.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UMULL -@desc Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. +@id 256 + +@desc { + + Unsigned Multiply Long multiplies two 32-bit unsigned values to produce a 64-bit result. In ARM instructions, the condition flags can optionally be updated based on the result. Use of this option adversely affects performance on many processor implementations. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 1 0 1 0 Rn(4) RdLo(4) RdHi(4) 0 0 0 0 Rm(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) - @conv { + } - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) + @asm umull reg_DLO reg_DHI reg_N reg_M } @@ -46,22 +56,57 @@ @word cond(4) 0 0 0 0 1 0 0 S(1) RdHi(4) RdLo(4) Rm(4) 1 0 0 1 Rn(4) - @syntax <reg_DLO> <reg_DHI> <reg_N> <reg_M> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } - @conv { + @asm umull reg_DLO reg_DHI reg_N reg_M - reg_DLO = Register(RdLo) - reg_DHI = Register(RdHi) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_DLO = Register(RdLo) + reg_DHI = Register(RdHi) + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm umulls reg_DLO reg_DHI reg_N reg_M + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqadd16_A88258.d b/plugins/arm/v7/opdefs/uqadd16_A88258.d index 14528c8..4e099ec 100644 --- a/plugins/arm/v7/opdefs/uqadd16_A88258.d +++ b/plugins/arm/v7/opdefs/uqadd16_A88258.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQADD16 -@desc Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 257 + +@desc { + + Unsigned Saturating Add 16 performs two unsigned 16-bit integer additions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqadd16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqadd16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqadd8_A88259.d b/plugins/arm/v7/opdefs/uqadd8_A88259.d index 94b8e39..4ac517a 100644 --- a/plugins/arm/v7/opdefs/uqadd8_A88259.d +++ b/plugins/arm/v7/opdefs/uqadd8_A88259.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQADD8 -@desc Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. +@id 258 + +@desc { + + Unsigned Saturating Add 8 performs four unsigned 8-bit integer additions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqadd8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqadd8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqasx_A88260.d b/plugins/arm/v7/opdefs/uqasx_A88260.d index 174b08c..0b2047f 100644 --- a/plugins/arm/v7/opdefs/uqasx_A88260.d +++ b/plugins/arm/v7/opdefs/uqasx_A88260.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQASX -@desc Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 259 + +@desc { + + Unsigned Saturating Add and Subtract with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer addition and one unsigned 16-bit subtraction, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 0 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqasx ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 0 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqasx ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqsax_A88261.d b/plugins/arm/v7/opdefs/uqsax_A88261.d index 6092e51..57b1b3f 100644 --- a/plugins/arm/v7/opdefs/uqsax_A88261.d +++ b/plugins/arm/v7/opdefs/uqsax_A88261.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQSAX -@desc Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 260 + +@desc { + + Unsigned Saturating Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqsax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqsax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqsub16_A88262.d b/plugins/arm/v7/opdefs/uqsub16_A88262.d index 1f458ff..23a4fb7 100644 --- a/plugins/arm/v7/opdefs/uqsub16_A88262.d +++ b/plugins/arm/v7/opdefs/uqsub16_A88262.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQSUB16 -@desc Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. +@id 261 + +@desc { + + Unsigned Saturating Subtract 16 performs two unsigned 16-bit integer subtractions, saturates the results to the 16-bit unsigned integer range 0 ≤ x ≤ 216 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqsub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqsub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uqsub8_A88263.d b/plugins/arm/v7/opdefs/uqsub8_A88263.d index 37d96e7..4054ec5 100644 --- a/plugins/arm/v7/opdefs/uqsub8_A88263.d +++ b/plugins/arm/v7/opdefs/uqsub8_A88263.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UQSUB8 -@desc Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. +@id 262 + +@desc { + + Unsigned Saturating Subtract 8 performs four unsigned 8-bit integer subtractions, saturates the results to the 8-bit unsigned integer range 0 ≤ x ≤ 28 – 1, and writes the results to the destination register. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm uqsub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm uqsub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usad8_A88264.d b/plugins/arm/v7/opdefs/usad8_A88264.d index 09d7ece..2927910 100644 --- a/plugins/arm/v7/opdefs/usad8_A88264.d +++ b/plugins/arm/v7/opdefs/usad8_A88264.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USAD8 -@desc Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. +@id 263 + +@desc { + + Unsigned Sum of Absolute Differences performs four unsigned 8-bit subtractions, and adds the absolute values of the differences together. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) 1 1 1 1 Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usad8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) 1 1 1 1 Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usad8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usada8_A88265.d b/plugins/arm/v7/opdefs/usada8_A88265.d index dd1efdb..df1b7f4 100644 --- a/plugins/arm/v7/opdefs/usada8_A88265.d +++ b/plugins/arm/v7/opdefs/usada8_A88265.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title USADA8 -@desc Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. +@id 264 + +@desc { + + Unsigned Sum of Absolute Differences and Accumulate performs four unsigned 8-bit subtractions, and adds the absolute values of the differences to a 32-bit accumulate operand. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 1 0 1 1 1 Rn(4) Ra(4) Rd(4) 0 0 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + } + + @asm usada8 reg_D reg_N reg_M reg_A } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 1 1 0 0 0 Rd(4) Ra(4) Rm(4) 0 0 0 1 Rn(4) - @syntax <reg_D> <reg_N> <reg_M> <reg_A> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - reg_A = Register(Ra) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + reg_A = Register(Ra) - } + } + + @asm usada8 reg_D reg_N reg_M reg_A + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usat16_A88267.d b/plugins/arm/v7/opdefs/usat16_A88267.d index c091dc6..056c0f2 100644 --- a/plugins/arm/v7/opdefs/usat16_A88267.d +++ b/plugins/arm/v7/opdefs/usat16_A88267.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USAT16 -@desc Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. +@id 266 + +@desc { + + Unsigned Saturate 16 saturates two signed 16-bit values to a selected unsigned range. The Q flag is set if the operation saturates. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 1 0 Rn(4) 0 0 0 0 Rd(4) 0 0 0 0 sat_imm(4) - @syntax <reg_D> <saturate_to> <reg_N> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) + } + + @asm usat16 reg_D saturate_to reg_N } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 1 1 1 0 sat_imm(4) Rd(4) 1 1 1 1 0 0 1 1 Rn(4) - @syntax <reg_D> <saturate_to> <reg_N> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) - } + } + + @asm usat16 reg_D saturate_to reg_N + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usat_A88266.d b/plugins/arm/v7/opdefs/usat_A88266.d index 55de21a..c89d083 100644 --- a/plugins/arm/v7/opdefs/usat_A88266.d +++ b/plugins/arm/v7/opdefs/usat_A88266.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title USAT -@desc Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. +@id 265 + +@desc { + + Unsigned Saturate saturates an optionally-shifted signed value to a selected unsigned range. The Q flag is set if the operation saturates. + +} @encoding (T1) { @word 1 1 1 1 0 0 1 1 1 0 sh(1) 0 Rn(4) 0 imm3(3) Rd(4) imm2(2) 0 sat_imm(5) - @syntax <reg_D> <saturate_to> <reg_N> <?shift> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm3:imm2) - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - shift = DecodeImmShift(sh:'0', imm3:imm2) + } + + @asm usat reg_D saturate_to reg_N ?shift } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 1 sat_imm(5) Rd(4) imm5(5) sh(1) 0 1 Rn(4) - @syntax <reg_D> <saturate_to> <reg_N> <?shift> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - saturate_to = UInt(sat_imm) - shift = DecodeImmShift(sh:'0', imm5) + reg_D = Register(Rd) + saturate_to = UInt(sat_imm) + reg_N = Register(Rn) + shift = DecodeImmShift(sh:'0', imm5) - } + } + + @asm usat reg_D saturate_to reg_N ?shift + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usax_A88268.d b/plugins/arm/v7/opdefs/usax_A88268.d index 040eedc..d8c5305 100644 --- a/plugins/arm/v7/opdefs/usax_A88268.d +++ b/plugins/arm/v7/opdefs/usax_A88268.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USAX -@desc Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. +@id 267 + +@desc { + + Unsigned Subtract and Add with Exchange exchanges the two halfwords of the second operand, performs one unsigned 16-bit integer subtraction and one unsigned 16-bit addition, and writes the results to the destination register. It sets the APSR.GE bits according to the results. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 1 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usax ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 0 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usax ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usub16_A88269.d b/plugins/arm/v7/opdefs/usub16_A88269.d index 31796d9..1209abf 100644 --- a/plugins/arm/v7/opdefs/usub16_A88269.d +++ b/plugins/arm/v7/opdefs/usub16_A88269.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USUB16 -@desc Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. +@id 268 + +@desc { + + Unsigned Subtract 16 performs two 16-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 1 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usub16 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usub16 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/usub8_A88270.d b/plugins/arm/v7/opdefs/usub8_A88270.d index 576894c..659a0e0 100644 --- a/plugins/arm/v7/opdefs/usub8_A88270.d +++ b/plugins/arm/v7/opdefs/usub8_A88270.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title USUB8 -@desc Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. +@id 269 + +@desc { + + Unsigned Subtract 8 performs four 8-bit unsigned integer subtractions, and writes the results to the destination register. It sets the APSR.GE bits according to the results of the subtractions. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 1 1 0 0 Rn(4) 1 1 1 1 Rd(4) 0 1 0 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + } + + @asm usub8 ?reg_D reg_N reg_M } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 0 1 0 1 Rn(4) Rd(4) 1 1 1 1 1 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) - } + } + + @asm usub8 ?reg_D reg_N reg_M + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtab16_A88272.d b/plugins/arm/v7/opdefs/uxtab16_A88272.d index 4fc61d2..92109fb 100644 --- a/plugins/arm/v7/opdefs/uxtab16_A88272.d +++ b/plugins/arm/v7/opdefs/uxtab16_A88272.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UXTAB16 -@desc Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. +@id 271 + +@desc { + + Unsigned Extend and Add Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, adds the results to two 16-bit values from another register, and writes the final results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 0 1 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtab16 ?reg_D reg_N reg_M ?rotation } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 0 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtab16 ?reg_D reg_N reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtab_A88271.d b/plugins/arm/v7/opdefs/uxtab_A88271.d index fe27d4b..9c98102 100644 --- a/plugins/arm/v7/opdefs/uxtab_A88271.d +++ b/plugins/arm/v7/opdefs/uxtab_A88271.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UXTAB -@desc Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. +@id 270 + +@desc { + + Unsigned Extend and Add Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, adds the result to the value in another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 1 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtab ?reg_D reg_N reg_M ?rotation } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 1 0 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtab ?reg_D reg_N reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtah_A88273.d b/plugins/arm/v7/opdefs/uxtah_A88273.d index 3c587d9..c1d0d36 100644 --- a/plugins/arm/v7/opdefs/uxtah_A88273.d +++ b/plugins/arm/v7/opdefs/uxtah_A88273.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,20 +23,30 @@ @title UXTAH -@desc Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. +@id 272 + +@desc { + + Unsigned Extend and Add Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, adds the result to a value from another register, and writes the final result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 0 0 1 Rn(4) 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtah ?reg_D reg_N reg_M ?rotation } @@ -46,20 +56,24 @@ @word cond(4) 0 1 1 0 1 1 1 1 Rn(4) Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtah ?reg_D reg_N reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtb16_A88275.d b/plugins/arm/v7/opdefs/uxtb16_A88275.d index a30d133..b2ac134 100644 --- a/plugins/arm/v7/opdefs/uxtb16_A88275.d +++ b/plugins/arm/v7/opdefs/uxtb16_A88275.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,29 @@ @title UXTB16 -@desc Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. +@id 274 + +@desc { + + Unsigned Extend Byte 16 extracts two 8-bit values from a register, zero-extends them to 16 bits each, and writes the results to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit values. + +} @encoding (T1) { @word 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { + + @conv { - @conv { + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + } + + @asm uxtb16 ?reg_D reg_M ?rotation } @@ -45,19 +55,23 @@ @word cond(4) 0 1 1 0 1 1 0 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtb16 ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxtb_A88274.d b/plugins/arm/v7/opdefs/uxtb_A88274.d index f49ba83..ac5b421 100644 --- a/plugins/arm/v7/opdefs/uxtb_A88274.d +++ b/plugins/arm/v7/opdefs/uxtb_A88274.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title UXTB -@desc Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. +@id 273 + +@desc { + + Unsigned Extend Byte extracts an 8-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 8-bit value. + +} @encoding (t1) { @half 1 0 1 1 0 0 1 0 1 1 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm uxtb ?reg_D reg_M ?rotation } @@ -44,13 +55,17 @@ @word 1 1 1 1 1 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax ".W" <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxtb.w ?reg_D reg_M ?rotation } @@ -60,19 +75,23 @@ @word cond(4) 0 1 1 0 1 1 1 0 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxtb ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/uxth_A88276.d b/plugins/arm/v7/opdefs/uxth_A88276.d index 5ae4f4f..b49360f 100644 --- a/plugins/arm/v7/opdefs/uxth_A88276.d +++ b/plugins/arm/v7/opdefs/uxth_A88276.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,18 +23,29 @@ @title UXTH -@desc Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. +@id 275 + +@desc { + + Unsigned Extend Halfword extracts a 16-bit value from a register, zero-extends it to 32 bits, and writes the result to the destination register. The instruction can specify a rotation by 0, 8, 16, or 24 bits before extracting the 16-bit value. + +} @encoding (t1) { @half 1 0 1 1 0 0 1 0 1 0 Rm(3) Rd(3) - @syntax <reg_D> <reg_M> + @syntax { + + @conv { + + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(0) - @conv { + } - reg_D = Register(Rd) - reg_M = Register(Rm) + @asm uxth ?reg_D reg_M ?rotation } @@ -44,13 +55,17 @@ @word 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 1 1 1 1 1 Rd(4) 1 0 rotate(2) Rm(4) - @syntax ".W" <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') + + } + + @asm uxth.w ?reg_D reg_M ?rotation } @@ -60,19 +75,23 @@ @word cond(4) 0 1 1 0 1 1 1 1 1 1 1 1 Rd(4) rotate(2) 0 0 0 1 1 1 Rm(4) - @syntax <reg_D> <reg_M> <?rotation> + @syntax { - @conv { + @conv { - reg_D = Register(Rd) - reg_M = Register(Rm) - rotation = Rotation(rotate:'000') + reg_D = Register(Rd) + reg_M = Register(Rm) + rotation = Rotation(rotate:'000') - } + } + + @asm uxth ?reg_D reg_M ?rotation + + @rules { - @rules { + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/wfi_A88425.d b/plugins/arm/v7/opdefs/wfi_A88425.d index f11d033..0fd2552 100644 --- a/plugins/arm/v7/opdefs/wfi_A88425.d +++ b/plugins/arm/v7/opdefs/wfi_A88425.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title WFI -@desc Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. +@id 424 + +@desc { + + Wait For Interrupt is a hint instruction that permits the processor to enter a low-power state until one of a number of asynchronous events occurs. For more information, see Wait For Interrupt on page B1-1202. In an implementation that includes the Virtualization Extensions, if HCR.TWI is set to 1, execution of a WFI instruction in a Non-secure mode other than Hyp mode generates a Hyp Trap exception if, ignoring the value of the HCR.TWI bit, conditions permit the processor to suspend execution. For more information see Trapping use of the WFI and WFE instructions on page B1-1255. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 0 1 1 0 0 0 0 + @syntax { + + @asm wfi + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 - @syntax ".W" + @syntax { + + @asm wfi.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 - @rules { + @syntax { + + @asm wfi + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/opdefs/yield_A88426.d b/plugins/arm/v7/opdefs/yield_A88426.d index 252c018..1ccee59 100644 --- a/plugins/arm/v7/opdefs/yield_A88426.d +++ b/plugins/arm/v7/opdefs/yield_A88426.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,19 +23,35 @@ @title YIELD -@desc YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. +@id 425 + +@desc { + + YIELD is a hint instruction. Software with a multithreading capability can use a YIELD instruction to indicate to the hardware that it is performing a task, for example a spin-lock, that could be swapped out to improve overall system performance. Hardware can use this hint to suspend and resume multiple software threads if it supports the capability. For more information about the recommended use of this instruction see The Yield instruction on page A4-178. + +} @encoding (t1) { @half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0 + @syntax { + + @asm yield + + } + } @encoding (T2) { @word 1 1 1 1 0 0 1 1 1 0 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 - @syntax ".W" + @syntax { + + @asm yield.w + + } } @@ -43,9 +59,15 @@ @word cond(4) 0 0 1 1 0 0 1 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 - @rules { + @syntax { + + @asm yield + + @rules { + + check g_arm_instruction_set_cond(cond) - chk_call StoreCondition(cond) + } } diff --git a/plugins/arm/v7/operands/maccess.c b/plugins/arm/v7/operands/maccess.c index 043d801..24d5393 100644 --- a/plugins/arm/v7/operands/maccess.c +++ b/plugins/arm/v7/operands/maccess.c @@ -36,8 +36,8 @@ struct _GArmV7MAccessOperand GArchOperand *base; /* Base de l'accès en mémoire */ GArchOperand *offset; /* Décalage pour l'adresse */ - GArchOperand *shift; /* Décalage pour le décalage */ - bool not_post_indexed; /* Positio du décalage */ + GArchOperand *shift; /* Décalage pour le décallage */ + bool post_indexed; /* Position du décalage */ bool write_back; /* Mise à jour de la base */ }; @@ -194,7 +194,7 @@ static int g_armv7_maccess_operand_compare(const GArmV7MAccessOperand *a, const result = sort_pointer(a->shift, b->shift, (__compar_fn_t)g_arch_operand_compare); if (result != 0) goto gamoc_done; - result = sort_boolean(a->not_post_indexed, b->not_post_indexed); + result = sort_boolean(a->post_indexed, b->post_indexed); if (result != 0) goto gamoc_done; result = sort_boolean(a->write_back, b->write_back); @@ -226,7 +226,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G g_arch_operand_print(operand->base, line, syntax); - if (!operand->not_post_indexed) + if (operand->post_indexed) g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); if (operand->offset != NULL) @@ -247,7 +247,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G } - if (operand->not_post_indexed) + if (!operand->post_indexed) g_buffer_line_append_text(line, BLC_ASSEMBLY, "]", 1, RTT_HOOK, NULL); if (operand->write_back) @@ -258,11 +258,19 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G /****************************************************************************** * * +<<<<<<< HEAD * Paramètres : base = représente le registre de la base d'accès. * * offset = détermine le décalage entre l'adresse et la base. * * shift = opération de décalage pour jouer sur le décalage. * * indexed = précise la forme donnée au décalage à appliquer. * * wback = indique une mise à jour de la base après usage. * +======= +* Paramètres : base = représente le registre de la base d'accès. * +* offset = détermine le décallage entre l'adresse et la base. * +* shift = opération de décallage pour jouer sur le décallage. * +* post = précise la forme donnée au décallage à appliquer. * +* wback = indique une mise à jour de la base après usage. * +>>>>>>> Rewritten the whole instruction definition format. * * * Description : Crée un accès à la mémoire depuis une base et un décalage. * * * @@ -272,7 +280,7 @@ static void g_armv7_maccess_operand_print(const GArmV7MAccessOperand *operand, G * * ******************************************************************************/ -GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool indexed, bool wback) +GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offset, GArchOperand *shift, bool post, bool wback) { GArmV7MAccessOperand *result; /* Structure à retourner */ @@ -282,7 +290,7 @@ GArchOperand *g_armv7_maccess_operand_new(GArchOperand *base, GArchOperand *offs result->offset = offset; result->shift = shift; - result->not_post_indexed = indexed; + result->post_indexed = post; result->write_back = wback; return G_ARCH_OPERAND(result); @@ -361,7 +369,7 @@ GArchOperand *g_armv7_maccess_operand_get_shift(const GArmV7MAccessOperand *oper bool g_armv7_maccess_operand_is_post_indexed(const GArmV7MAccessOperand *operand) { - return !operand->not_post_indexed; + return operand->post_indexed; } diff --git a/plugins/arm/v7/operands/reglist.c b/plugins/arm/v7/operands/reglist.c index 00c3b98..1f56249 100644 --- a/plugins/arm/v7/operands/reglist.c +++ b/plugins/arm/v7/operands/reglist.c @@ -255,7 +255,7 @@ static void g_armv7_reglist_operand_print(const GArmV7RegListOperand *operand, G /****************************************************************************** * * -* Paramètres : - * +* Paramètres : selected = masque de bits pour les registres à intégrer. * * * * Description : Crée une liste vierge de registres ARM. * * * @@ -265,48 +265,24 @@ static void g_armv7_reglist_operand_print(const GArmV7RegListOperand *operand, G * * ******************************************************************************/ -GArchOperand *g_armv7_reglist_operand_new(void) -{ - GArchOperand *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_ARMV7_REGLIST_OPERAND, NULL); - - return G_ARCH_OPERAND(result); - -} - - -/****************************************************************************** -* * -* Paramètres : operand = liste de registres à compléter. * -* selected = masque de bits pour les registres à intégrer. * -* * -* Description : Remplit une liste de registres de registres ARM. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool g_armv7_reglist_load_registers(GArmV7RegListOperand *operand, uint32_t selected) +GArchOperand *g_armv7_reglist_operand_new(uint16_t selected) { + GArmV7RegListOperand *result; /* Structure à retourner */ uint8_t i; /* Boucle de parcours */ GArmV7Register *reg; /* Nouveau registre à intégrer */ - for (i = 18; i < 32; i++) - if (selected & (1 << i)) return false; + result = g_object_new(G_TYPE_ARMV7_REGLIST_OPERAND, NULL); - for (i = 0; i < 18; i++) + for (i = 0; i < 16; i++) { if ((selected & (1 << i)) == 0) continue; reg = g_armv7_register_new(i); - g_armv7_reglist_add_register(operand, reg); + g_armv7_reglist_add_register(result, reg); } - return true; + return G_ARCH_OPERAND(result); } diff --git a/plugins/arm/v7/operands/reglist.h b/plugins/arm/v7/operands/reglist.h index 60b78a6..82f1a60 100644 --- a/plugins/arm/v7/operands/reglist.h +++ b/plugins/arm/v7/operands/reglist.h @@ -55,10 +55,7 @@ typedef struct _GArmV7RegListOperandClass GArmV7RegListOperandClass; GType g_armv7_reglist_operand_get_type(void); /* Crée une liste vierge de registres ARM. */ -GArchOperand *g_armv7_reglist_operand_new(void); - -/* Remplit une liste de registres de registres ARM. */ -bool g_armv7_reglist_load_registers(GArmV7RegListOperand *, uint32_t); +GArchOperand *g_armv7_reglist_operand_new(uint16_t); /* Ajoute un registre à une liste de registres ARM. */ void g_armv7_reglist_add_register(GArmV7RegListOperand *, GArmV7Register *); diff --git a/plugins/arm/v7/pseudo.c b/plugins/arm/v7/pseudo.c index e560f5d..12ad50b 100644 --- a/plugins/arm/v7/pseudo.c +++ b/plugins/arm/v7/pseudo.c @@ -483,7 +483,7 @@ bool armv7_thumb_expand_imm(uint32_t imm12, uint32_t *value) * * ******************************************************************************/ -bool armv7_decode_imm_shift(uint8_t type2, uint8_t imm5, SRType *type, uint32_t *value) +bool armv7_decode_imm_shift(uint8_t type2, uint8_t imm5, SRType *type, uint8_t *value) { bool result; /* Bilan à retourner */ @@ -681,3 +681,50 @@ uint32_t armv7_zero_extend(uint32_t x, unsigned int n, unsigned int i) return x; } + + +/****************************************************************************** +* * +* Paramètres : x = valeur sur 32 bits maximum à traiter. * +* t = bit de poids nombre de bits à prendre en compte. * +* i = taille finale à obtenir. * +* * +* Description : Fournit une aide pour la fonction 'SignExtend'. * +* * +* Retour : Nouvelle valeur calculée. * +* * +* Remarques : - * +* * +******************************************************************************/ + +uint32_t armv7_sign_extend(uint32_t x, unsigned int t, unsigned int i) +{ + uint32_t result; /* Valeur à retourner */ + bool set; /* Bit de poids fort à 1 ? */ + unsigned int k; /* Boucle de parcours */ + + result = 0; + + set = (x & (1 << t)); + + switch (i) + { + +#define SIGN_EXTEND_CASE(sz) \ + case sz: \ + result = x; \ + if (set) \ + for (k = t + 1; k < sz; k++) \ + result |= (1 << k); \ + break; + + SIGN_EXTEND_CASE(4); + SIGN_EXTEND_CASE(8); + SIGN_EXTEND_CASE(16); + SIGN_EXTEND_CASE(32); + + } + + return result; + +} diff --git a/plugins/arm/v7/pseudo.h b/plugins/arm/v7/pseudo.h index c918d57..d070bcd 100644 --- a/plugins/arm/v7/pseudo.h +++ b/plugins/arm/v7/pseudo.h @@ -110,7 +110,7 @@ typedef enum _SRType /* Traduit la fonction 'DecodeImmShift'. */ -bool armv7_decode_imm_shift(uint8_t, uint8_t, SRType *, uint32_t *); +bool armv7_decode_imm_shift(uint8_t, uint8_t, SRType *, uint8_t *); /* Traduit la fonction 'DecodeRegShift'. */ bool armv7_decode_reg_shift(uint8_t, SRType *); @@ -131,6 +131,9 @@ bool armv7_shift(uint32_t, unsigned int, SRType, unsigned int, bool, uint32_t *) /* Traduit la fonction 'ZeroExtend'. */ uint32_t armv7_zero_extend(uint32_t, unsigned int, unsigned int); +/* Fournit une aide pour la fonction 'SignExtend'. */ +uint32_t armv7_sign_extend(uint32_t, unsigned int, unsigned int); + #endif /* _PLUGINS_ARM_V7_PSEUDO_H */ diff --git a/plugins/dalvik/Makefile.am b/plugins/dalvik/Makefile.am index d12f733..2e042f2 100644 --- a/plugins/dalvik/Makefile.am +++ b/plugins/dalvik/Makefile.am @@ -12,13 +12,14 @@ libdalvik_la_SOURCES = \ link.h link.c \ operand.h operand.c \ post.h \ + processor-int.h \ processor.h processor.c \ register.h register.c libdalvik_la_LIBADD = \ - opcodes/libdalvikopcodes.la \ operands/libdalvikoperands.la \ - pseudo/libdalvikpseudo.la + pseudo/libdalvikpseudo.la \ + v35/libdalvik35.la libdalvik_la_CFLAGS = $(AM_CFLAGS) @@ -28,4 +29,4 @@ AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBPYTHON_CFLAGS) $(LIBPYGOBJECT_CFLAGS) $(LIBX AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) -SUBDIRS = opdefs opcodes operands pseudo +SUBDIRS = operands pseudo v35 diff --git a/plugins/dalvik/context.h b/plugins/dalvik/context.h index fbee9e0..76c2ea4 100644 --- a/plugins/dalvik/context.h +++ b/plugins/dalvik/context.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_CONTEXT_H -#define _ARCH_DALVIK_CONTEXT_H +#ifndef _PLUGINS_DALVIK_CONTEXT_H +#define _PLUGINS_DALVIK_CONTEXT_H #include <glib-object.h> @@ -99,4 +99,4 @@ GDalvikDContext *g_dalvik_dcontext_new(void); -#endif /* _ARCH_DALVIK_CONTEXT_H */ +#endif /* _PLUGINS_DALVIK_CONTEXT_H */ diff --git a/plugins/dalvik/core.c b/plugins/dalvik/core.c index 7f0c79f..57d382c 100644 --- a/plugins/dalvik/core.c +++ b/plugins/dalvik/core.c @@ -28,8 +28,8 @@ #include <plugins/plugin-def.h> -#include "processor.h" #include "register.h" +#include "v35/processor.h" @@ -54,7 +54,7 @@ G_MODULE_EXPORT bool chrysalide_plugin_init(GPluginModule *plugin) { bool result; /* Bilan à retourner */ - result = register_processor_type("dalvik", "Dalvik Virtual Machine", G_TYPE_DALVIK_PROCESSOR, + result = register_processor_type("dalvik35", "Dalvik Virtual Machine v35", G_TYPE_DALVIK35_PROCESSOR, NULL, NULL); return result; diff --git a/plugins/dalvik/fetch.h b/plugins/dalvik/fetch.h index e9ea340..4a9a788 100644 --- a/plugins/dalvik/fetch.h +++ b/plugins/dalvik/fetch.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_FETCH_H -#define _ARCH_DALVIK_FETCH_H +#ifndef _PLUGINS_DALVIK_FETCH_H +#define _PLUGINS_DALVIK_FETCH_H #include <arch/instruction.h> @@ -53,4 +53,4 @@ static inline void help_fetching_with_dalvik_ifz_instruction(GArchInstruction *i -#endif /* _ARCH_DALVIK_FETCH_H */ +#endif /* _PLUGINS_DALVIK_FETCH_H */ diff --git a/plugins/dalvik/helpers.h b/plugins/dalvik/helpers.h index 6a0ba5c..5b23f0e 100644 --- a/plugins/dalvik/helpers.h +++ b/plugins/dalvik/helpers.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_HELPERS_H -#define _ARCH_DALVIK_HELPERS_H +#ifndef _PLUGINS_DALVIK_HELPERS_H +#define _PLUGINS_DALVIK_HELPERS_H #include "operand.h" @@ -40,4 +40,4 @@ -#endif /* _ARCH_DALVIK_HELPERS_H */ +#endif /* _PLUGINS_DALVIK_HELPERS_H */ diff --git a/plugins/dalvik/instruction-def.h b/plugins/dalvik/instruction-def.h deleted file mode 100644 index af6e308..0000000 --- a/plugins/dalvik/instruction-def.h +++ /dev/null @@ -1,305 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * instruction-def.h - définition interne des identifiants d'instructions Dalvik - * - * Copyright (C) 2011-2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -#ifndef _ARCH_DALVIK_INSTRUCTION_DEF_H -#define _ARCH_DALVIK_INSTRUCTION_DEF_H - - - -/* Enumération de tous les opcodes */ -typedef enum _DalvikOpcodes -{ - DOP_NOP, /* nop (0x00) */ - DOP_MOVE, /* move (0x01) */ - DOP_MOVE_FROM_16, /* move/from16 (0x02) */ - DOP_MOVE_16, /* move/16 (0x03) */ - DOP_MOVE_WIDE, /* move-wide (0x04) */ - DOP_MOVE_WIDE_FROM_16, /* move-wide/from16 (0x05) */ - DOP_MOVE_WIDE_16, /* move-wide/16 (0x06) */ - DOP_MOVE_OBJECT, /* move-object (0x07) */ - DOP_MOVE_OBJECT_FROM_16, /* move-object/from16 (0x08) */ - DOP_MOVE_OBJECT_16, /* move-object/16 (0x09) */ - DOP_MOVE_RESULT, /* move-result (0x0a) */ - DOP_MOVE_RESULT_WIDE, /* move-result-wide (0x0b) */ - DOP_MOVE_RESULT_OBJECT, /* move-result-object (0x0c) */ - DOP_MOVE_EXCEPTION, /* move-exception (0x0d) */ - DOP_RETURN_VOID, /* return-void (0x0e) */ - DOP_RETURN, /* return (0x0f) */ - DOP_RETURN_WIDE, /* return-wide (0x10) */ - DOP_RETURN_OBJECT, /* return-object (0x11) */ - DOP_CONST_4, /* const/4 (0x12) */ - DOP_CONST_16, /* const/16 (0x13) */ - DOP_CONST, /* const (0x14) */ - DOP_CONST_HIGH16, /* const/high16 (0x15) */ - DOP_CONST_WIDE_16, /* const-wide/16 (0x16) */ - DOP_CONST_WIDE_32, /* const-wide/32 (0x17) */ - DOP_CONST_WIDE, /* const-wide (0x18) */ - DOP_CONST_WIDE_HIGH16, /* const-wide/high16 (0x19) */ - DOP_CONST_STRING, /* const-string (0x1a) */ - DOP_CONST_STRING_JUMBO, /* const-string/jumbo (0x1b) */ - DOP_CONST_CLASS, /* const-class (0x1c) */ - DOP_MONITOR_ENTER, /* monitor-enter (0x1d) */ - DOP_MONITOR_EXIT, /* monitor-exit (0x1e) */ - DOP_CHECK_CAST, /* check-cast (0x1f) */ - DOP_INSTANCE_OF, /* instance-of (0x20) */ - DOP_ARRAY_LENGTH, /* array-length (0x21) */ - DOP_NEW_INSTANCE, /* new-instance (0x22) */ - DOP_NEW_ARRAY, /* new-array (0x23) */ - DOP_FILLED_NEW_ARRAY, /* filled-new-array (0x24) */ - DOP_FILLED_NEW_ARRAY_RANGE, /* filled-new-array/range(0x25)*/ - DOP_FILL_ARRAY_DATA, /* fill-array-data (0x26) */ - DOP_THROW, /* throw (0x27) */ - DOP_GOTO, /* goto (0x28) */ - DOP_GOTO_16, /* goto/16 (0x29) */ - DOP_GOTO_32, /* goto/32 (0x2a) */ - DOP_PACKED_SWITCH, /* packed-switch (0x2b) */ - DOP_SPARSE_SWITCH, /* sparse-switch (0x2c) */ - DOP_CMPL_FLOAT, /* cmp-long (0x2d) */ - DOP_CMPG_FLOAT, /* cmpg-float (0x2e) */ - DOP_CMPL_DOUBLE, /* cmpl-double (0x2f) */ - DOP_CMPG_DOUBLE, /* cmpg-double (0x30) */ - DOP_CMP_LONG, /* cmp-long (0x31) */ - DOP_IF_EQ, /* if-eq (0x32) */ - DOP_IF_NE, /* if-ne (0x33) */ - DOP_IF_LT, /* if-lt (0x34) */ - DOP_IF_GE, /* if-ge (0x35) */ - DOP_IF_GT, /* if-gt (0x36) */ - DOP_IF_LE, /* if-le (0x37) */ - DOP_IF_EQZ, /* if-eqz (0x38) */ - DOP_IF_NEZ, /* if-nez (0x39) */ - DOP_IF_LTZ, /* if-ltz (0x3a) */ - DOP_IF_GEZ, /* if-gez (0x3b) */ - DOP_IF_GTZ, /* if-gtz (0x3c) */ - DOP_IF_LEZ, /* if-lez (0x3d) */ - DOP_UNUSED_3E, /* -unused- (0x3e) */ - DOP_UNUSED_3F, /* -unused- (0x3f) */ - DOP_UNUSED_40, /* -unused- (0x40) */ - DOP_UNUSED_41, /* -unused- (0x41) */ - DOP_UNUSED_42, /* -unused- (0x42) */ - DOP_UNUSED_43, /* -unused- (0x43) */ - DOP_AGET, /* aget (0x44) */ - DOP_AGET_WIDE, /* aget-wide (0x45) */ - DOP_AGET_OBJECT, /* aget-object (0x46) */ - DOP_AGET_BOOLEAN, /* aget-boolean (0x47) */ - DOP_AGET_BYTE, /* aget-byte (0x48) */ - DOP_AGET_CHAR, /* aget-char (0x49) */ - DOP_AGET_SHORT, /* aget-short (0x4a) */ - DOP_APUT, /* aput (0x4b) */ - DOP_APUT_WIDE, /* aput-wide (0x4c) */ - DOP_APUT_OBJECT, /* aput-object (0x4d) */ - DOP_APUT_BOOLEAN, /* aput-boolean (0x4e) */ - DOP_APUT_BYTE, /* aput-byte (0x4f) */ - DOP_APUT_CHAR, /* aput-char (0x50) */ - DOP_APUT_SHORT, /* aput-short (0x51) */ - DOP_IGET, /* iget (0x52) */ - DOP_IGET_WIDE, /* iget-wide (0x53) */ - DOP_IGET_OBJECT, /* iget-object (0x54) */ - DOP_IGET_BOOLEAN, /* iget-boolean (0x55) */ - DOP_IGET_BYTE, /* iget-byte (0x56) */ - DOP_IGET_CHAR, /* iget-char (0x57) */ - DOP_IGET_SHORT, /* iget-short (0x58) */ - DOP_IPUT, /* iput (0x59) */ - DOP_IPUT_WIDE, /* iput-wide (0x5a) */ - DOP_IPUT_OBJECT, /* iput-object (0x5b) */ - DOP_IPUT_BOOLEAN, /* iput-boolean (0x5c) */ - DOP_IPUT_BYTE, /* iput-byte (0x5d) */ - DOP_IPUT_CHAR, /* iput-char (0x5e) */ - DOP_IPUT_SHORT, /* iput-short (0x5f) */ - DOP_SGET, /* sget (0x60) */ - DOP_SGET_WIDE, /* sget-wide (0x61) */ - DOP_SGET_OBJECT, /* sget-object (0x62) */ - DOP_SGET_BOOLEAN, /* sget-boolean (0x63) */ - DOP_SGET_BYTE, /* sget-byte (0x64) */ - DOP_SGET_CHAR, /* sget-char (0x65) */ - DOP_SGET_SHORT, /* sget-short (0x66) */ - DOP_SPUT, /* sput (0x67) */ - DOP_SPUT_WIDE, /* sput-wide (0x68) */ - DOP_SPUT_OBJECT, /* sput-object (0x69) */ - DOP_SPUT_BOOLEAN, /* sput-boolean (0x6a) */ - DOP_SPUT_BYTE, /* sput-byte (0x6b) */ - DOP_SPUT_CHAR, /* sput-char (0x6c) */ - DOP_SPUT_SHORT, /* sput-short (0x6d) */ - DOP_INVOKE_VIRTUAL, /* invoke-virtual (0x6e) */ - DOP_INVOKE_SUPER, /* invoke-super (0x6f) */ - DOP_INVOKE_DIRECT, /* invoke-direct (0x70) */ - DOP_INVOKE_STATIC, /* invoke-static (0x71) */ - DOP_INVOKE_INTERFACE, /* invoke-interface (0x72) */ - DOP_UNUSED_73, /* -unused- (0x73) */ - DOP_INVOKE_VIRTUAL_RANGE, /* invoke-virtual/range (0x74) */ - DOP_INVOKE_SUPER_RANGE, /* invoke-super/range (0x75) */ - DOP_INVOKE_DIRECT_RANGE, /* invoke-direct/range (0x76) */ - DOP_INVOKE_STATIC_RANGE, /* invoke-static/range (0x77) */ - DOP_INVOKE_INTERFACE_RANGE, /* invoke-interface/rg. (0x78) */ - DOP_UNUSED_79, /* -unused- (0x79) */ - DOP_UNUSED_7A, /* -unused- (0x7a) */ - DOP_NEG_INT, /* neg-int (0x7b) */ - DOP_NOT_INT, /* not-int (0x7c) */ - DOP_NEG_LONG, /* neg-long (0x7d) */ - DOP_NOT_LONG, /* not-long (0x7e) */ - DOP_NEG_FLOAT, /* neg-float (0x7f) */ - DOP_NEG_DOUBLE, /* neg-double (0x80) */ - DOP_TO_INT_LONG, /* int-to-long (0x81) */ - DOP_TO_INT_FLOAT, /* int-to-float (0x82) */ - DOP_TO_INT_DOUBLE, /* int-to-double (0x83) */ - DOP_TO_LONG_INT, /* long-to-int (0x84) */ - DOP_TO_LONG_FLOAT, /* long-to-float (0x85) */ - DOP_TO_LONG_DOUBLE, /* long-to-double (0x86) */ - DOP_TO_FLOAT_INT, /* float-to-int (0x87) */ - DOP_TO_FLOAT_LONG, /* float-to-long (0x88) */ - DOP_TO_FLOAT_DOUBLE, /* float-to-double (0x89) */ - DOP_TO_DOUBLE_INT, /* double-to-int (0x8a) */ - DOP_TO_DOUBLE_LONG, /* double-to-long (0x8b) */ - DOP_TO_DOUBLE_FLOAT, /* double-to-float (0x8c) */ - DOP_TO_INT_BYTE, /* int-to-byte (0x8d) */ - DOP_TO_INT_CHAR, /* int-to-char (0x8e) */ - DOP_TO_INT_SHORT, /* int-to-short (0x8f) */ - DOP_ADD_INT, /* add-int (0x90) */ - DOP_SUB_INT, /* sub-int (0x91) */ - DOP_MUL_INT, /* mul-int (0x92) */ - DOP_DIV_INT, /* div-int (0x93) */ - DOP_REM_INT, /* rem-int (0x94) */ - DOP_AND_INT, /* and-int (0x95) */ - DOP_OR_INT, /* or-int (0x96) */ - DOP_XOR_INT, /* xor-int (0x97) */ - DOP_SHL_INT, /* shl-int (0x98) */ - DOP_SHR_INT, /* shr-int (0x99) */ - DOP_USHR_INT, /* ushr-int (0x9a) */ - DOP_ADD_LONG, /* add-long (0x9b) */ - DOP_SUB_LONG, /* sub-long (0x9c) */ - DOP_MUL_LONG, /* mul-long (0x9d) */ - DOP_DIV_LONG, /* div-long (0x9e) */ - DOP_REM_LONG, /* rem-long (0x9f) */ - DOP_AND_LONG, /* and-long (0xa0) */ - DOP_OR_LONG, /* or-long (0xa1) */ - DOP_XOR_LONG, /* xor-long (0xa2) */ - DOP_SHL_LONG, /* shl-long (0xa3) */ - DOP_SHR_LONG, /* shr-long (0xa4) */ - DOP_USHR_LONG, /* ushr-long (0xa5) */ - DOP_ADD_FLOAT, /* add-float (0xa6) */ - DOP_SUB_FLOAT, /* sub-float (0xa7) */ - DOP_MUL_FLOAT, /* mul-float (0xa8) */ - DOP_DIV_FLOAT, /* mul-float (0xa9) */ - DOP_REM_FLOAT, /* mul-float (0xaa) */ - DOP_ADD_DOUBLE, /* add-double (0xab) */ - DOP_SUB_DOUBLE, /* sub-double (0xac) */ - DOP_MUL_DOUBLE, /* mul-double (0xad) */ - DOP_DIV_DOUBLE, /* div-double (0xae) */ - DOP_REM_DOUBLE, /* rem-double (0xaf) */ - DOP_ADD_INT_2ADDR, /* add-int/2addr (0xb0) */ - DOP_SUB_INT_2ADDR, /* add-int/2addr (0xb1) */ - DOP_MUL_INT_2ADDR, /* mul-int/2addr (0xb2) */ - DOP_DIV_INT_2ADDR, /* div-int/2addr (0xb3) */ - DOP_REM_INT_2ADDR, /* rem-int/2addr (0xb4) */ - DOP_AND_INT_2ADDR, /* and-int/2addr (0xb5) */ - DOP_OR_INT_2ADDR, /* or-int/2addr (0xb6) */ - DOP_XOR_INT_2ADDR, /* xor-int/2addr (0xb7) */ - DOP_SHL_INT_2ADDR, /* shl-int/2addr (0xb8) */ - DOP_SHR_INT_2ADDR, /* shr-int/2addr (0xb9) */ - DOP_USHR_INT_2ADDR, /* ushr-int/2addr (0xba) */ - DOP_ADD_LONG_2ADDR, /* add-long/2addr (0xbb) */ - DOP_SUB_LONG_2ADDR, /* sub-long/2addr (0xbc) */ - DOP_MUL_LONG_2ADDR, /* mul-long/2addr (0xbd) */ - DOP_DIV_LONG_2ADDR, /* div-long/2addr (0xbe) */ - DOP_REM_LONG_2ADDR, /* rem-long/2addr (0xbf) */ - DOP_AND_LONG_2ADDR, /* and-long/2addr (0xc0) */ - DOP_OR_LONG_2ADDR, /* or-long/2addr (0xc1) */ - DOP_XOR_LONG_2ADDR, /* xor-long/2addr (0xc2) */ - DOP_SHL_LONG_2ADDR, /* shl-long/2addr (0xc3) */ - DOP_SHR_LONG_2ADDR, /* shr-long/2addr (0xc4) */ - DOP_USHR_LONG_2ADDR, /* ushr-long/2addr (0xc5) */ - DOP_ADD_FLOAT_2ADDR, /* add-float/2addr (0xc6) */ - DOP_SUB_FLOAT_2ADDR, /* sub-float/2addr (0xc7) */ - DOP_MUL_FLOAT_2ADDR, /* mul-float/2addr (0xc8) */ - DOP_DIV_FLOAT_2ADDR, /* div-float/2addr (0xc9) */ - DOP_REM_FLOAT_2ADDR, /* rem-float/2addr (0xca) */ - DOP_ADD_DOUBLE_2ADDR, /* add-double/2addr (0xcb) */ - DOP_SUB_DOUBLE_2ADDR, /* sub-double/2addr (0xcc) */ - DOP_MUL_DOUBLE_2ADDR, /* mul-double/2addr (0xcd) */ - DOP_DIV_DOUBLE_2ADDR, /* div-double/2addr (0xce) */ - DOP_REM_DOUBLE_2ADDR, /* rem-double/2addr (0xcf) */ - DOP_ADD_INT_LIT16, /* add-int/lit16 (0xd0) */ - DOP_RSUB_INT, /* rsub-int (0xd1) */ - DOP_MUL_INT_LIT16, /* mul-int/lit16 (0xd2) */ - DOP_DIV_INT_LIT16, /* div-int/lit16 (0xd3) */ - DOP_REM_INT_LIT16, /* rem-int/lit16 (0xd4) */ - DOP_AND_INT_LIT16, /* and-int/lit16 (0xd5) */ - DOP_OR_INT_LIT16, /* or-int/lit16 (0xd6) */ - DOP_XOR_INT_LIT16, /* xor-int/lit16 (0xd7) */ - DOP_ADD_INT_LIT8, /* add-int/lit8 (0xd8) */ - DOP_RSUB_INT_LIT8, /* rsub-int/lit8 (0xd9) */ - DOP_MUL_INT_LIT8, /* mul-int/lit8 (0xda) */ - DOP_DIV_INT_LIT8, /* div-int/lit8 (0xdb) */ - DOP_REM_INT_LIT8, /* rem-int/lit8 (0xdc) */ - DOP_AND_INT_LIT8, /* and-int/lit8 (0xdd) */ - DOP_OR_INT_LIT8, /* or-int/lit8 (0xde) */ - DOP_XOR_INT_LIT8, /* xor-int/lit8 (0xdf) */ - DOP_SHL_INT_LIT8, /* shl-int/lit8 (0xe0) */ - DOP_SHR_INT_LIT8, /* shr-int/lit8 (0xe1) */ - DOP_USHR_INT_LIT8, /* ushr-int/lit8 (0xe2) */ - DOP_UNUSED_E3, /* -unused- (0xe3) */ - DOP_UNUSED_E4, /* -unused- (0xe4) */ - DOP_UNUSED_E5, /* -unused- (0xe5) */ - DOP_UNUSED_E6, /* -unused- (0xe6) */ - DOP_UNUSED_E7, /* -unused- (0xe7) */ - DOP_UNUSED_E8, /* -unused- (0xe8) */ - DOP_UNUSED_E9, /* -unused- (0xe9) */ - DOP_UNUSED_EA, /* -unused- (0xea) */ - DOP_UNUSED_EB, /* -unused- (0xeb) */ - DOP_UNUSED_EC, /* -unused- (0xec) */ - DOP_UNUSED_ED, /* -unused- (0xed) */ - DOP_UNUSED_EE, /* -unused- (0xee) */ - DOP_UNUSED_EF, /* -unused- (0xef) */ - DOP_UNUSED_F0, /* -unused- (0xf0) */ - DOP_UNUSED_F1, /* -unused- (0xf1) */ - DOP_UNUSED_F2, /* -unused- (0xf2) */ - DOP_UNUSED_F3, /* -unused- (0xf3) */ - DOP_UNUSED_F4, /* -unused- (0xf4) */ - DOP_UNUSED_F5, /* -unused- (0xf5) */ - DOP_UNUSED_F6, /* -unused- (0xf6) */ - DOP_UNUSED_F7, /* -unused- (0xf7) */ - DOP_UNUSED_F8, /* -unused- (0xf8) */ - DOP_UNUSED_F9, /* -unused- (0xf9) */ - DOP_UNUSED_FA, /* -unused- (0xfa) */ - DOP_UNUSED_FB, /* -unused- (0xfb) */ - DOP_UNUSED_FC, /* -unused- (0xfc) */ - DOP_UNUSED_FD, /* -unused- (0xfd) */ - DOP_UNUSED_FE, /* -unused- (0xfe) */ - DOP_UNUSED_FF, /* -unused- (0xff) */ - - DOP_COUNT - -} DalvikOpcodes; - - -/* Enumération de tous les pseudo-opcodes */ -typedef enum _DalvikPseudoOpcodes -{ - DPO_PACKED_SWITCH = 0x0100, /* Switch aux clefs compactes */ - DPO_SPARSE_SWITCH = 0x0200, /* Switch aux clefs éclatées */ - DPO_FILL_ARRAY_DATA = 0x0300 /* Contenu de tableau */ - -} DalvikPseudoOpcodes; - - - -#endif /* _ARCH_DALVIK_INSTRUCTION_DEF_H */ diff --git a/plugins/dalvik/instruction-int.h b/plugins/dalvik/instruction-int.h index b4e59b0..847b112 100644 --- a/plugins/dalvik/instruction-int.h +++ b/plugins/dalvik/instruction-int.h @@ -21,14 +21,14 @@ */ -#ifndef _ARCH_DALVIK_INSTRUCTION_INT_H -#define _ARCH_DALVIK_INSTRUCTION_INT_H +#ifndef _PLUGINS_DALVIK_INSTRUCTION_INT_H +#define _PLUGINS_DALVIK_INSTRUCTION_INT_H -#include <arch/instruction-int.h> +#include "instruction.h" -#include "instruction-def.h" +#include <arch/instruction-int.h> @@ -37,11 +37,6 @@ struct _GDalvikInstruction { GArchInstruction parent; /* A laisser en premier */ - const char *keyword; /* Nom clef de l'instruction */ - - DalvikOpcodes type; /* Position dans la liste */ - DalvikPseudoOpcodes ptype; /* Position dans la liste #2 */ - }; /* Définition générique d'une instruction d'architecture Dalvik (classe) */ @@ -53,4 +48,4 @@ struct _GDalvikInstructionClass -#endif /* _ARCH_DALVIK_INSTRUCTION_INT_H */ +#endif /* _PLUGINS_DALVIK_INSTRUCTION_INT_H */ diff --git a/plugins/dalvik/instruction.c b/plugins/dalvik/instruction.c index 7105dc9..bd41cf9 100644 --- a/plugins/dalvik/instruction.c +++ b/plugins/dalvik/instruction.c @@ -32,7 +32,6 @@ #include "instruction-int.h" -#include "operands/register.h" @@ -48,12 +47,6 @@ static void g_dalvik_instruction_dispose(GDalvikInstruction *); /* Procède à la libération totale de la mémoire. */ static void g_dalvik_instruction_finalize(GDalvikInstruction *); -/* Indique l'encodage d'une instruction de façon détaillée. */ -static const char *g_dalvik_instruction_get_encoding(const GDalvikInstruction *); - -/* Fournit le nom humain de l'instruction manipulée. */ -static const char *g_dalvik_instruction_get_keyword(const GDalvikInstruction *, AsmSyntax); - /* Construit un petit résumé concis de l'instruction. */ static char *g_dalvik_instruction_build_tooltip(const GDalvikInstruction *); @@ -63,7 +56,6 @@ static char *g_dalvik_instruction_build_tooltip(const GDalvikInstruction *); G_DEFINE_TYPE(GDalvikInstruction, g_dalvik_instruction, G_TYPE_ARCH_INSTRUCTION); - /****************************************************************************** * * * Paramètres : klass = classe à initialiser. * @@ -88,8 +80,6 @@ static void g_dalvik_instruction_class_init(GDalvikInstructionClass *klass) instr = G_ARCH_INSTRUCTION_CLASS(klass); - instr->get_encoding = (get_instruction_encoding_fc)g_dalvik_instruction_get_encoding; - instr->get_keyword = (get_instruction_keyword_fc)g_dalvik_instruction_get_keyword; instr->build_tooltip = (build_instruction_tooltip_fc)g_dalvik_instruction_build_tooltip; } @@ -153,74 +143,6 @@ static void g_dalvik_instruction_finalize(GDalvikInstruction *instr) /****************************************************************************** * * -* Paramètres : keyword = définition du nom humaine de l'instruction. * -* * -* Description : Crée une instruction pour l'architecture Dalvik. * -* * -* Retour : Adresse de la structure mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchInstruction *g_dalvik_instruction_new(const char *keyword) -{ - GArchInstruction *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_DALVIK_INSTRUCTION, NULL); - - G_DALVIK_INSTRUCTION(result)->keyword = keyword; - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction quelconque à consulter. * -* * -* Description : Indique l'encodage d'une instruction de façon détaillée. * -* * -* Retour : Description humaine de l'encodage utilisé. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static const char *g_dalvik_instruction_get_encoding(const GDalvikInstruction *instr) -{ - const char *result; /* Description à retourner */ - - result = "Dalvik"; - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : instr = instruction d'assemblage à consulter. * -* syntax = type de représentation demandée. * -* * -* Description : Fournit le nom humain de l'instruction manipulée. * -* * -* Retour : Mot clef de bas niveau. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static const char *g_dalvik_instruction_get_keyword(const GDalvikInstruction *instr, AsmSyntax syntax) -{ - return instr->keyword; - -} - - -/****************************************************************************** -* * * Paramètres : instr = instruction Dalvik à consulter. * * * * Description : Construit un petit résumé concis de l'instruction. * @@ -240,22 +162,3 @@ static char *g_dalvik_instruction_build_tooltip(const GDalvikInstruction *instr) return result; } - - -/****************************************************************************** -* * -* Paramètres : instr = instruction Dalvik à consulter. * -* * -* Description : Indique l'opcode associé à une instruction Dalvik. * -* * -* Retour : Identifiant de l'instruction en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -DalvikOpcodes g_dalvik_instruction_get_opcode(const GDalvikInstruction *instr) -{ - return instr->type; - -} diff --git a/plugins/dalvik/instruction.h b/plugins/dalvik/instruction.h index 8f05cc5..e11a249 100644 --- a/plugins/dalvik/instruction.h +++ b/plugins/dalvik/instruction.h @@ -21,16 +21,13 @@ */ -#ifndef _ARCH_DALVIK_INSTRUCTION_H -#define _ARCH_DALVIK_INSTRUCTION_H +#ifndef _PLUGINS_DALVIK_INSTRUCTION_H +#define _PLUGINS_DALVIK_INSTRUCTION_H #include <arch/instruction.h> -#include "instruction-def.h" - - #define G_TYPE_DALVIK_INSTRUCTION g_dalvik_instruction_get_type() #define G_DALVIK_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), g_dalvik_instruction_get_type(), GDalvikInstruction)) @@ -48,21 +45,6 @@ typedef struct _GDalvikInstructionClass GDalvikInstructionClass; /* Indique le type défini pour une instruction d'architecture Dalvik. */ GType g_dalvik_instruction_get_type(void); -/* Crée une instruction pour l'architecture Dalvik. */ -GArchInstruction *g_dalvik_instruction_new(const char *); - -/* Indique l'opcode associé à une instruction Dalvik. */ -DalvikOpcodes g_dalvik_instruction_get_opcode(const struct _GDalvikInstruction *); - - - -/* --------------------- AIDE A LA MISE EN PLACE D'INSTRUCTIONS --------------------- */ - - - - -/* ------------------------ AIDE A LA PHASE DE DECOMPILATION ------------------------ */ - -#endif /* _ARCH_DALVIK_INSTRUCTION_H */ +#endif /* _PLUGINS_DALVIK_INSTRUCTION_H */ diff --git a/plugins/dalvik/link.h b/plugins/dalvik/link.h index 41d03ec..36584b2 100644 --- a/plugins/dalvik/link.h +++ b/plugins/dalvik/link.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_LINK_H -#define _ARCH_DALVIK_LINK_H +#ifndef _PLUGINS_DALVIK_LINK_H +#define _PLUGINS_DALVIK_LINK_H #include <arch/link.h> @@ -45,4 +45,4 @@ void handle_dalvik_packed_switch_links(GArchInstruction *, GArchProcessor *, GPr -#endif /* _ARCH_DALVIK_LINK_H */ +#endif /* _PLUGINS_DALVIK_LINK_H */ diff --git a/plugins/dalvik/opdefs/invoke_6e.d b/plugins/dalvik/opdefs/invoke_6e.d deleted file mode 100644 index e7b3f0d..0000000 --- a/plugins/dalvik/opdefs/invoke_6e.d +++ /dev/null @@ -1,30 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions Dalvik - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title invoke-virtual - -@encoding() { - - @format 35c | pool_meth - -} diff --git a/plugins/dalvik/opdefs/invoke_6f.d b/plugins/dalvik/opdefs/invoke_6f.d deleted file mode 100644 index 9fa4666..0000000 --- a/plugins/dalvik/opdefs/invoke_6f.d +++ /dev/null @@ -1,30 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions Dalvik - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title invoke-super - -@encoding() { - - @format 35c | pool_meth - -} diff --git a/plugins/dalvik/opdefs/invoke_70.d b/plugins/dalvik/opdefs/invoke_70.d deleted file mode 100644 index 6662ce3..0000000 --- a/plugins/dalvik/opdefs/invoke_70.d +++ /dev/null @@ -1,30 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions Dalvik - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title invoke-direct - -@encoding() { - - @format 35c | pool_meth - -} diff --git a/plugins/dalvik/opdefs/invoke_71.d b/plugins/dalvik/opdefs/invoke_71.d deleted file mode 100644 index f179dbd..0000000 --- a/plugins/dalvik/opdefs/invoke_71.d +++ /dev/null @@ -1,30 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions Dalvik - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title invoke-static - -@encoding() { - - @format 35c | pool_meth - -} diff --git a/plugins/dalvik/opdefs/invoke_72.d b/plugins/dalvik/opdefs/invoke_72.d deleted file mode 100644 index 6ad8e09..0000000 --- a/plugins/dalvik/opdefs/invoke_72.d +++ /dev/null @@ -1,30 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions Dalvik - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title invoke-interface - -@encoding() { - - @format 35c | pool_meth - -} diff --git a/plugins/dalvik/opdefs/nop_00.d b/plugins/dalvik/opdefs/nop_00.d deleted file mode 100644 index d10d439..0000000 --- a/plugins/dalvik/opdefs/nop_00.d +++ /dev/null @@ -1,30 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions Dalvik - * - * Copyright (C) 2015 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Foobar. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title nop - -@encoding() { - - @format 10x - -} diff --git a/plugins/dalvik/operand.h b/plugins/dalvik/operand.h index b34c87c..f5ef9ed 100644 --- a/plugins/dalvik/operand.h +++ b/plugins/dalvik/operand.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_OPERAND_H -#define _ARCH_DALVIK_OPERAND_H +#ifndef _PLUGINS_DALVIK_OPERAND_H +#define _PLUGINS_DALVIK_OPERAND_H #include <arch/instruction.h> @@ -122,4 +122,4 @@ void dalvik_mark_first_operand_as_written(GArchInstruction *); -#endif /* _ARCH_DALVIK_OPERAND_H */ +#endif /* _PLUGINS_DALVIK_OPERAND_H */ diff --git a/plugins/dalvik/operands/args.h b/plugins/dalvik/operands/args.h index 354333d..9c4ba84 100644 --- a/plugins/dalvik/operands/args.h +++ b/plugins/dalvik/operands/args.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_OPERANDS_ARGS_H -#define _ARCH_DALVIK_OPERANDS_ARGS_H +#ifndef _PLUGINS_DALVIK_OPERANDS_ARGS_H +#define _PLUGINS_DALVIK_OPERANDS_ARGS_H #include <glib-object.h> @@ -64,4 +64,4 @@ GArchOperand *g_dalvik_args_operand_get(const GDalvikArgsOperand *, size_t); -#endif /* _ARCH_DALVIK_OPERANDS_ARGS_H */ +#endif /* _PLUGINS_DALVIK_OPERANDS_ARGS_H */ diff --git a/plugins/dalvik/operands/pool.h b/plugins/dalvik/operands/pool.h index 3045a2c..d4e9722 100644 --- a/plugins/dalvik/operands/pool.h +++ b/plugins/dalvik/operands/pool.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_OPERANDS_POOL_H -#define _ARCH_DALVIK_OPERANDS_POOL_H +#ifndef _PLUGINS_DALVIK_OPERANDS_POOL_H +#define _PLUGINS_DALVIK_OPERANDS_POOL_H #include <glib-object.h> @@ -77,4 +77,4 @@ uint32_t g_dalvik_pool_operand_get_index(const GDalvikPoolOperand *); -#endif /* _ARCH_DALVIK_OPERANDS_POOL_H */ +#endif /* _PLUGINS_DALVIK_OPERANDS_POOL_H */ diff --git a/plugins/dalvik/operands/register.h b/plugins/dalvik/operands/register.h index f1dec72..58be978 100644 --- a/plugins/dalvik/operands/register.h +++ b/plugins/dalvik/operands/register.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_OPERANDS_REGISTER_H -#define _ARCH_DALVIK_OPERANDS_REGISTER_H +#ifndef _PLUGINS_DALVIK_OPERANDS_REGISTER_H +#define _PLUGINS_DALVIK_OPERANDS_REGISTER_H #include <glib-object.h> @@ -72,4 +72,4 @@ bool g_dalvik_register_operand_is_written(const GDalvikRegisterOperand *); -#endif /* _ARCH_DALVIK_OPERANDS_REGISTER_H */ +#endif /* _PLUGINS_DALVIK_OPERANDS_REGISTER_H */ diff --git a/plugins/dalvik/post.h b/plugins/dalvik/post.h index 63d35c3..7c867fd 100644 --- a/plugins/dalvik/post.h +++ b/plugins/dalvik/post.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_POST_H -#define _ARCH_DALVIK_POST_H +#ifndef _PLUGINS_DALVIK_POST_H +#define _PLUGINS_DALVIK_POST_H #include <arch/post.h> @@ -49,4 +49,4 @@ static inline void post_process_dalvik_ifz_target_resolution(GArchInstruction *i -#endif /* _ARCH_DALVIK_POST_H */ +#endif /* _PLUGINS_DALVIK_POST_H */ diff --git a/plugins/dalvik/processor-int.h b/plugins/dalvik/processor-int.h new file mode 100644 index 0000000..6d551fa --- /dev/null +++ b/plugins/dalvik/processor-int.h @@ -0,0 +1,59 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * processor-int.h - prototypes pour la définition générique interne du processeur de la VM Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _PLUGINS_DALVIK_PROCESSOR_INT_H +#define _PLUGINS_DALVIK_PROCESSOR_INT_H + + +#include "processor.h" + + +#include <arch/processor-int.h> + + +#include "context.h" + + + +/* Définition du processeur de la VM Dalvik (instance) */ +struct _GDalvikProcessor +{ + GArchProcessor parent; /* Instance parente */ + +}; + + +/* Définition du processeur de la VM Dalvik (classe) */ +struct _GDalvikProcessorClass +{ + GArchProcessorClass parent; /* Classe parente */ + +}; + + +/* Décode une pseudo-instruction dans un flux de données. */ +GArchInstruction *g_dalvik_processor_disassemble_pseudo(const GArchProcessor *, GDalvikContext *, const GBinContent *, vmpa2t *, uint8_t); + + + +#endif /* _PLUGINS_DALVIK_PROCESSOR_INT_H */ diff --git a/plugins/dalvik/processor.c b/plugins/dalvik/processor.c index ff8b805..c3bce8f 100644 --- a/plugins/dalvik/processor.c +++ b/plugins/dalvik/processor.c @@ -27,34 +27,17 @@ #include <assert.h> -#include <arch/processor-int.h> #include <plugins/dex/format.h> -#include "context.h" #include "instruction.h" -#include "opcodes/opcodes.h" +#include "processor-int.h" #include "pseudo/fill.h" +#include "pseudo/identifiers.h" #include "pseudo/switch.h" -/* Définition du processeur de la VM Dalvik (instance) */ -struct _GDalvikProcessor -{ - GArchProcessor parent; /* Instance parente */ - -}; - - -/* Définition du processeur de la VM Dalvik (classe) */ -struct _GDalvikProcessorClass -{ - GArchProcessorClass parent; /* Classe parente */ - -}; - - /* Initialise la classe des processeurs de VM Dalvik. */ static void g_dalvik_processor_class_init(GDalvikProcessorClass *); @@ -73,19 +56,12 @@ static GDalvikContext *g_dalvik_processor_get_context(const GDalvikProcessor *); /* Fournit un contexte pour la décompilation Dalvik. */ //static GDalvikDContext *g_dalvik_processor_get_decomp_context(const GDalvikProcessor *); -/* Décode une instruction dans un flux de données. */ -static GArchInstruction *g_dalvik_processor_disassemble(const GArchProcessor *, GDalvikContext *, const GBinContent *, vmpa2t *, GExeFormat *); - -/* Décode une pseudo-instruction dans un flux de données. */ -static GArchInstruction *g_dalvik_processor_disassemble_pseudo(const GArchProcessor *, GDalvikContext *, const GBinContent *, vmpa2t *, uint8_t); - /* Indique le type défini par la GLib pour le processeur DALVIK. */ G_DEFINE_TYPE(GDalvikProcessor, g_dalvik_processor, G_TYPE_ARCH_PROCESSOR); - /****************************************************************************** * * * Paramètres : klass = classe à initialiser. * @@ -113,8 +89,6 @@ static void g_dalvik_processor_class_init(GDalvikProcessorClass *klass) proc->get_ctx = (get_processor_context_fc)g_dalvik_processor_get_context; //proc->get_dec_ctx = (get_decomp_context_fc)g_dalvik_processor_get_decomp_context; - proc->disassemble = (disass_instr_fc)g_dalvik_processor_disassemble; - } @@ -183,29 +157,6 @@ static void g_dalvik_processor_finalize(GDalvikProcessor *proc) /****************************************************************************** * * -* Paramètres : - * -* * -* Description : Crée le support de l'architecture Dalvik. * -* * -* Retour : Architecture mise en place. * -* * -* Remarques : - * -* * -******************************************************************************/ - -GArchProcessor *g_dalvik_processor_new(void) -{ - GArchProcessor *result; /* Structure à retourner */ - - result = g_object_new(G_TYPE_DALVIK_PROCESSOR, NULL); - - return result; - -} - - -/****************************************************************************** -* * * Paramètres : proc = architecture, spectatrice ici. * * * * Description : Fournit un contexte pour l'exécution du processeur Dalvik. * @@ -245,282 +196,6 @@ static GDalvikDContext *g_dalvik_processor_get_decomp_context(const GDalvikProce /****************************************************************************** * * -* Paramètres : proc = architecture visée par la procédure. * -* ctx = contexte lié à l'exécution du processeur. * -* content = flux de données à analyser. * -* pos = position courante dans ce flux. [OUT] * -* format = format du fichier contenant le code. * -* * -* Description : Désassemble une instruction dans un flux de données. * -* * -* Retour : Instruction mise en place ou NULL en cas d'échec. * -* * -* Remarques : - * -* * -******************************************************************************/ - -static GArchInstruction *g_dalvik_processor_disassemble(const GArchProcessor *proc, GDalvikContext *ctx, const GBinContent *content, vmpa2t *pos, GExeFormat *format) -{ - GArchInstruction *result; /* Instruction à renvoyer */ - uint8_t raw8; /* Donnée de 8 bits à analyser */ - DalvikOpcodes id; /* Identifiant d'instruction */ - - static const disass_instr_fc decodings[DOP_COUNT] = { - - [DOP_NOP] = dalvik_read_instr_nop, - [DOP_MOVE] = dalvik_read_instr_move, - [DOP_MOVE_FROM_16] = dalvik_read_instr_move_from16, - [DOP_MOVE_16] = dalvik_read_instr_move_16, - [DOP_MOVE_WIDE] = dalvik_read_instr_move_wide, - [DOP_MOVE_WIDE_FROM_16] = dalvik_read_instr_move_wide_from16, - [DOP_MOVE_WIDE_16] = dalvik_read_instr_move_wide_16, - [DOP_MOVE_OBJECT] = dalvik_read_instr_move_object, - [DOP_MOVE_OBJECT_FROM_16] = dalvik_read_instr_move_object_from16, - [DOP_MOVE_OBJECT_16] = dalvik_read_instr_move_object_16, - [DOP_MOVE_RESULT] = dalvik_read_instr_move_result, - [DOP_MOVE_RESULT_WIDE] = dalvik_read_instr_move_result_wide, - [DOP_MOVE_RESULT_OBJECT] = dalvik_read_instr_move_result_object, - [DOP_MOVE_EXCEPTION] = dalvik_read_instr_move_exception, - [DOP_RETURN_VOID] = dalvik_read_instr_return_void, - [DOP_RETURN] = dalvik_read_instr_return, - [DOP_RETURN_WIDE] = dalvik_read_instr_return_wide, - [DOP_RETURN_OBJECT] = dalvik_read_instr_return_object, - [DOP_CONST_4] = dalvik_read_instr_const_4, - [DOP_CONST_16] = dalvik_read_instr_const_16, - [DOP_CONST] = dalvik_read_instr_const, - [DOP_CONST_HIGH16] = dalvik_read_instr_const_high16, - [DOP_CONST_WIDE_16] = dalvik_read_instr_const_wide_16, - [DOP_CONST_WIDE_32] = dalvik_read_instr_const_wide_32, - [DOP_CONST_WIDE] = dalvik_read_instr_const_wide, - [DOP_CONST_WIDE_HIGH16] = dalvik_read_instr_const_wide_high16, - [DOP_CONST_STRING] = dalvik_read_instr_const_string, - [DOP_CONST_STRING_JUMBO] = dalvik_read_instr_const_string_jumbo, - [DOP_CONST_CLASS] = dalvik_read_instr_const_class, - [DOP_MONITOR_ENTER] = dalvik_read_instr_monitor_enter, - [DOP_MONITOR_EXIT] = dalvik_read_instr_monitor_exit, - [DOP_CHECK_CAST] = dalvik_read_instr_check_cast, - [DOP_INSTANCE_OF] = dalvik_read_instr_instance_of, - [DOP_ARRAY_LENGTH] = dalvik_read_instr_array_length, - [DOP_NEW_INSTANCE] = dalvik_read_instr_new_instance, - [DOP_NEW_ARRAY] = dalvik_read_instr_new_array, - [DOP_FILLED_NEW_ARRAY] = dalvik_read_instr_filled_new_array, - [DOP_FILLED_NEW_ARRAY_RANGE]= dalvik_read_instr_filled_new_array_range, - [DOP_FILL_ARRAY_DATA] = dalvik_read_instr_fill_array_data, - [DOP_THROW] = dalvik_read_instr_throw, - [DOP_GOTO] = dalvik_read_instr_goto, - [DOP_GOTO_16] = dalvik_read_instr_goto_16, - [DOP_GOTO_32] = dalvik_read_instr_goto_32, - [DOP_PACKED_SWITCH] = dalvik_read_instr_packed_switch, - [DOP_SPARSE_SWITCH] = dalvik_read_instr_sparse_switch, - [DOP_CMPL_FLOAT] = dalvik_read_instr_cmpl_float, - [DOP_CMPG_FLOAT] = dalvik_read_instr_cmpg_float, - [DOP_CMPL_DOUBLE] = dalvik_read_instr_cmpl_double, - [DOP_CMPG_DOUBLE] = dalvik_read_instr_cmpg_double, - [DOP_CMP_LONG] = dalvik_read_instr_cmp_long, - [DOP_IF_EQ] = dalvik_read_instr_if_eq, - [DOP_IF_NE] = dalvik_read_instr_if_ne, - [DOP_IF_LT] = dalvik_read_instr_if_lt, - [DOP_IF_GE] = dalvik_read_instr_if_ge, - [DOP_IF_GT] = dalvik_read_instr_if_gt, - [DOP_IF_LE] = dalvik_read_instr_if_le, - [DOP_IF_EQZ] = dalvik_read_instr_if_eqz, - [DOP_IF_NEZ] = dalvik_read_instr_if_nez, - [DOP_IF_LTZ] = dalvik_read_instr_if_ltz, - [DOP_IF_GEZ] = dalvik_read_instr_if_gez, - [DOP_IF_GTZ] = dalvik_read_instr_if_gtz, - [DOP_IF_LEZ] = dalvik_read_instr_if_lez, - [DOP_AGET] = dalvik_read_instr_aget, - [DOP_AGET_WIDE] = dalvik_read_instr_aget_wide, - [DOP_AGET_OBJECT] = dalvik_read_instr_aget_object, - [DOP_AGET_BOOLEAN] = dalvik_read_instr_aget_boolean, - [DOP_AGET_BYTE] = dalvik_read_instr_aget_byte, - [DOP_AGET_CHAR] = dalvik_read_instr_aget_char, - [DOP_AGET_SHORT] = dalvik_read_instr_aget_short, - [DOP_APUT] = dalvik_read_instr_aput, - [DOP_APUT_WIDE] = dalvik_read_instr_aput_wide, - [DOP_APUT_OBJECT] = dalvik_read_instr_aput_object, - [DOP_APUT_BOOLEAN] = dalvik_read_instr_aput_boolean, - [DOP_APUT_BYTE] = dalvik_read_instr_aput_byte, - [DOP_APUT_CHAR] = dalvik_read_instr_aput_char, - [DOP_APUT_SHORT] = dalvik_read_instr_aput_short, - [DOP_IGET] = dalvik_read_instr_iget, - [DOP_IGET_WIDE] = dalvik_read_instr_iget_wide, - [DOP_IGET_OBJECT] = dalvik_read_instr_iget_object, - [DOP_IGET_BOOLEAN] = dalvik_read_instr_iget_boolean, - [DOP_IGET_BYTE] = dalvik_read_instr_iget_byte, - [DOP_IGET_CHAR] = dalvik_read_instr_iget_char, - [DOP_IGET_SHORT] = dalvik_read_instr_iget_short, - [DOP_IPUT] = dalvik_read_instr_iput, - [DOP_IPUT_WIDE] = dalvik_read_instr_iput_wide, - [DOP_IPUT_OBJECT] = dalvik_read_instr_iput_object, - [DOP_IPUT_BOOLEAN] = dalvik_read_instr_iput_boolean, - [DOP_IPUT_BYTE] = dalvik_read_instr_iput_byte, - [DOP_IPUT_CHAR] = dalvik_read_instr_iput_char, - [DOP_IPUT_SHORT] = dalvik_read_instr_iput_short, - [DOP_SGET] = dalvik_read_instr_sget, - [DOP_SGET_WIDE] = dalvik_read_instr_sget_wide, - [DOP_SGET_OBJECT] = dalvik_read_instr_sget_object, - [DOP_SGET_BOOLEAN] = dalvik_read_instr_sget_boolean, - [DOP_SGET_BYTE] = dalvik_read_instr_sget_byte, - [DOP_SGET_CHAR] = dalvik_read_instr_sget_char, - [DOP_SGET_SHORT] = dalvik_read_instr_sget_short, - [DOP_SPUT] = dalvik_read_instr_sput, - [DOP_SPUT_WIDE] = dalvik_read_instr_sput_wide, - [DOP_SPUT_OBJECT] = dalvik_read_instr_sput_object, - [DOP_SPUT_BOOLEAN] = dalvik_read_instr_sput_boolean, - [DOP_SPUT_BYTE] = dalvik_read_instr_sput_byte, - [DOP_SPUT_CHAR] = dalvik_read_instr_sput_char, - [DOP_SPUT_SHORT] = dalvik_read_instr_sput_short, - [DOP_INVOKE_VIRTUAL] = dalvik_read_instr_invoke_virtual, - [DOP_INVOKE_SUPER] = dalvik_read_instr_invoke_super, - [DOP_INVOKE_DIRECT] = dalvik_read_instr_invoke_direct, - [DOP_INVOKE_STATIC] = dalvik_read_instr_invoke_static, - [DOP_INVOKE_INTERFACE] = dalvik_read_instr_invoke_interface, - [DOP_INVOKE_VIRTUAL_RANGE] = dalvik_read_instr_invoke_virtual_range, - [DOP_INVOKE_SUPER_RANGE] = dalvik_read_instr_invoke_super_range, - [DOP_INVOKE_DIRECT_RANGE] = dalvik_read_instr_invoke_direct_range, - [DOP_INVOKE_STATIC_RANGE] = dalvik_read_instr_invoke_static_range, - [DOP_INVOKE_INTERFACE_RANGE]= dalvik_read_instr_invoke_interface_range, - [DOP_NEG_INT] = dalvik_read_instr_neg_int, - [DOP_NOT_INT] = dalvik_read_instr_not_int, - [DOP_NEG_LONG] = dalvik_read_instr_neg_long, - [DOP_NOT_LONG] = dalvik_read_instr_not_long, - [DOP_NEG_FLOAT] = dalvik_read_instr_neg_float, - [DOP_NEG_DOUBLE] = dalvik_read_instr_neg_double, - [DOP_TO_INT_LONG] = dalvik_read_instr_int_to_long, - [DOP_TO_INT_FLOAT] = dalvik_read_instr_int_to_float, - [DOP_TO_INT_DOUBLE] = dalvik_read_instr_int_to_double, - [DOP_TO_LONG_INT] = dalvik_read_instr_long_to_int, - [DOP_TO_LONG_FLOAT] = dalvik_read_instr_long_to_float, - [DOP_TO_LONG_DOUBLE] = dalvik_read_instr_long_to_double, - [DOP_TO_FLOAT_INT] = dalvik_read_instr_float_to_int, - [DOP_TO_FLOAT_LONG] = dalvik_read_instr_float_to_long, - [DOP_TO_FLOAT_DOUBLE] = dalvik_read_instr_float_to_double, - [DOP_TO_DOUBLE_INT] = dalvik_read_instr_double_to_int, - [DOP_TO_DOUBLE_LONG] = dalvik_read_instr_double_to_long, - [DOP_TO_DOUBLE_FLOAT] = dalvik_read_instr_double_to_float, - [DOP_TO_INT_BYTE] = dalvik_read_instr_int_to_byte, - [DOP_TO_INT_CHAR] = dalvik_read_instr_int_to_char, - [DOP_TO_INT_SHORT] = dalvik_read_instr_int_to_short, - [DOP_ADD_INT] = dalvik_read_instr_add_int, - [DOP_SUB_INT] = dalvik_read_instr_sub_int, - [DOP_MUL_INT] = dalvik_read_instr_mul_int, - [DOP_DIV_INT] = dalvik_read_instr_div_int, - [DOP_REM_INT] = dalvik_read_instr_rem_int, - [DOP_AND_INT] = dalvik_read_instr_and_int, - [DOP_OR_INT] = dalvik_read_instr_or_int, - [DOP_XOR_INT] = dalvik_read_instr_xor_int, - [DOP_SHL_INT] = dalvik_read_instr_shl_int, - [DOP_SHR_INT] = dalvik_read_instr_shr_int, - [DOP_USHR_INT] = dalvik_read_instr_ushr_int, - [DOP_ADD_LONG] = dalvik_read_instr_add_long, - [DOP_SUB_LONG] = dalvik_read_instr_sub_long, - [DOP_MUL_LONG] = dalvik_read_instr_mul_long, - [DOP_DIV_LONG] = dalvik_read_instr_div_long, - [DOP_REM_LONG] = dalvik_read_instr_rem_long, - [DOP_AND_LONG] = dalvik_read_instr_and_long, - [DOP_OR_LONG] = dalvik_read_instr_or_long, - [DOP_XOR_LONG] = dalvik_read_instr_xor_long, - [DOP_SHL_LONG] = dalvik_read_instr_shl_long, - [DOP_SHR_LONG] = dalvik_read_instr_shr_long, - [DOP_USHR_LONG] = dalvik_read_instr_ushr_long, - [DOP_ADD_FLOAT] = dalvik_read_instr_add_float, - [DOP_SUB_FLOAT] = dalvik_read_instr_sub_float, - [DOP_MUL_FLOAT] = dalvik_read_instr_mul_float, - [DOP_DIV_FLOAT] = dalvik_read_instr_div_float, - [DOP_REM_FLOAT] = dalvik_read_instr_rem_float, - [DOP_ADD_DOUBLE] = dalvik_read_instr_add_double, - [DOP_SUB_DOUBLE] = dalvik_read_instr_sub_double, - [DOP_MUL_DOUBLE] = dalvik_read_instr_mul_double, - [DOP_DIV_DOUBLE] = dalvik_read_instr_div_double, - [DOP_REM_DOUBLE] = dalvik_read_instr_rem_double, - [DOP_ADD_INT_2ADDR] = dalvik_read_instr_add_int_2addr, - [DOP_SUB_INT_2ADDR] = dalvik_read_instr_sub_int_2addr, - [DOP_MUL_INT_2ADDR] = dalvik_read_instr_mul_int_2addr, - [DOP_DIV_INT_2ADDR] = dalvik_read_instr_div_int_2addr, - [DOP_REM_INT_2ADDR] = dalvik_read_instr_rem_int_2addr, - [DOP_AND_INT_2ADDR] = dalvik_read_instr_and_int_2addr, - [DOP_OR_INT_2ADDR] = dalvik_read_instr_or_int_2addr, - [DOP_XOR_INT_2ADDR] = dalvik_read_instr_xor_int_2addr, - [DOP_SHL_INT_2ADDR] = dalvik_read_instr_shl_int_2addr, - [DOP_SHR_INT_2ADDR] = dalvik_read_instr_shr_int_2addr, - [DOP_USHR_INT_2ADDR] = dalvik_read_instr_ushr_int_2addr, - [DOP_ADD_LONG_2ADDR] = dalvik_read_instr_add_long_2addr, - [DOP_SUB_LONG_2ADDR] = dalvik_read_instr_sub_long_2addr, - [DOP_MUL_LONG_2ADDR] = dalvik_read_instr_mul_long_2addr, - [DOP_DIV_LONG_2ADDR] = dalvik_read_instr_div_long_2addr, - [DOP_REM_LONG_2ADDR] = dalvik_read_instr_rem_long_2addr, - [DOP_AND_LONG_2ADDR] = dalvik_read_instr_and_long_2addr, - [DOP_OR_LONG_2ADDR] = dalvik_read_instr_or_long_2addr, - [DOP_XOR_LONG_2ADDR] = dalvik_read_instr_xor_long_2addr, - [DOP_SHL_LONG_2ADDR] = dalvik_read_instr_shl_long_2addr, - [DOP_SHR_LONG_2ADDR] = dalvik_read_instr_shr_long_2addr, - [DOP_USHR_LONG_2ADDR] = dalvik_read_instr_ushr_long_2addr, - [DOP_ADD_FLOAT_2ADDR] = dalvik_read_instr_add_float_2addr, - [DOP_SUB_FLOAT_2ADDR] = dalvik_read_instr_sub_float_2addr, - [DOP_MUL_FLOAT_2ADDR] = dalvik_read_instr_mul_float_2addr, - [DOP_DIV_FLOAT_2ADDR] = dalvik_read_instr_div_float_2addr, - [DOP_REM_FLOAT_2ADDR] = dalvik_read_instr_rem_float_2addr, - [DOP_ADD_DOUBLE_2ADDR] = dalvik_read_instr_add_double_2addr, - [DOP_SUB_DOUBLE_2ADDR] = dalvik_read_instr_sub_double_2addr, - [DOP_MUL_DOUBLE_2ADDR] = dalvik_read_instr_mul_double_2addr, - [DOP_DIV_DOUBLE_2ADDR] = dalvik_read_instr_div_double_2addr, - [DOP_REM_DOUBLE_2ADDR] = dalvik_read_instr_rem_double_2addr, - [DOP_ADD_INT_LIT16] = dalvik_read_instr_add_int_lit16, - [DOP_RSUB_INT] = dalvik_read_instr_rsub_int, - [DOP_MUL_INT_LIT16] = dalvik_read_instr_mul_int_lit16, - [DOP_DIV_INT_LIT16] = dalvik_read_instr_div_int_lit16, - [DOP_REM_INT_LIT16] = dalvik_read_instr_rem_int_lit16, - [DOP_AND_INT_LIT16] = dalvik_read_instr_and_int_lit16, - [DOP_OR_INT_LIT16] = dalvik_read_instr_or_int_lit16, - [DOP_XOR_INT_LIT16] = dalvik_read_instr_xor_int_lit16, - [DOP_ADD_INT_LIT8] = dalvik_read_instr_add_int_lit8, - [DOP_RSUB_INT_LIT8] = dalvik_read_instr_rsub_int_lit8, - [DOP_MUL_INT_LIT8] = dalvik_read_instr_mul_int_lit8, - [DOP_DIV_INT_LIT8] = dalvik_read_instr_div_int_lit8, - [DOP_REM_INT_LIT8] = dalvik_read_instr_rem_int_lit8, - [DOP_AND_INT_LIT8] = dalvik_read_instr_and_int_lit8, - [DOP_OR_INT_LIT8] = dalvik_read_instr_or_int_lit8, - [DOP_XOR_INT_LIT8] = dalvik_read_instr_xor_int_lit8, - [DOP_SHL_INT_LIT8] = dalvik_read_instr_shl_int_lit8, - [DOP_SHR_INT_LIT8] = dalvik_read_instr_shr_int_lit8, - [DOP_USHR_INT_LIT8] = dalvik_read_instr_ushr_int_lit8 - - }; - - /* Données brutes associées à une instruction ? */ - - result = g_dalvik_context_get_raw_data(ctx, content, pos); - - if (result != NULL) goto gdpd_done; - - /* Pseudo-instruction... */ - - if (!g_binary_content_read_u8(content, pos, &raw8)) - return NULL; - - result = g_dalvik_processor_disassemble_pseudo(proc, ctx, content, pos, raw8); - - if (result != NULL) goto gdpd_done; - - /* ... ou instruction classique */ - - assert(raw8 < DOP_COUNT); - - id = (DalvikOpcodes)raw8; - - if (decodings[id] != NULL) - result = decodings[id](proc, G_PROC_CONTEXT(ctx), content, pos, format); - - gdpd_done: - - return result; - -} - - -/****************************************************************************** -* * * Paramètres : proc = architecture visée par la procédure. * * data = flux de données à analyser. * * pos = position courante dans ce flux. [OUT] * @@ -536,7 +211,7 @@ static GArchInstruction *g_dalvik_processor_disassemble(const GArchProcessor *pr * * ******************************************************************************/ -static GArchInstruction *g_dalvik_processor_disassemble_pseudo(const GArchProcessor *proc, GDalvikContext *ctx, const GBinContent *content, vmpa2t *pos, uint8_t low8) +GArchInstruction *g_dalvik_processor_disassemble_pseudo(const GArchProcessor *proc, GDalvikContext *ctx, const GBinContent *content, vmpa2t *pos, uint8_t low8) { GArchInstruction *result; /* Instruction à renvoyer */ vmpa2t tmp; /* Position modifiable */ diff --git a/plugins/dalvik/processor.h b/plugins/dalvik/processor.h index c6c1278..ffddb2a 100644 --- a/plugins/dalvik/processor.h +++ b/plugins/dalvik/processor.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_PROCESSOR_H -#define _ARCH_DALVIK_PROCESSOR_H +#ifndef _PLUGINS_DALVIK_PROCESSOR_H +#define _PLUGINS_DALVIK_PROCESSOR_H #include <arch/processor.h> @@ -45,9 +45,6 @@ typedef struct _GDalvikProcessorClass GDalvikProcessorClass; /* Indique le type défini par la GLib pour le processeur Dalvik. */ GType g_dalvik_processor_get_type(void); -/* Crée le support de l'architecture Dalvik. */ -GArchProcessor *g_dalvik_processor_new(void); - -#endif /* _ARCH_DALVIK_PROCESSOR_H */ +#endif /* _PLUGINS_DALVIK_PROCESSOR_H */ diff --git a/plugins/dalvik/pseudo/fill.c b/plugins/dalvik/pseudo/fill.c index dc5683c..5c86a80 100644 --- a/plugins/dalvik/pseudo/fill.c +++ b/plugins/dalvik/pseudo/fill.c @@ -28,6 +28,7 @@ #include <string.h> +#include "identifiers.h" #include "../instruction-int.h" @@ -63,6 +64,9 @@ static void g_dalvik_fill_instr_dispose(GDalvikFillInstr *); /* Procède à la libération totale de la mémoire. */ static void g_dalvik_fill_instr_finalize(GDalvikFillInstr *); +/* Fournit le nom humain de l'instruction manipulée. */ +static const char *g_dalvik_fill_instruction_get_keyword(const GDalvikFillInstr *, AsmSyntax); + /* Indique le type défini pour une pseudo-instruction Dalvik de remplissage. */ @@ -84,12 +88,17 @@ G_DEFINE_TYPE(GDalvikFillInstr, g_dalvik_fill_instr, G_TYPE_DALVIK_INSTRUCTION); static void g_dalvik_fill_instr_class_init(GDalvikFillInstrClass *klass) { GObjectClass *object; /* Autre version de la classe */ + GArchInstructionClass *instr; /* Encore une autre vision... */ object = G_OBJECT_CLASS(klass); object->dispose = (GObjectFinalizeFunc/* ! */)g_dalvik_fill_instr_dispose; object->finalize = (GObjectFinalizeFunc)g_dalvik_fill_instr_finalize; + instr = G_ARCH_INSTRUCTION_CLASS(klass); + + instr->get_keyword = (get_instruction_keyword_fc)g_dalvik_fill_instruction_get_keyword; + } @@ -107,7 +116,6 @@ static void g_dalvik_fill_instr_class_init(GDalvikFillInstrClass *klass) static void g_dalvik_fill_instr_init(GDalvikFillInstr *instr) { - G_DALVIK_INSTRUCTION(instr)->keyword = "array-data"; } @@ -174,7 +182,7 @@ GArchInstruction *g_dalvik_fill_instr_new(uint16_t ident, GDalvikContext *ctx, c result = g_object_new(G_TYPE_DALVIK_FILL_INSTR, NULL); - G_DALVIK_INSTRUCTION(result)->ptype = ident; + G_ARCH_INSTRUCTION(result)->uid = DPO_FILL_ARRAY_DATA; if (!g_binary_content_read_u16(content, pos, SRE_LITTLE, &result->item_width)) goto gdfin_bad; @@ -196,3 +204,27 @@ GArchInstruction *g_dalvik_fill_instr_new(uint16_t ident, GDalvikContext *ctx, c return NULL; } + + +/****************************************************************************** +* * +* Paramètres : instr = instruction d'assemblage à consulter. * +* syntax = type de représentation demandée. * +* * +* Description : Fournit le nom humain de l'instruction manipulée. * +* * +* Retour : Mot clef de bas niveau. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static const char *g_dalvik_fill_instruction_get_keyword(const GDalvikFillInstr *instr, AsmSyntax syntax) +{ + const char *result; /* Désignation à retourner */ + + result = "array-data"; + + return result; + +} diff --git a/plugins/dalvik/pseudo/fill.h b/plugins/dalvik/pseudo/fill.h index 2a63df9..a022ed2 100644 --- a/plugins/dalvik/pseudo/fill.h +++ b/plugins/dalvik/pseudo/fill.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_PSEUDO_FILL_H -#define _ARCH_DALVIK_PSEUDO_FILL_H +#ifndef _PLUGINS_DALVIK_PSEUDO_FILL_H +#define _PLUGINS_DALVIK_PSEUDO_FILL_H #include "../context.h" @@ -57,4 +57,4 @@ GArchInstruction *g_dalvik_fill_instr_new(uint16_t, GDalvikContext *, const GBin -#endif /* _ARCH_DALVIK_PSEUDO_FILL_H */ +#endif /* _PLUGINS_DALVIK_PSEUDO_FILL_H */ diff --git a/plugins/dalvik/pseudo/identifiers.h b/plugins/dalvik/pseudo/identifiers.h new file mode 100644 index 0000000..e1ab8fc --- /dev/null +++ b/plugins/dalvik/pseudo/identifiers.h @@ -0,0 +1,39 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * identifiers.h - définition d'identifiants uniques pour Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _PLUGINS_DALVIK_PSEUDO_IDENTIFIERS_H +#define _PLUGINS_DALVIK_PSEUDO_IDENTIFIERS_H + + +/* Enumération de tous les pseudo-opcodes */ +typedef enum _DalvikPseudoOpcodes +{ + DPO_PACKED_SWITCH = 0x0100, /* Switch aux clefs compactes */ + DPO_SPARSE_SWITCH = 0x0200, /* Switch aux clefs éclatées */ + DPO_FILL_ARRAY_DATA = 0x0300 /* Contenu de tableau */ + +} DalvikPseudoOpcodes; + + + +#endif /* _PLUGINS_DALVIK_PSEUDO_IDENTIFIERS_H */ diff --git a/plugins/dalvik/pseudo/switch.c b/plugins/dalvik/pseudo/switch.c index 90cff87..d6d255c 100644 --- a/plugins/dalvik/pseudo/switch.c +++ b/plugins/dalvik/pseudo/switch.c @@ -28,6 +28,7 @@ #include <malloc.h> +#include "identifiers.h" #include "../instruction-int.h" @@ -68,6 +69,9 @@ static void g_dalvik_switch_instr_finalize(GDalvikSwitchInstr *); /* Lit toutes les valeurs associés aux branchements. */ static bool g_dalvik_switch_decode_data(GDalvikSwitchInstr *, const GBinContent *, const vmpa2t *); +/* Fournit le nom humain de l'instruction manipulée. */ +static const char *g_dalvik_switch_instruction_get_keyword(const GDalvikSwitchInstr *, AsmSyntax); + /* Indique le type défini pour une pseudo-instruction Dalvik de remplissage. */ @@ -89,12 +93,17 @@ G_DEFINE_TYPE(GDalvikSwitchInstr, g_dalvik_switch_instr, G_TYPE_DALVIK_INSTRUCTI static void g_dalvik_switch_instr_class_init(GDalvikSwitchInstrClass *klass) { GObjectClass *object; /* Autre version de la classe */ + GArchInstructionClass *instr; /* Encore une autre vision... */ object = G_OBJECT_CLASS(klass); object->dispose = (GObjectFinalizeFunc/* ! */)g_dalvik_switch_instr_dispose; object->finalize = (GObjectFinalizeFunc)g_dalvik_switch_instr_finalize; + instr = G_ARCH_INSTRUCTION_CLASS(klass); + + instr->get_keyword = (get_instruction_keyword_fc)g_dalvik_switch_instruction_get_keyword; + } @@ -112,7 +121,6 @@ static void g_dalvik_switch_instr_class_init(GDalvikSwitchInstrClass *klass) static void g_dalvik_switch_instr_init(GDalvikSwitchInstr *instr) { - G_DALVIK_INSTRUCTION(instr)->keyword = "switch-data"; } @@ -185,7 +193,7 @@ GArchInstruction *g_dalvik_switch_instr_new(uint16_t ident, GDalvikContext *ctx, result = g_object_new(G_TYPE_DALVIK_SWITCH_INSTR, NULL); - G_DALVIK_INSTRUCTION(result)->ptype = ident; + G_ARCH_INSTRUCTION(result)->uid = ident; if (!g_binary_content_read_u16(content, pos, SRE_LITTLE, &result->switch_size)) goto gdsin_bad; @@ -237,7 +245,7 @@ static bool g_dalvik_switch_decode_data(GDalvikSwitchInstr *instr, const GBinCon copy_vmpa(&iter, pos); - if (G_DALVIK_INSTRUCTION(instr)->ptype == DPO_PACKED_SWITCH) + if (G_ARCH_INSTRUCTION(instr)->uid == DPO_PACKED_SWITCH) { if (!g_binary_content_read_s32(content, &iter, SRE_LITTLE, &first_key)) goto gdsdd_bad; @@ -276,6 +284,30 @@ static bool g_dalvik_switch_decode_data(GDalvikSwitchInstr *instr, const GBinCon /****************************************************************************** * * +* Paramètres : instr = instruction d'assemblage à consulter. * +* syntax = type de représentation demandée. * +* * +* Description : Fournit le nom humain de l'instruction manipulée. * +* * +* Retour : Mot clef de bas niveau. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static const char *g_dalvik_switch_instruction_get_keyword(const GDalvikSwitchInstr *instr, AsmSyntax syntax) +{ + const char *result; /* Désignation à retourner */ + + result = "switch-data"; + + return result; + +} + + +/****************************************************************************** +* * * Paramètres : instr = instruction d'assemblage à compléter. * * keys = tableau renseignant les conditions de saut. [OUT] * * targets = tableau renseignant les sauts relatifs. [OUT] * diff --git a/plugins/dalvik/pseudo/switch.h b/plugins/dalvik/pseudo/switch.h index d672f86..b17a9c9 100644 --- a/plugins/dalvik/pseudo/switch.h +++ b/plugins/dalvik/pseudo/switch.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_PSEUDO_SWITCH_H -#define _ARCH_DALVIK_PSEUDO_SWITCH_H +#ifndef _PLUGINS_DALVIK_PSEUDO_SWITCH_H +#define _PLUGINS_DALVIK_PSEUDO_SWITCH_H #include "../context.h" @@ -60,4 +60,4 @@ uint16_t g_dalvik_switch_get_data(GDalvikSwitchInstr *, const int32_t **, const -#endif /* _ARCH_DALVIK_PSEUDO_SWITCH_H */ +#endif /* _PLUGINS_DALVIK_PSEUDO_SWITCH_H */ diff --git a/plugins/dalvik/register.h b/plugins/dalvik/register.h index de5efe5..d678bfd 100644 --- a/plugins/dalvik/register.h +++ b/plugins/dalvik/register.h @@ -21,8 +21,8 @@ */ -#ifndef _ARCH_DALVIK_REGISTERS_H -#define _ARCH_DALVIK_REGISTERS_H +#ifndef _PLUGINS_DALVIK_REGISTERS_H +#define _PLUGINS_DALVIK_REGISTERS_H #include <glib-object.h> @@ -73,4 +73,4 @@ void clean_dalvik_register_cache(void); -#endif /* _ARCH_DALVIK_REGISTERS_H */ +#endif /* _PLUGINS_DALVIK_REGISTERS_H */ diff --git a/plugins/dalvik/v35/Makefile.am b/plugins/dalvik/v35/Makefile.am new file mode 100644 index 0000000..a29d4a5 --- /dev/null +++ b/plugins/dalvik/v35/Makefile.am @@ -0,0 +1,20 @@ + +lib_LTLIBRARIES = libdalvik35.la + +libdalvik35_la_SOURCES = \ + instruction.h instruction.c \ + operand.h \ + processor.h processor.c + +libdalvik35_la_LIBADD = \ + opcodes/libdalvik35opcodes.la + +libdalvik35_la_CFLAGS = $(AM_CFLAGS) + + +AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBPYTHON_CFLAGS) $(LIBPYGOBJECT_CFLAGS) $(LIBXML_CFLAGS) -I$(top_srcdir)/src + +AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) + + +SUBDIRS = opdefs opcodes diff --git a/plugins/dalvik/v35/instruction.c b/plugins/dalvik/v35/instruction.c new file mode 100644 index 0000000..99d51d0 --- /dev/null +++ b/plugins/dalvik/v35/instruction.c @@ -0,0 +1,267 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * instruction.c - gestion des instructions de la VM Dalvik v35 + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "instruction.h" + + +#include <assert.h> + + +#include "opcodes/descriptions.h" +#include "opcodes/keywords.h" +#include "../instruction-int.h" + + + +/* Définition générique d'une instruction d'architecture Dalvik v35 (instance) */ +struct _GDalvik35Instruction +{ + GDalvikInstruction parent; /* A laisser en premier */ + +}; + +/* Définition générique d'une instruction d'architecture Dalvik v35 (classe) */ +struct _GDalvik35InstructionClass +{ + GDalvikInstructionClass parent; /* A laisser en premier */ + +}; + + +/* Initialise la classe des instructions pour Dalvik v35. */ +static void g_dalvik35_instruction_class_init(GDalvik35InstructionClass *); + +/* Initialise une instance d'opérande d'architecture Dalvik. */ +static void g_dalvik35_instruction_init(GDalvik35Instruction *); + +/* Supprime toutes les références externes. */ +static void g_dalvik35_instruction_dispose(GDalvik35Instruction *); + +/* Procède à la libération totale de la mémoire. */ +static void g_dalvik35_instruction_finalize(GDalvik35Instruction *); + +/* Indique l'encodage d'une instruction de façon détaillée. */ +static const char *g_dalvik35_instruction_get_encoding(const GDalvik35Instruction *); + +/* Fournit le nom humain de l'instruction manipulée. */ +static const char *g_dalvik35_instruction_get_keyword(const GDalvik35Instruction *, AsmSyntax); + +/* Fournit une description pour l'instruction manipulée. */ +static const char *g_dalvik35_instruction_get_description(const GDalvik35Instruction *); + + + +/* Indique le type défini pour une instruction d'architecture Dalvik v35. */ +G_DEFINE_TYPE(GDalvik35Instruction, g_dalvik35_instruction, G_TYPE_DALVIK_INSTRUCTION); + + +/****************************************************************************** +* * +* Paramètres : klass = classe à initialiser. * +* * +* Description : Initialise la classe des instructions pour Dalvik v35. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_instruction_class_init(GDalvik35InstructionClass *klass) +{ + GObjectClass *object; /* Autre version de la classe */ + GArchInstructionClass *instr; /* Encore une autre vision... */ + + object = G_OBJECT_CLASS(klass); + + object->dispose = (GObjectFinalizeFunc/* ! */)g_dalvik35_instruction_dispose; + object->finalize = (GObjectFinalizeFunc)g_dalvik35_instruction_finalize; + + instr = G_ARCH_INSTRUCTION_CLASS(klass); + + instr->get_encoding = (get_instruction_encoding_fc)g_dalvik35_instruction_get_encoding; + instr->get_keyword = (get_instruction_keyword_fc)g_dalvik35_instruction_get_keyword; + instr->get_desc = (get_instruction_desc_fc)g_dalvik35_instruction_get_description; + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instance à initialiser. * +* * +* Description : Initialise une instance d'instruction d'architecture Dalvik. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_instruction_init(GDalvik35Instruction *instr) +{ + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instance d'objet GLib à traiter. * +* * +* Description : Supprime toutes les références externes. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_instruction_dispose(GDalvik35Instruction *instr) +{ + G_OBJECT_CLASS(g_dalvik35_instruction_parent_class)->dispose(G_OBJECT(instr)); + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instance d'objet GLib à traiter. * +* * +* Description : Procède à la libération totale de la mémoire. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_instruction_finalize(GDalvik35Instruction *instr) +{ + G_OBJECT_CLASS(g_dalvik35_instruction_parent_class)->finalize(G_OBJECT(instr)); + +} + + +/****************************************************************************** +* * +* Paramètres : keyword = définition du nom humaine de l'instruction. * +* * +* Description : Crée une instruction pour l'architecture Dalvik v35. * +* * +* Retour : Adresse de la structure mise en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArchInstruction *g_dalvik35_instruction_new(itid_t uid) +{ + GArchInstruction *result; /* Structure à retourner */ + + result = g_object_new(G_TYPE_DALVIK35_INSTRUCTION, NULL); + + G_ARCH_INSTRUCTION(result)->uid = uid; + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instruction quelconque à consulter. * +* * +* Description : Indique l'encodage d'une instruction de façon détaillée. * +* * +* Retour : Description humaine de l'encodage utilisé. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static const char *g_dalvik35_instruction_get_encoding(const GDalvik35Instruction *instr) +{ + const char *result; /* Description à retourner */ + + result = "Dalvik v35"; + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instruction d'assemblage à consulter. * +* syntax = type de représentation demandée. * +* * +* Description : Fournit le nom humain de l'instruction manipulée. * +* * +* Retour : Mot clef de bas niveau. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static const char *g_dalvik35_instruction_get_keyword(const GDalvik35Instruction *instr, AsmSyntax syntax) +{ + const char *result; /* Désignation à retourner */ + itid_t uid; /* Accès simplifié */ + + uid = G_ARCH_INSTRUCTION(instr)->uid; + + assert(uid < DOP35_COUNT); + + result = _dalvik35_keywords[uid]; + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : instr = instruction d'assemblage à consulter. * +* * +* Description : Fournit une description pour l'instruction manipulée. * +* * +* Retour : Chaîne de caractères avec balises éventuelles. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static const char *g_dalvik35_instruction_get_description(const GDalvik35Instruction *instr) +{ + const char *result; /* Description à retourner */ + itid_t uid; /* Accès simplifié */ + + uid = G_ARCH_INSTRUCTION(instr)->uid; + + assert(uid < DOP35_COUNT); + + result = _dalvik35_descriptions[uid]; + + return result; + +} diff --git a/plugins/dalvik/v35/instruction.h b/plugins/dalvik/v35/instruction.h new file mode 100644 index 0000000..152c224 --- /dev/null +++ b/plugins/dalvik/v35/instruction.h @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * instruction.h - prototypes pour la gestion des instructions de la VM Dalvik v35 + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _PLUGINS_DALVIK_V35_INSTRUCTION_H +#define _PLUGINS_DALVIK_V35_INSTRUCTION_H + + +#include <arch/instruction.h> + + + +#define G_TYPE_DALVIK35_INSTRUCTION g_dalvik35_instruction_get_type() +#define G_DALVIK35_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), G_TYPE_DALVIK35_INSTRUCTION, GDalvik35Instruction)) +#define G_IS_DALVIK35_INSTRUCTION(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), G_TYPE_DALVIK35_INSTRUCTION)) +#define G_DALVIK35_INSTRUCTION_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_DALVIK35_INSTRUCTION, GDalvik35InstructionClass)) +#define G_IS_DALVIK35_INSTRUCTION_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_DALVIK35_INSTRUCTION)) +#define G_DALVIK35_INSTRUCTION_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_DALVIK35_INSTRUCTION, GDalvik35InstructionClass)) + + +/* Définition générique d'une instruction d'architecture Dalvik v35 (instance) */ +typedef struct _GDalvik35Instruction GDalvik35Instruction; + +/* Définition générique d'une instruction d'architecture Dalvik v35 (classe) */ +typedef struct _GDalvik35InstructionClass GDalvik35InstructionClass; + + +/* Indique le type défini pour une instruction d'architecture Dalvik v35. */ +GType g_dalvik35_instruction_get_type(void); + +/* Crée une instruction pour l'architecture Dalvik v35. */ +GArchInstruction *g_dalvik35_instruction_new(itid_t); + + + +#endif /* _PLUGINS_DALVIK_V35_INSTRUCTION_H */ diff --git a/plugins/dalvik/opcodes/Makefile.am b/plugins/dalvik/v35/opcodes/Makefile.am index 9889cfa..4746f5c 100644 --- a/plugins/dalvik/opcodes/Makefile.am +++ b/plugins/dalvik/v35/opcodes/Makefile.am @@ -9,15 +9,18 @@ am__depfiles_maybe = depfiles include gencode.mk -noinst_LTLIBRARIES = libdalvikopcodes.la +noinst_LTLIBRARIES = libdalvik35opcodes.la -libdalvikopcodes_la_SOURCES = $(GENERATED_FILES) +libdalvik35opcodes_la_SOURCES = $(GENERATED_FILES) -libdalvikopcodes_la_LIBADD = +libdalvik35opcodes_la_LIBADD = -libdalvikopcodes_la_CFLAGS = $(AM_CFLAGS) +libdalvik35opcodes_la_CFLAGS = $(AM_CFLAGS) AM_CPPFLAGS = $(LIBGTK_CFLAGS) $(LIBXML_CFLAGS) -I$(top_srcdir)/src AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) $(COMPLIANCE_FLAGS) + + +CLEANFILES = $(GENERATED_FILES) diff --git a/plugins/dalvik/opdefs/Makefile.am b/plugins/dalvik/v35/opdefs/Makefile.am index fed398f..f660e3d 100644 --- a/plugins/dalvik/opdefs/Makefile.am +++ b/plugins/dalvik/v35/opdefs/Makefile.am @@ -5,44 +5,44 @@ include $(top_srcdir)/tools/d2c/d2c.mk D2C_BIN = $(top_srcdir)/tools/d2c/d2c GEN_BIN = $(top_srcdir)/tools/d2c/d2c_genmakefile.sh -D2C_TYPE = format -D2C_OUTDIR = $(PWD)/.. +D2C_OUTDIR = $(PWD)/../opcodes/ + +D2C_TYPE = format -D2C_ARCH = dalvik -D2C_HEADER = _ARCH_DALVIK -D2C_PREFIX = DALVIK_OPT_ +D2C_ARCH = "Dalvik v35" +D2C_ARCH_CN = Dalvik35 +D2C_GUARD = PLUGINS_DALVIK_V35_OPCODES D2C_ENCODINGS = \ -e none -D2C_MACROS = \ - -M SetInsFlag=g_arch_instruction_set_flag +D2C_ID_PREFIX = DOP35 +D2C_ID_COUNT = 255 + +D2C_SPECIFIC = --op-prefix=DALVIK_OPT_ -FIXED_C_INCLUDES = \ - \n\#include \<stdint.h\> \ - \n \ - \n\#include <analysis\/content.h> \ - \n\#include <arch/context.h> \ - \n\#include <format\/executable.h> \ - \n \ - \n\#include \"..\/fetch.h\" \ - \n\#include \"..\/helpers.h\" \ - \n\#include \"..\/instruction.h\" \ - \n\#include \"..\/link.h\" \ - \n\#include \"..\/post.h\" \ - \n\#include \"..\/processor.h\" \ - \n\n -FIXED_H_INCLUDES = \ - \#include <stdint.h> \ - \n \ - \n\#include <arch/context.h> \ - \n\#include <analysis/content.h> \ - \n\#include <format/executable.h> \ - \n \ +FIXED_C_INCLUDES = \ + \#include <stdint.h> \ + \n \ + \n\#include "../instruction.h" \ + \n\#include "../operand.h" \ + \n\#include "../../fetch.h" \ + \n\#include "../../helpers.h" \ + \n\#include "../../link.h" \ + \n\#include "../../post.h" + +FIXED_H_INCLUDES = \ + \#include <stdint.h> \ + \n \ + \n\#include <analysis/content.h> \ + \n\#include <arch/context.h> \ + \n\#include <format/executable.h> \ + \n \ \n\#include "../processor.h" + # for (( i = 0; i < 256; i++)); do def=$(ls `printf "*_%02x.d" $i` 2> /dev/null); test -z "$def" || echo -e "\t$def\t\t\t\t\t\t\t\\" ; done DALVIK_DEFS = \ nop_00.d \ @@ -107,6 +107,12 @@ DALVIK_DEFS = \ if_3b.d \ if_3c.d \ if_3d.d \ + unused_3e.d \ + unused_3f.d \ + unused_40.d \ + unused_41.d \ + unused_42.d \ + unused_43.d \ aget_44.d \ aget_45.d \ aget_46.d \ @@ -154,11 +160,14 @@ DALVIK_DEFS = \ invoke_70.d \ invoke_71.d \ invoke_72.d \ + unused_73.d \ invoke_74.d \ invoke_75.d \ invoke_76.d \ invoke_77.d \ invoke_78.d \ + unused_79.d \ + unused_7a.d \ neg_7b.d \ not_7c.d \ neg_7d.d \ @@ -262,7 +271,37 @@ DALVIK_DEFS = \ xor_df.d \ shl_e0.d \ shr_e1.d \ - ushr_e2.d + ushr_e2.d \ + unused_e3.d \ + unused_e4.d \ + unused_e5.d \ + unused_e6.d \ + unused_e7.d \ + unused_e8.d \ + unused_e9.d \ + unused_ea.d \ + unused_eb.d \ + unused_ec.d \ + unused_ed.d \ + unused_ee.d \ + unused_ef.d \ + unused_f0.d \ + unused_f1.d \ + unused_f2.d \ + unused_f3.d \ + unused_f4.d \ + unused_f5.d \ + unused_f6.d \ + unused_f7.d \ + unused_f8.d \ + unused_f9.d \ + unused_fa.d \ + unused_fb.d \ + unused_fc.d \ + unused_fd.d \ + unused_fe.d \ + unused_ff.d + # make dist procède répertoire par répertoire. Or le répertoire opcodes utilise # le contenu du répertoire opdefs. Il faut donc générer les fichiers nécessaires @@ -279,7 +318,7 @@ dist-hook: all: $(DALVIK_DEFS:.d=.g) fmk.done d2c_final_rules fmk.done: $(DALVIK_DEFS) - $(GEN_BIN) ../opcodes/ ../opdefs/.gen $(top_srcdir)/tools/d2c/globalgen.mk - + $(GEN_BIN) $(D2C_OUTDIR) - touch $@ clean: diff --git a/plugins/dalvik/v35/opdefs/add_90.d b/plugins/dalvik/v35/opdefs/add_90.d new file mode 100644 index 0000000..a4eae0d --- /dev/null +++ b/plugins/dalvik/v35/opdefs/add_90.d @@ -0,0 +1,40 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title add-int + +@id 144 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + +@encoding() { + + @format 23x + +} diff --git a/plugins/dalvik/v35/opdefs/add_9b.d b/plugins/dalvik/v35/opdefs/add_9b.d new file mode 100644 index 0000000..c26a453 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/add_9b.d @@ -0,0 +1,40 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title add-long + +@id 155 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + +@encoding() { + + @format 23x + +} diff --git a/plugins/dalvik/v35/opdefs/add_a6.d b/plugins/dalvik/v35/opdefs/add_a6.d new file mode 100644 index 0000000..16b95f1 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/add_a6.d @@ -0,0 +1,40 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title add-float + +@id 166 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + +@encoding() { + + @format 23x + +} diff --git a/plugins/dalvik/v35/opdefs/add_ab.d b/plugins/dalvik/v35/opdefs/add_ab.d new file mode 100644 index 0000000..20670ad --- /dev/null +++ b/plugins/dalvik/v35/opdefs/add_ab.d @@ -0,0 +1,40 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title add-double + +@id 171 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + +@encoding() { + + @format 23x + +} diff --git a/plugins/dalvik/opdefs/add_b0.d b/plugins/dalvik/v35/opdefs/add_b0.d index 9c5605e..11a415e 100644 --- a/plugins/dalvik/opdefs/add_b0.d +++ b/plugins/dalvik/v35/opdefs/add_b0.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title add-int/2addr +@id 176 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/add_bb.d b/plugins/dalvik/v35/opdefs/add_bb.d index aba27f3..05f471d 100644 --- a/plugins/dalvik/opdefs/add_bb.d +++ b/plugins/dalvik/v35/opdefs/add_bb.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title add-long/2addr +@id 187 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/add_c6.d b/plugins/dalvik/v35/opdefs/add_c6.d index 3394b92..46a5025 100644 --- a/plugins/dalvik/opdefs/add_c6.d +++ b/plugins/dalvik/v35/opdefs/add_c6.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title add-float/2addr +@id 198 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/add_cb.d b/plugins/dalvik/v35/opdefs/add_cb.d index 896f614..4b12d63 100644 --- a/plugins/dalvik/opdefs/add_cb.d +++ b/plugins/dalvik/v35/opdefs/add_cb.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title add-double/2addr +@id 203 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/add_d0.d b/plugins/dalvik/v35/opdefs/add_d0.d index f6f4324..383d25c 100644 --- a/plugins/dalvik/opdefs/add_d0.d +++ b/plugins/dalvik/v35/opdefs/add_d0.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title add-int/lit16 +@id 208 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/add_d8.d b/plugins/dalvik/v35/opdefs/add_d8.d index ec4ee01..e88a5c9 100644 --- a/plugins/dalvik/opdefs/add_d8.d +++ b/plugins/dalvik/v35/opdefs/add_d8.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title add-int/lit8 +@id 216 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/aget_44.d b/plugins/dalvik/v35/opdefs/aget_44.d index b3a26cb..6931af6 100644 --- a/plugins/dalvik/opdefs/aget_44.d +++ b/plugins/dalvik/v35/opdefs/aget_44.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget +@id 68 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aget_45.d b/plugins/dalvik/v35/opdefs/aget_45.d index 184667b..9268f6f 100644 --- a/plugins/dalvik/opdefs/aget_45.d +++ b/plugins/dalvik/v35/opdefs/aget_45.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget-wide +@id 69 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aget_46.d b/plugins/dalvik/v35/opdefs/aget_46.d index b951c09..0d2185e 100644 --- a/plugins/dalvik/opdefs/aget_46.d +++ b/plugins/dalvik/v35/opdefs/aget_46.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget-object +@id 70 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aget_47.d b/plugins/dalvik/v35/opdefs/aget_47.d index 0a5e90b..5b75c11 100644 --- a/plugins/dalvik/opdefs/aget_47.d +++ b/plugins/dalvik/v35/opdefs/aget_47.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget-boolean +@id 71 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aget_48.d b/plugins/dalvik/v35/opdefs/aget_48.d index c84f513..8765831 100644 --- a/plugins/dalvik/opdefs/aget_48.d +++ b/plugins/dalvik/v35/opdefs/aget_48.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget-byte +@id 72 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aget_49.d b/plugins/dalvik/v35/opdefs/aget_49.d index 396434b..24e0fa9 100644 --- a/plugins/dalvik/opdefs/aget_49.d +++ b/plugins/dalvik/v35/opdefs/aget_49.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget-char +@id 73 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aget_4a.d b/plugins/dalvik/v35/opdefs/aget_4a.d index ce9497f..841ec31 100644 --- a/plugins/dalvik/opdefs/aget_4a.d +++ b/plugins/dalvik/v35/opdefs/aget_4a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aget-short +@id 74 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/and_95.d b/plugins/dalvik/v35/opdefs/and_95.d index 3926c05..a75999d 100644 --- a/plugins/dalvik/opdefs/and_95.d +++ b/plugins/dalvik/v35/opdefs/and_95.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title and-int +@id 149 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/and_a0.d b/plugins/dalvik/v35/opdefs/and_a0.d index b011156..488233e 100644 --- a/plugins/dalvik/opdefs/and_a0.d +++ b/plugins/dalvik/v35/opdefs/and_a0.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title and-long +@id 160 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/and_b5.d b/plugins/dalvik/v35/opdefs/and_b5.d index dec2ffb..34547da 100644 --- a/plugins/dalvik/opdefs/and_b5.d +++ b/plugins/dalvik/v35/opdefs/and_b5.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title and-int/2addr +@id 181 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/and_c0.d b/plugins/dalvik/v35/opdefs/and_c0.d index 6fb52b6..17bf2c6 100644 --- a/plugins/dalvik/opdefs/and_c0.d +++ b/plugins/dalvik/v35/opdefs/and_c0.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title and-long/2addr +@id 192 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/and_d5.d b/plugins/dalvik/v35/opdefs/and_d5.d index 081c0d0..84c88c8 100644 --- a/plugins/dalvik/opdefs/and_d5.d +++ b/plugins/dalvik/v35/opdefs/and_d5.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title and-int/lit16 +@id 213 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/and_dd.d b/plugins/dalvik/v35/opdefs/and_dd.d index 8adae05..0296b07 100644 --- a/plugins/dalvik/opdefs/and_dd.d +++ b/plugins/dalvik/v35/opdefs/and_dd.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title and-int/lit8 +@id 221 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/aput_4b.d b/plugins/dalvik/v35/opdefs/aput_4b.d index 90cc75f..dc6a820 100644 --- a/plugins/dalvik/opdefs/aput_4b.d +++ b/plugins/dalvik/v35/opdefs/aput_4b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput +@id 75 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aput_4c.d b/plugins/dalvik/v35/opdefs/aput_4c.d index ff545f4..83c38ac 100644 --- a/plugins/dalvik/opdefs/aput_4c.d +++ b/plugins/dalvik/v35/opdefs/aput_4c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput-wide +@id 76 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aput_4d.d b/plugins/dalvik/v35/opdefs/aput_4d.d index 4c9ae98..8c1a9d1 100644 --- a/plugins/dalvik/opdefs/aput_4d.d +++ b/plugins/dalvik/v35/opdefs/aput_4d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput-object +@id 77 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aput_4e.d b/plugins/dalvik/v35/opdefs/aput_4e.d index 1602e62..5c7c923 100644 --- a/plugins/dalvik/opdefs/aput_4e.d +++ b/plugins/dalvik/v35/opdefs/aput_4e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput-boolean +@id 78 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aput_4f.d b/plugins/dalvik/v35/opdefs/aput_4f.d index 3632974..29a4c70 100644 --- a/plugins/dalvik/opdefs/aput_4f.d +++ b/plugins/dalvik/v35/opdefs/aput_4f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput-byte +@id 79 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aput_50.d b/plugins/dalvik/v35/opdefs/aput_50.d index c295386..2c093ec 100644 --- a/plugins/dalvik/opdefs/aput_50.d +++ b/plugins/dalvik/v35/opdefs/aput_50.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput-char +@id 80 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/aput_51.d b/plugins/dalvik/v35/opdefs/aput_51.d index 11ad5b2..aeb9dd6 100644 --- a/plugins/dalvik/opdefs/aput_51.d +++ b/plugins/dalvik/v35/opdefs/aput_51.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title aput-short +@id 81 + +@desc { + + Perform the identified array operation at the identified index of the given array, loading or storing into the value register. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/array_21.d b/plugins/dalvik/v35/opdefs/array_21.d index e0ca860..56f5c4f 100644 --- a/plugins/dalvik/opdefs/array_21.d +++ b/plugins/dalvik/v35/opdefs/array_21.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title array-length +@id 33 + +@desc { + + Store in the given destination register the length of the indicated array, in entries + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/array_24.d b/plugins/dalvik/v35/opdefs/array_24.d index 00b7896..5c5be4f 100644 --- a/plugins/dalvik/opdefs/array_24.d +++ b/plugins/dalvik/v35/opdefs/array_24.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title filled-new-array +@id 36 + +@desc { + + Construct an array of the given type and size, filling it with the supplied contents. The type must be an array type. The array's contents must be single-word (that is, no arrays of <b>long</b> or <b>double</b>, but reference types are acceptable). The constructed instance is stored as a "result" in the same way that the method invocation instructions store their results, so the constructed instance must be moved to a register with an immediately subsequent <b>move-result-object</b> instruction (if it is to be used). + +} + @encoding() { @format 35c | pool_type diff --git a/plugins/dalvik/opdefs/array_26.d b/plugins/dalvik/v35/opdefs/array_26.d index f57afd1..adceb24 100644 --- a/plugins/dalvik/opdefs/array_26.d +++ b/plugins/dalvik/v35/opdefs/array_26.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title fill-array-data +@id 38 + +@desc { + + Fill the given array with the indicated data. The reference must be to an array of primitives, and the data table must match it in type and must contain no more elements than will fit in the array. That is, the array may be larger than the table, and if so, only the initial elements of the array are set, leaving the remainder alone. + +} + @encoding() { @format 31t diff --git a/plugins/dalvik/opdefs/check_1f.d b/plugins/dalvik/v35/opdefs/check_1f.d index 0f59ba7..4be9fef 100644 --- a/plugins/dalvik/opdefs/check_1f.d +++ b/plugins/dalvik/v35/opdefs/check_1f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title check-cast +@id 31 + +@desc { + + Throw a <b>ClassCastException</b> if the reference in the given register cannot be cast to the indicated type. + +<b>Note:</b> Since <b>A</b> must always be a reference (and not a primitive value), this will necessarily fail at runtime (that is, it will throw an exception) if <b>B</b> refers to a primitive type. + +} + @encoding() { @format 21c | pool_type diff --git a/plugins/dalvik/opdefs/cmp_31.d b/plugins/dalvik/v35/opdefs/cmp_31.d index baedee6..aeea00a 100644 --- a/plugins/dalvik/opdefs/cmp_31.d +++ b/plugins/dalvik/v35/opdefs/cmp_31.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title cmp-long +@id 49 + +@desc { + + Perform the indicated floating point or <b>long</b> comparison, setting <b>a</b> to <b>0</b> if <b>b == c</b>, <b>1</b> if <b>b > c</b>, or <b>-1</b> if <b>b < c</b>. The "bias" listed for the floating point operations indicates how <b>NaN</b> comparisons are treated: "gt bias" instructions return <b>1</b> for <b>NaN</b> comparisons, and "lt bias" instructions return <b>-1</b>. + +For example, to check to see if floating point <b>x < y</b> it is advisable to use <b>cmpg-float</b>; a result of <b>-1</b> indicates that the test was true, and the other values indicate it was false either due to a valid comparison or because one of the values was <b>NaN</b>. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/cmpg_2e.d b/plugins/dalvik/v35/opdefs/cmpg_2e.d index 296337c..c06be47 100644 --- a/plugins/dalvik/opdefs/cmpg_2e.d +++ b/plugins/dalvik/v35/opdefs/cmpg_2e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title cmpg-float +@id 46 + +@desc { + + Perform the indicated floating point or <b>long</b> comparison, setting <b>a</b> to <b>0</b> if <b>b == c</b>, <b>1</b> if <b>b > c</b>, or <b>-1</b> if <b>b < c</b>. The "bias" listed for the floating point operations indicates how <b>NaN</b> comparisons are treated: "gt bias" instructions return <b>1</b> for <b>NaN</b> comparisons, and "lt bias" instructions return <b>-1</b>. + +For example, to check to see if floating point <b>x < y</b> it is advisable to use <b>cmpg-float</b>; a result of <b>-1</b> indicates that the test was true, and the other values indicate it was false either due to a valid comparison or because one of the values was <b>NaN</b>. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/cmpg_30.d b/plugins/dalvik/v35/opdefs/cmpg_30.d index dbb66ae..40917d4 100644 --- a/plugins/dalvik/opdefs/cmpg_30.d +++ b/plugins/dalvik/v35/opdefs/cmpg_30.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title cmpg-double +@id 48 + +@desc { + + Perform the indicated floating point or <b>long</b> comparison, setting <b>a</b> to <b>0</b> if <b>b == c</b>, <b>1</b> if <b>b > c</b>, or <b>-1</b> if <b>b < c</b>. The "bias" listed for the floating point operations indicates how <b>NaN</b> comparisons are treated: "gt bias" instructions return <b>1</b> for <b>NaN</b> comparisons, and "lt bias" instructions return <b>-1</b>. + +For example, to check to see if floating point <b>x < y</b> it is advisable to use <b>cmpg-float</b>; a result of <b>-1</b> indicates that the test was true, and the other values indicate it was false either due to a valid comparison or because one of the values was <b>NaN</b>. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/cmpl_2d.d b/plugins/dalvik/v35/opdefs/cmpl_2d.d index b76b73e..9b9e883 100644 --- a/plugins/dalvik/opdefs/cmpl_2d.d +++ b/plugins/dalvik/v35/opdefs/cmpl_2d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title cmpl-float +@id 45 + +@desc { + + Perform the indicated floating point or <b>long</b> comparison, setting <b>a</b> to <b>0</b> if <b>b == c</b>, <b>1</b> if <b>b > c</b>, or <b>-1</b> if <b>b < c</b>. The "bias" listed for the floating point operations indicates how <b>NaN</b> comparisons are treated: "gt bias" instructions return <b>1</b> for <b>NaN</b> comparisons, and "lt bias" instructions return <b>-1</b>. + +For example, to check to see if floating point <b>x < y</b> it is advisable to use <b>cmpg-float</b>; a result of <b>-1</b> indicates that the test was true, and the other values indicate it was false either due to a valid comparison or because one of the values was <b>NaN</b>. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/cmpl_2f.d b/plugins/dalvik/v35/opdefs/cmpl_2f.d index cebd732..4429977 100644 --- a/plugins/dalvik/opdefs/cmpl_2f.d +++ b/plugins/dalvik/v35/opdefs/cmpl_2f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title cmpl-double +@id 47 + +@desc { + + Perform the indicated floating point or <b>long</b> comparison, setting <b>a</b> to <b>0</b> if <b>b == c</b>, <b>1</b> if <b>b > c</b>, or <b>-1</b> if <b>b < c</b>. The "bias" listed for the floating point operations indicates how <b>NaN</b> comparisons are treated: "gt bias" instructions return <b>1</b> for <b>NaN</b> comparisons, and "lt bias" instructions return <b>-1</b>. + +For example, to check to see if floating point <b>x < y</b> it is advisable to use <b>cmpg-float</b>; a result of <b>-1</b> indicates that the test was true, and the other values indicate it was false either due to a valid comparison or because one of the values was <b>NaN</b>. + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/const_12.d b/plugins/dalvik/v35/opdefs/const_12.d index bc4e4f8..963738a 100644 --- a/plugins/dalvik/opdefs/const_12.d +++ b/plugins/dalvik/v35/opdefs/const_12.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const/4 +@id 18 + +@desc { + + Move the given literal value (sign-extended to 32 bits) into the specified register. + +} + @encoding() { @format 11n diff --git a/plugins/dalvik/opdefs/const_13.d b/plugins/dalvik/v35/opdefs/const_13.d index 9b65ba4..32c09df 100644 --- a/plugins/dalvik/opdefs/const_13.d +++ b/plugins/dalvik/v35/opdefs/const_13.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const/16 +@id 19 + +@desc { + + Move the given literal value (sign-extended to 32 bits) into the specified register. + +} + @encoding() { @format 21s diff --git a/plugins/dalvik/opdefs/const_14.d b/plugins/dalvik/v35/opdefs/const_14.d index 039d372..402a889 100644 --- a/plugins/dalvik/opdefs/const_14.d +++ b/plugins/dalvik/v35/opdefs/const_14.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const +@id 20 + +@desc { + + Move the given literal value into the specified register. + +} + @encoding() { @format 31i diff --git a/plugins/dalvik/opdefs/const_15.d b/plugins/dalvik/v35/opdefs/const_15.d index add0673..a9d6f98 100644 --- a/plugins/dalvik/opdefs/const_15.d +++ b/plugins/dalvik/v35/opdefs/const_15.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const/high16 +@id 21 + +@desc { + + Move the given literal value (right-zero-extended to 32 bits) into the specified register. + +} + @encoding() { @format 21h diff --git a/plugins/dalvik/opdefs/const_16.d b/plugins/dalvik/v35/opdefs/const_16.d index cb1ce25..3dcc25a 100644 --- a/plugins/dalvik/opdefs/const_16.d +++ b/plugins/dalvik/v35/opdefs/const_16.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-wide/16 +@id 22 + +@desc { + + Move the given literal value (sign-extended to 64 bits) into the specified register-pair. + +} + @encoding() { @format 21s diff --git a/plugins/dalvik/opdefs/const_17.d b/plugins/dalvik/v35/opdefs/const_17.d index 88a9f0c..093f6d6 100644 --- a/plugins/dalvik/opdefs/const_17.d +++ b/plugins/dalvik/v35/opdefs/const_17.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-wide/32 +@id 23 + +@desc { + + Move the given literal value (sign-extended to 64 bits) into the specified register-pair. + +} + @encoding() { @format 31i diff --git a/plugins/dalvik/opdefs/const_18.d b/plugins/dalvik/v35/opdefs/const_18.d index d792add..b77fad9 100644 --- a/plugins/dalvik/opdefs/const_18.d +++ b/plugins/dalvik/v35/opdefs/const_18.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-wide +@id 24 + +@desc { + + Move the given literal value into the specified register-pair. + +} + @encoding() { @format 51l diff --git a/plugins/dalvik/opdefs/const_19.d b/plugins/dalvik/v35/opdefs/const_19.d index 577eaf3..731797c 100644 --- a/plugins/dalvik/opdefs/const_19.d +++ b/plugins/dalvik/v35/opdefs/const_19.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-wide/high16 +@id 25 + +@desc { + + Move the given literal value (right-zero-extended to 64 bits) into the specified register-pair. + +} + @encoding() { @format 21h diff --git a/plugins/dalvik/opdefs/const_1a.d b/plugins/dalvik/v35/opdefs/const_1a.d index 22c11ae..a019a08 100644 --- a/plugins/dalvik/opdefs/const_1a.d +++ b/plugins/dalvik/v35/opdefs/const_1a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-string +@id 26 + +@desc { + + Move a reference to the string specified by the given index into the specified register. + +} + @encoding() { @format 21c | pool_string diff --git a/plugins/dalvik/opdefs/const_1b.d b/plugins/dalvik/v35/opdefs/const_1b.d index 699cef6..65323bc 100644 --- a/plugins/dalvik/opdefs/const_1b.d +++ b/plugins/dalvik/v35/opdefs/const_1b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-string/jumbo +@id 27 + +@desc { + + Move a reference to the string specified by the given index into the specified register. + +} + @encoding() { @format 31c | pool_string diff --git a/plugins/dalvik/opdefs/const_1c.d b/plugins/dalvik/v35/opdefs/const_1c.d index c539ee9..ff7d1ae 100644 --- a/plugins/dalvik/opdefs/const_1c.d +++ b/plugins/dalvik/v35/opdefs/const_1c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title const-class +@id 28 + +@desc { + + Move a reference to the class specified by the given index into the specified register. In the case where the indicated type is primitive, this will store a reference to the primitive type's degenerate class. + +} + @encoding() { @format 21c | pool_type diff --git a/plugins/dalvik/opdefs/div_93.d b/plugins/dalvik/v35/opdefs/div_93.d index cfb7f34..096a084 100644 --- a/plugins/dalvik/opdefs/div_93.d +++ b/plugins/dalvik/v35/opdefs/div_93.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-int +@id 147 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/div_9e.d b/plugins/dalvik/v35/opdefs/div_9e.d index b12ebd1..cbe850a 100644 --- a/plugins/dalvik/opdefs/div_9e.d +++ b/plugins/dalvik/v35/opdefs/div_9e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-long +@id 158 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/div_a9.d b/plugins/dalvik/v35/opdefs/div_a9.d index f7ce52e..728eec5 100644 --- a/plugins/dalvik/opdefs/div_a9.d +++ b/plugins/dalvik/v35/opdefs/div_a9.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-float +@id 169 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/div_ae.d b/plugins/dalvik/v35/opdefs/div_ae.d index fae8164..aaf9952 100644 --- a/plugins/dalvik/opdefs/div_ae.d +++ b/plugins/dalvik/v35/opdefs/div_ae.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-double +@id 174 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/div_b3.d b/plugins/dalvik/v35/opdefs/div_b3.d index d1cf5d9..30c3092 100644 --- a/plugins/dalvik/opdefs/div_b3.d +++ b/plugins/dalvik/v35/opdefs/div_b3.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-int/2addr +@id 179 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/div_be.d b/plugins/dalvik/v35/opdefs/div_be.d index a146c29..3506db1 100644 --- a/plugins/dalvik/opdefs/div_be.d +++ b/plugins/dalvik/v35/opdefs/div_be.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-long/2addr +@id 190 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/div_c9.d b/plugins/dalvik/v35/opdefs/div_c9.d index 541ed90..9585edf 100644 --- a/plugins/dalvik/opdefs/div_c9.d +++ b/plugins/dalvik/v35/opdefs/div_c9.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-float/2addr +@id 201 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/div_ce.d b/plugins/dalvik/v35/opdefs/div_ce.d index 2c735e4..96e7196 100644 --- a/plugins/dalvik/opdefs/div_ce.d +++ b/plugins/dalvik/v35/opdefs/div_ce.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-double/2addr +@id 206 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/div_d3.d b/plugins/dalvik/v35/opdefs/div_d3.d index 9dde5bd..a669a66 100644 --- a/plugins/dalvik/opdefs/div_d3.d +++ b/plugins/dalvik/v35/opdefs/div_d3.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-int/lit16 +@id 211 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/div_db.d b/plugins/dalvik/v35/opdefs/div_db.d index 6754ed8..6c6ee91 100644 --- a/plugins/dalvik/opdefs/div_db.d +++ b/plugins/dalvik/v35/opdefs/div_db.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title div-int/lit8 +@id 219 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/filled_25.d b/plugins/dalvik/v35/opdefs/filled_25.d index cf31e09..aabc19f 100644 --- a/plugins/dalvik/opdefs/filled_25.d +++ b/plugins/dalvik/v35/opdefs/filled_25.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title filled-new-array/range +@id 37 + +@desc { + + Construct an array of the given type and size, filling it with the supplied contents. Clarifications and restrictions are the same as <b>filled-new-array</b>, described above. + +} + @encoding() { @format 3rc | pool_type diff --git a/plugins/dalvik/opdefs/goto_28.d b/plugins/dalvik/v35/opdefs/goto_28.d index a9c12d1..1d99514 100644 --- a/plugins/dalvik/opdefs/goto_28.d +++ b/plugins/dalvik/v35/opdefs/goto_28.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title goto +@id 40 + +@desc { + + Unconditionally jump to the indicated instruction. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either with <b>goto/32</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 10t diff --git a/plugins/dalvik/opdefs/goto_29.d b/plugins/dalvik/v35/opdefs/goto_29.d index 8272a7d..6a19c84 100644 --- a/plugins/dalvik/opdefs/goto_29.d +++ b/plugins/dalvik/v35/opdefs/goto_29.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title goto/16 +@id 41 + +@desc { + + Unconditionally jump to the indicated instruction. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either with <b>goto/32</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 20t diff --git a/plugins/dalvik/opdefs/goto_2a.d b/plugins/dalvik/v35/opdefs/goto_2a.d index 937b10d..f9108ea 100644 --- a/plugins/dalvik/opdefs/goto_2a.d +++ b/plugins/dalvik/v35/opdefs/goto_2a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title goto/32 +@id 42 + +@desc { + + Unconditionally jump to the indicated instruction. + +} + @encoding() { @format 30t diff --git a/plugins/dalvik/opdefs/if_32.d b/plugins/dalvik/v35/opdefs/if_32.d index f88098a..5fe3e80 100644 --- a/plugins/dalvik/opdefs/if_32.d +++ b/plugins/dalvik/v35/opdefs/if_32.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-eq +@id 50 + +@desc { + + Branch to the given destination if the given two registers' values compare as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 22t diff --git a/plugins/dalvik/opdefs/if_33.d b/plugins/dalvik/v35/opdefs/if_33.d index f655f67..de20c7f 100644 --- a/plugins/dalvik/opdefs/if_33.d +++ b/plugins/dalvik/v35/opdefs/if_33.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-ne +@id 51 + +@desc { + + Branch to the given destination if the given two registers' values compare as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 22t diff --git a/plugins/dalvik/opdefs/if_34.d b/plugins/dalvik/v35/opdefs/if_34.d index 1146980..d571c47 100644 --- a/plugins/dalvik/opdefs/if_34.d +++ b/plugins/dalvik/v35/opdefs/if_34.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-lt +@id 52 + +@desc { + + Branch to the given destination if the given two registers' values compare as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 22t diff --git a/plugins/dalvik/opdefs/if_35.d b/plugins/dalvik/v35/opdefs/if_35.d index b11b243..2467a6d 100644 --- a/plugins/dalvik/opdefs/if_35.d +++ b/plugins/dalvik/v35/opdefs/if_35.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-ge +@id 53 + +@desc { + + Branch to the given destination if the given two registers' values compare as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 22t diff --git a/plugins/dalvik/opdefs/if_36.d b/plugins/dalvik/v35/opdefs/if_36.d index 7436901..d4142d8 100644 --- a/plugins/dalvik/opdefs/if_36.d +++ b/plugins/dalvik/v35/opdefs/if_36.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-gt +@id 54 + +@desc { + + Branch to the given destination if the given two registers' values compare as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 22t diff --git a/plugins/dalvik/opdefs/if_37.d b/plugins/dalvik/v35/opdefs/if_37.d index 9ecbd84..8097bff 100644 --- a/plugins/dalvik/opdefs/if_37.d +++ b/plugins/dalvik/v35/opdefs/if_37.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-le +@id 55 + +@desc { + + Branch to the given destination if the given two registers' values compare as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 22t diff --git a/plugins/dalvik/opdefs/if_38.d b/plugins/dalvik/v35/opdefs/if_38.d index ff21f2b..54680c2 100644 --- a/plugins/dalvik/opdefs/if_38.d +++ b/plugins/dalvik/v35/opdefs/if_38.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-eqz +@id 56 + +@desc { + + Branch to the given destination if the given register's value compares with 0 as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 21t diff --git a/plugins/dalvik/opdefs/if_39.d b/plugins/dalvik/v35/opdefs/if_39.d index 0dbba57..d74191e 100644 --- a/plugins/dalvik/opdefs/if_39.d +++ b/plugins/dalvik/v35/opdefs/if_39.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-nez +@id 57 + +@desc { + + Branch to the given destination if the given register's value compares with 0 as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 21t diff --git a/plugins/dalvik/opdefs/if_3a.d b/plugins/dalvik/v35/opdefs/if_3a.d index b003824..ded0257 100644 --- a/plugins/dalvik/opdefs/if_3a.d +++ b/plugins/dalvik/v35/opdefs/if_3a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-ltz +@id 58 + +@desc { + + Branch to the given destination if the given register's value compares with 0 as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 21t diff --git a/plugins/dalvik/opdefs/if_3b.d b/plugins/dalvik/v35/opdefs/if_3b.d index f571d7e..bd0591f 100644 --- a/plugins/dalvik/opdefs/if_3b.d +++ b/plugins/dalvik/v35/opdefs/if_3b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-gez +@id 59 + +@desc { + + Branch to the given destination if the given register's value compares with 0 as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 21t diff --git a/plugins/dalvik/opdefs/if_3c.d b/plugins/dalvik/v35/opdefs/if_3c.d index 154fe2c..9f0e622 100644 --- a/plugins/dalvik/opdefs/if_3c.d +++ b/plugins/dalvik/v35/opdefs/if_3c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-gtz +@id 60 + +@desc { + + Branch to the given destination if the given register's value compares with 0 as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 21t diff --git a/plugins/dalvik/opdefs/if_3d.d b/plugins/dalvik/v35/opdefs/if_3d.d index 2aa5f87..92eaeb9 100644 --- a/plugins/dalvik/opdefs/if_3d.d +++ b/plugins/dalvik/v35/opdefs/if_3d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title if-lez +@id 61 + +@desc { + + Branch to the given destination if the given register's value compares with 0 as specified. + +<b>Note:</b> The branch offset must not be <b>0</b>. (A spin loop may be legally constructed either by branching around a backward <b>goto</b> or by including a <b>nop</b> as a target before the branch.) + +} + @encoding() { @format 21t diff --git a/plugins/dalvik/opdefs/iget_52.d b/plugins/dalvik/v35/opdefs/iget_52.d index ca5c140..b88bb18 100644 --- a/plugins/dalvik/opdefs/iget_52.d +++ b/plugins/dalvik/v35/opdefs/iget_52.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget +@id 82 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iget_53.d b/plugins/dalvik/v35/opdefs/iget_53.d index 3d458d9..878a108 100644 --- a/plugins/dalvik/opdefs/iget_53.d +++ b/plugins/dalvik/v35/opdefs/iget_53.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget-wide +@id 83 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iget_54.d b/plugins/dalvik/v35/opdefs/iget_54.d index 343accc..6eb1235 100644 --- a/plugins/dalvik/opdefs/iget_54.d +++ b/plugins/dalvik/v35/opdefs/iget_54.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget-object +@id 84 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iget_55.d b/plugins/dalvik/v35/opdefs/iget_55.d index dc9d7a4..fa65812 100644 --- a/plugins/dalvik/opdefs/iget_55.d +++ b/plugins/dalvik/v35/opdefs/iget_55.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget-boolean +@id 85 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iget_56.d b/plugins/dalvik/v35/opdefs/iget_56.d index 92e4d6c..d77ef24 100644 --- a/plugins/dalvik/opdefs/iget_56.d +++ b/plugins/dalvik/v35/opdefs/iget_56.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget-byte +@id 86 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iget_57.d b/plugins/dalvik/v35/opdefs/iget_57.d index b8864c7..acde802 100644 --- a/plugins/dalvik/opdefs/iget_57.d +++ b/plugins/dalvik/v35/opdefs/iget_57.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget-char +@id 87 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iget_58.d b/plugins/dalvik/v35/opdefs/iget_58.d index 85a3fb8..7a0ac96 100644 --- a/plugins/dalvik/opdefs/iget_58.d +++ b/plugins/dalvik/v35/opdefs/iget_58.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iget-short +@id 88 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/instanceof_20.d b/plugins/dalvik/v35/opdefs/instanceof_20.d index 7652c56..3e84fb7 100644 --- a/plugins/dalvik/opdefs/instanceof_20.d +++ b/plugins/dalvik/v35/opdefs/instanceof_20.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title instance-of +@id 32 + +@desc { + + Store in the given destination register <b>1</b> if the indicated reference is an instance of the given type, or <b>0</b> if not. + +<b>Note:</b> Since <b>B</b> must always be a reference (and not a primitive value), this will always result in <b>0</b> being stored if <b>C</b> refers to a primitive type. + +} + @encoding() { @format 22c | pool_type diff --git a/plugins/dalvik/v35/opdefs/invoke_6e.d b/plugins/dalvik/v35/opdefs/invoke_6e.d new file mode 100644 index 0000000..a045be8 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/invoke_6e.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title invoke-virtual + +@id 110 + +@desc { + + Call the indicated method. The result (if any) may be stored with an appropriate <b>move-result*</b> variant as the immediately subsequent instruction. + +<b>invoke-virtual</b> is used to invoke a normal virtual method (a method that is not <b>private</b>, <b>static</b>, or <b>final</b>, and is also not a constructor). + +When the <b>method_id</b> references a method of a non-interface class, <b>invoke-super</b> is used to invoke the closest superclass's virtual method (as opposed to the one with the same <b>method_id</b> in the calling class). The same method restrictions hold as for <b>invoke-virtual</b>. + +In Dex files version <b>037</b> or later, if the <b>method_id</b> refers to an interface method, <b>invoke-super</b> is used to invoke the most specific, non-overridden version of that method defined on that interface. The same method restrictions hold as for <b>invoke-virtual</b>. In Dex files prior to version <b>037</b>, having an interface <b>method_id</b> is illegal and undefined. + +<b>invoke-direct</b> is used to invoke a non-<b>static</b> direct method (that is, an instance method that is by its nature non-overridable, namely either a <b>private</b> instance method or a constructor). + +<b>invoke-static</b> is used to invoke a <b>static</b> method (which is always considered a direct method). + +<b>invoke-interface</b> is used to invoke an <b>interface</b> method, that is, on an object whose concrete class isn't known, using a <b>method_id</b> that refers to an <b>interface</b>. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the method argument to be a more direct offset (or pair thereof). + +} + +@encoding() { + + @format 35c | pool_meth + +} diff --git a/plugins/dalvik/v35/opdefs/invoke_6f.d b/plugins/dalvik/v35/opdefs/invoke_6f.d new file mode 100644 index 0000000..804f2d1 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/invoke_6f.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title invoke-super + +@id 111 + +@desc { + + Call the indicated method. The result (if any) may be stored with an appropriate <b>move-result*</b> variant as the immediately subsequent instruction. + +<b>invoke-virtual</b> is used to invoke a normal virtual method (a method that is not <b>private</b>, <b>static</b>, or <b>final</b>, and is also not a constructor). + +When the <b>method_id</b> references a method of a non-interface class, <b>invoke-super</b> is used to invoke the closest superclass's virtual method (as opposed to the one with the same <b>method_id</b> in the calling class). The same method restrictions hold as for <b>invoke-virtual</b>. + +In Dex files version <b>037</b> or later, if the <b>method_id</b> refers to an interface method, <b>invoke-super</b> is used to invoke the most specific, non-overridden version of that method defined on that interface. The same method restrictions hold as for <b>invoke-virtual</b>. In Dex files prior to version <b>037</b>, having an interface <b>method_id</b> is illegal and undefined. + +<b>invoke-direct</b> is used to invoke a non-<b>static</b> direct method (that is, an instance method that is by its nature non-overridable, namely either a <b>private</b> instance method or a constructor). + +<b>invoke-static</b> is used to invoke a <b>static</b> method (which is always considered a direct method). + +<b>invoke-interface</b> is used to invoke an <b>interface</b> method, that is, on an object whose concrete class isn't known, using a <b>method_id</b> that refers to an <b>interface</b>. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the method argument to be a more direct offset (or pair thereof). + +} + +@encoding() { + + @format 35c | pool_meth + +} diff --git a/plugins/dalvik/v35/opdefs/invoke_70.d b/plugins/dalvik/v35/opdefs/invoke_70.d new file mode 100644 index 0000000..f383427 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/invoke_70.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title invoke-direct + +@id 112 + +@desc { + + Call the indicated method. The result (if any) may be stored with an appropriate <b>move-result*</b> variant as the immediately subsequent instruction. + +<b>invoke-virtual</b> is used to invoke a normal virtual method (a method that is not <b>private</b>, <b>static</b>, or <b>final</b>, and is also not a constructor). + +When the <b>method_id</b> references a method of a non-interface class, <b>invoke-super</b> is used to invoke the closest superclass's virtual method (as opposed to the one with the same <b>method_id</b> in the calling class). The same method restrictions hold as for <b>invoke-virtual</b>. + +In Dex files version <b>037</b> or later, if the <b>method_id</b> refers to an interface method, <b>invoke-super</b> is used to invoke the most specific, non-overridden version of that method defined on that interface. The same method restrictions hold as for <b>invoke-virtual</b>. In Dex files prior to version <b>037</b>, having an interface <b>method_id</b> is illegal and undefined. + +<b>invoke-direct</b> is used to invoke a non-<b>static</b> direct method (that is, an instance method that is by its nature non-overridable, namely either a <b>private</b> instance method or a constructor). + +<b>invoke-static</b> is used to invoke a <b>static</b> method (which is always considered a direct method). + +<b>invoke-interface</b> is used to invoke an <b>interface</b> method, that is, on an object whose concrete class isn't known, using a <b>method_id</b> that refers to an <b>interface</b>. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the method argument to be a more direct offset (or pair thereof). + +} + +@encoding() { + + @format 35c | pool_meth + +} diff --git a/plugins/dalvik/v35/opdefs/invoke_71.d b/plugins/dalvik/v35/opdefs/invoke_71.d new file mode 100644 index 0000000..b21eca3 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/invoke_71.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title invoke-static + +@id 113 + +@desc { + + Call the indicated method. The result (if any) may be stored with an appropriate <b>move-result*</b> variant as the immediately subsequent instruction. + +<b>invoke-virtual</b> is used to invoke a normal virtual method (a method that is not <b>private</b>, <b>static</b>, or <b>final</b>, and is also not a constructor). + +When the <b>method_id</b> references a method of a non-interface class, <b>invoke-super</b> is used to invoke the closest superclass's virtual method (as opposed to the one with the same <b>method_id</b> in the calling class). The same method restrictions hold as for <b>invoke-virtual</b>. + +In Dex files version <b>037</b> or later, if the <b>method_id</b> refers to an interface method, <b>invoke-super</b> is used to invoke the most specific, non-overridden version of that method defined on that interface. The same method restrictions hold as for <b>invoke-virtual</b>. In Dex files prior to version <b>037</b>, having an interface <b>method_id</b> is illegal and undefined. + +<b>invoke-direct</b> is used to invoke a non-<b>static</b> direct method (that is, an instance method that is by its nature non-overridable, namely either a <b>private</b> instance method or a constructor). + +<b>invoke-static</b> is used to invoke a <b>static</b> method (which is always considered a direct method). + +<b>invoke-interface</b> is used to invoke an <b>interface</b> method, that is, on an object whose concrete class isn't known, using a <b>method_id</b> that refers to an <b>interface</b>. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the method argument to be a more direct offset (or pair thereof). + +} + +@encoding() { + + @format 35c | pool_meth + +} diff --git a/plugins/dalvik/v35/opdefs/invoke_72.d b/plugins/dalvik/v35/opdefs/invoke_72.d new file mode 100644 index 0000000..74cca2b --- /dev/null +++ b/plugins/dalvik/v35/opdefs/invoke_72.d @@ -0,0 +1,52 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title invoke-interface + +@id 114 + +@desc { + + Call the indicated method. The result (if any) may be stored with an appropriate <b>move-result*</b> variant as the immediately subsequent instruction. + +<b>invoke-virtual</b> is used to invoke a normal virtual method (a method that is not <b>private</b>, <b>static</b>, or <b>final</b>, and is also not a constructor). + +When the <b>method_id</b> references a method of a non-interface class, <b>invoke-super</b> is used to invoke the closest superclass's virtual method (as opposed to the one with the same <b>method_id</b> in the calling class). The same method restrictions hold as for <b>invoke-virtual</b>. + +In Dex files version <b>037</b> or later, if the <b>method_id</b> refers to an interface method, <b>invoke-super</b> is used to invoke the most specific, non-overridden version of that method defined on that interface. The same method restrictions hold as for <b>invoke-virtual</b>. In Dex files prior to version <b>037</b>, having an interface <b>method_id</b> is illegal and undefined. + +<b>invoke-direct</b> is used to invoke a non-<b>static</b> direct method (that is, an instance method that is by its nature non-overridable, namely either a <b>private</b> instance method or a constructor). + +<b>invoke-static</b> is used to invoke a <b>static</b> method (which is always considered a direct method). + +<b>invoke-interface</b> is used to invoke an <b>interface</b> method, that is, on an object whose concrete class isn't known, using a <b>method_id</b> that refers to an <b>interface</b>. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the method argument to be a more direct offset (or pair thereof). + +} + +@encoding() { + + @format 35c | pool_meth + +} diff --git a/plugins/dalvik/opdefs/invoke_74.d b/plugins/dalvik/v35/opdefs/invoke_74.d index 77b68de..e8275fc 100644 --- a/plugins/dalvik/opdefs/invoke_74.d +++ b/plugins/dalvik/v35/opdefs/invoke_74.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title invoke-virtual/range +@id 116 + +@desc { + + Call the indicated method. See first <b>invoke-<i>kind</i></b> description above for details, caveats, and suggestions. + +} + @encoding() { @format 3rc | pool_meth diff --git a/plugins/dalvik/opdefs/invoke_75.d b/plugins/dalvik/v35/opdefs/invoke_75.d index e886dad..5802f05 100644 --- a/plugins/dalvik/opdefs/invoke_75.d +++ b/plugins/dalvik/v35/opdefs/invoke_75.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title invoke-super/range +@id 117 + +@desc { + + Call the indicated method. See first <b>invoke-<i>kind</i></b> description above for details, caveats, and suggestions. + +} + @encoding() { @format 3rc | pool_meth diff --git a/plugins/dalvik/opdefs/invoke_76.d b/plugins/dalvik/v35/opdefs/invoke_76.d index 8156689..ac1a7b0 100644 --- a/plugins/dalvik/opdefs/invoke_76.d +++ b/plugins/dalvik/v35/opdefs/invoke_76.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title invoke-direct/range +@id 118 + +@desc { + + Call the indicated method. See first <b>invoke-<i>kind</i></b> description above for details, caveats, and suggestions. + +} + @encoding() { @format 3rc | pool_meth diff --git a/plugins/dalvik/opdefs/invoke_77.d b/plugins/dalvik/v35/opdefs/invoke_77.d index b5707e2..64d6075 100644 --- a/plugins/dalvik/opdefs/invoke_77.d +++ b/plugins/dalvik/v35/opdefs/invoke_77.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title invoke-static/range +@id 119 + +@desc { + + Call the indicated method. See first <b>invoke-<i>kind</i></b> description above for details, caveats, and suggestions. + +} + @encoding() { @format 3rc | pool_meth diff --git a/plugins/dalvik/opdefs/invoke_78.d b/plugins/dalvik/v35/opdefs/invoke_78.d index 5589b38..f3e8839 100644 --- a/plugins/dalvik/opdefs/invoke_78.d +++ b/plugins/dalvik/v35/opdefs/invoke_78.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title invoke-interface/range +@id 120 + +@desc { + + Call the indicated method. See first <b>invoke-<i>kind</i></b> description above for details, caveats, and suggestions. + +} + @encoding() { @format 3rc | pool_meth diff --git a/plugins/dalvik/opdefs/iput_59.d b/plugins/dalvik/v35/opdefs/iput_59.d index fd17db4..b11da8b 100644 --- a/plugins/dalvik/opdefs/iput_59.d +++ b/plugins/dalvik/v35/opdefs/iput_59.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput +@id 89 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iput_5a.d b/plugins/dalvik/v35/opdefs/iput_5a.d index 509868c..f2e8311 100644 --- a/plugins/dalvik/opdefs/iput_5a.d +++ b/plugins/dalvik/v35/opdefs/iput_5a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput-wide +@id 90 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iput_5b.d b/plugins/dalvik/v35/opdefs/iput_5b.d index 9ad7500..631892c 100644 --- a/plugins/dalvik/opdefs/iput_5b.d +++ b/plugins/dalvik/v35/opdefs/iput_5b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput-object +@id 91 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iput_5c.d b/plugins/dalvik/v35/opdefs/iput_5c.d index 9ae86fa..8cc1fb6 100644 --- a/plugins/dalvik/opdefs/iput_5c.d +++ b/plugins/dalvik/v35/opdefs/iput_5c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput-boolean +@id 92 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iput_5d.d b/plugins/dalvik/v35/opdefs/iput_5d.d index 8a3830e..93edb58 100644 --- a/plugins/dalvik/opdefs/iput_5d.d +++ b/plugins/dalvik/v35/opdefs/iput_5d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput-byte +@id 93 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iput_5e.d b/plugins/dalvik/v35/opdefs/iput_5e.d index 5120675..48cb4f6 100644 --- a/plugins/dalvik/opdefs/iput_5e.d +++ b/plugins/dalvik/v35/opdefs/iput_5e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput-char +@id 94 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/iput_5f.d b/plugins/dalvik/v35/opdefs/iput_5f.d index 7fe2d80..9bbd72a 100644 --- a/plugins/dalvik/opdefs/iput_5f.d +++ b/plugins/dalvik/v35/opdefs/iput_5f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title iput-short +@id 95 + +@desc { + + Perform the identified object instance field operation with the identified field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 22c | pool_field diff --git a/plugins/dalvik/opdefs/monitor_1d.d b/plugins/dalvik/v35/opdefs/monitor_1d.d index ab7ce5f..101ffad 100644 --- a/plugins/dalvik/opdefs/monitor_1d.d +++ b/plugins/dalvik/v35/opdefs/monitor_1d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title monitor-enter +@id 29 + +@desc { + + Acquire the monitor for the indicated object. + +} + @encoding() { @format 11x diff --git a/plugins/dalvik/opdefs/monitor_1e.d b/plugins/dalvik/v35/opdefs/monitor_1e.d index b5b0d20..b54af35 100644 --- a/plugins/dalvik/opdefs/monitor_1e.d +++ b/plugins/dalvik/v35/opdefs/monitor_1e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title monitor-exit +@id 30 + +@desc { + + Release the monitor for the indicated object. + +<b>Note:</b> If this instruction needs to throw an exception, it must do so as if the pc has already advanced past the instruction. It may be useful to think of this as the instruction successfully executing (in a sense), and the exception getting thrown <i>after</i> the instruction but <i>before</i> the next one gets a chance to run. This definition makes it possible for a method to use a monitor cleanup catch-all (e.g., <b>finally</b>) block as the monitor cleanup for that block itself, as a way to handle the arbitrary exceptions that might get thrown due to the historical implementation of <b>Thread.stop()</b>, while still managing to have proper monitor hygiene. + +} + @encoding() { @format 11x diff --git a/plugins/dalvik/opdefs/move_01.d b/plugins/dalvik/v35/opdefs/move_01.d index caa2a85..788a359 100644 --- a/plugins/dalvik/opdefs/move_01.d +++ b/plugins/dalvik/v35/opdefs/move_01.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move +@id 1 + +@desc { + + Move the contents of one non-object register to another. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/move_02.d b/plugins/dalvik/v35/opdefs/move_02.d index c8b96bd..8453561 100644 --- a/plugins/dalvik/opdefs/move_02.d +++ b/plugins/dalvik/v35/opdefs/move_02.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move/from16 +@id 2 + +@desc { + + Move the contents of one non-object register to another. + +} + @encoding() { @format 22x diff --git a/plugins/dalvik/opdefs/move_03.d b/plugins/dalvik/v35/opdefs/move_03.d index 6957de7..a665ccd 100644 --- a/plugins/dalvik/opdefs/move_03.d +++ b/plugins/dalvik/v35/opdefs/move_03.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move/16 +@id 3 + +@desc { + + Move the contents of one non-object register to another. + +} + @encoding() { @format 32x diff --git a/plugins/dalvik/opdefs/move_04.d b/plugins/dalvik/v35/opdefs/move_04.d index 57196cc..d4f9395 100644 --- a/plugins/dalvik/opdefs/move_04.d +++ b/plugins/dalvik/v35/opdefs/move_04.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title move-wide +@id 4 + +@desc { + + Move the contents of one register-pair to another. + +<b>Note:</b> It is legal to move from <b>v<i>N</i></b> to either <b>v<i>N-1</i></b> or <b>v<i>N+1</i></b>, so implementations must arrange for both halves of a register pair to be read before anything is written. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/move_05.d b/plugins/dalvik/v35/opdefs/move_05.d index 2b974bb..36b276c 100644 --- a/plugins/dalvik/opdefs/move_05.d +++ b/plugins/dalvik/v35/opdefs/move_05.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title move-wide/from16 +@id 5 + +@desc { + + Move the contents of one register-pair to another. + +<b>Note:</b> Implementation considerations are the same as <b>move-wide</b>, above. + +} + @encoding() { @format 22x diff --git a/plugins/dalvik/opdefs/move_06.d b/plugins/dalvik/v35/opdefs/move_06.d index 4acaf62..2b40adb 100644 --- a/plugins/dalvik/opdefs/move_06.d +++ b/plugins/dalvik/v35/opdefs/move_06.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title move-wide/16 +@id 6 + +@desc { + + Move the contents of one register-pair to another. + +<b>Note:</b> Implementation considerations are the same as <b>move-wide</b>, above. + +} + @encoding() { @format 32x diff --git a/plugins/dalvik/opdefs/move_07.d b/plugins/dalvik/v35/opdefs/move_07.d index cde3102..8d982e5 100644 --- a/plugins/dalvik/opdefs/move_07.d +++ b/plugins/dalvik/v35/opdefs/move_07.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-object +@id 7 + +@desc { + + Move the contents of one object-bearing register to another. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/move_08.d b/plugins/dalvik/v35/opdefs/move_08.d index aba0cad..d58d356 100644 --- a/plugins/dalvik/opdefs/move_08.d +++ b/plugins/dalvik/v35/opdefs/move_08.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-object/from16 +@id 8 + +@desc { + + Move the contents of one object-bearing register to another. + +} + @encoding() { @format 22x diff --git a/plugins/dalvik/opdefs/move_09.d b/plugins/dalvik/v35/opdefs/move_09.d index 3bf6a65..520c03e 100644 --- a/plugins/dalvik/opdefs/move_09.d +++ b/plugins/dalvik/v35/opdefs/move_09.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-object/16 +@id 9 + +@desc { + + Move the contents of one object-bearing register to another. + +} + @encoding() { @format 32x diff --git a/plugins/dalvik/opdefs/move_0a.d b/plugins/dalvik/v35/opdefs/move_0a.d index b6a185a..250b8fc 100644 --- a/plugins/dalvik/opdefs/move_0a.d +++ b/plugins/dalvik/v35/opdefs/move_0a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-result +@id 10 + +@desc { + + Move the single-word non-object result of the most recent <b>invoke-<i>kind</i></b> into the indicated register. This must be done as the instruction immediately after an <b>invoke-<i>kind</i></b> whose (single-word, non-object) result is not to be ignored; anywhere else is invalid. + +} + @encoding() { @format 11x diff --git a/plugins/dalvik/opdefs/move_0b.d b/plugins/dalvik/v35/opdefs/move_0b.d index d266cb8..35b6270 100644 --- a/plugins/dalvik/opdefs/move_0b.d +++ b/plugins/dalvik/v35/opdefs/move_0b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-result-wide +@id 11 + +@desc { + + Move the double-word result of the most recent <b>invoke-<i>kind</i></b> into the indicated register pair. This must be done as the instruction immediately after an <b>invoke-<i>kind</i></b> whose (double-word) result is not to be ignored; anywhere else is invalid. + +} + @encoding() { @format 11x diff --git a/plugins/dalvik/opdefs/move_0c.d b/plugins/dalvik/v35/opdefs/move_0c.d index 8e6f67f..4109578 100644 --- a/plugins/dalvik/opdefs/move_0c.d +++ b/plugins/dalvik/v35/opdefs/move_0c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-result-object +@id 12 + +@desc { + + Move the object result of the most recent <b>invoke-<i>kind</i></b> into the indicated register. This must be done as the instruction immediately after an <b>invoke-<i>kind</i></b> or <b>filled-new-array</b> whose (object) result is not to be ignored; anywhere else is invalid. + +} + @encoding() { @format 11x diff --git a/plugins/dalvik/opdefs/move_0d.d b/plugins/dalvik/v35/opdefs/move_0d.d index f442006..155e585 100644 --- a/plugins/dalvik/opdefs/move_0d.d +++ b/plugins/dalvik/v35/opdefs/move_0d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title move-exception +@id 13 + +@desc { + + Save a just-caught exception into the given register. This must be the first instruction of any exception handler whose caught exception is not to be ignored, and this instruction must <i>only</i> ever occur as the first instruction of an exception handler; anywhere else is invalid. + +} + @encoding() { @format 11x diff --git a/plugins/dalvik/opdefs/mul_92.d b/plugins/dalvik/v35/opdefs/mul_92.d index 83b5cac..7de6f1a 100644 --- a/plugins/dalvik/opdefs/mul_92.d +++ b/plugins/dalvik/v35/opdefs/mul_92.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-int +@id 146 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/mul_9d.d b/plugins/dalvik/v35/opdefs/mul_9d.d index ecc216d..0f62e22 100644 --- a/plugins/dalvik/opdefs/mul_9d.d +++ b/plugins/dalvik/v35/opdefs/mul_9d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-long +@id 157 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/mul_a8.d b/plugins/dalvik/v35/opdefs/mul_a8.d index 63e51e5..0a77ac1 100644 --- a/plugins/dalvik/opdefs/mul_a8.d +++ b/plugins/dalvik/v35/opdefs/mul_a8.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-float +@id 168 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/mul_ad.d b/plugins/dalvik/v35/opdefs/mul_ad.d index 17f950c..8f43825 100644 --- a/plugins/dalvik/opdefs/mul_ad.d +++ b/plugins/dalvik/v35/opdefs/mul_ad.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-double +@id 173 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/mul_b2.d b/plugins/dalvik/v35/opdefs/mul_b2.d index a7b917c..b82d948 100644 --- a/plugins/dalvik/opdefs/mul_b2.d +++ b/plugins/dalvik/v35/opdefs/mul_b2.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-int/2addr +@id 178 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/mul_bd.d b/plugins/dalvik/v35/opdefs/mul_bd.d index 8ce23b1..622dd61 100644 --- a/plugins/dalvik/opdefs/mul_bd.d +++ b/plugins/dalvik/v35/opdefs/mul_bd.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-long/2addr +@id 189 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/mul_c8.d b/plugins/dalvik/v35/opdefs/mul_c8.d index 1d17cc1..04a1ac1 100644 --- a/plugins/dalvik/opdefs/mul_c8.d +++ b/plugins/dalvik/v35/opdefs/mul_c8.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-float/2addr +@id 200 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/mul_cd.d b/plugins/dalvik/v35/opdefs/mul_cd.d index 1816780..3622c1a 100644 --- a/plugins/dalvik/opdefs/mul_cd.d +++ b/plugins/dalvik/v35/opdefs/mul_cd.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-double/2addr +@id 205 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/mul_d2.d b/plugins/dalvik/v35/opdefs/mul_d2.d index 998ecd7..b7f44a0 100644 --- a/plugins/dalvik/opdefs/mul_d2.d +++ b/plugins/dalvik/v35/opdefs/mul_d2.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-int/lit16 +@id 210 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/mul_da.d b/plugins/dalvik/v35/opdefs/mul_da.d index 4c1a264..ac7fba2 100644 --- a/plugins/dalvik/opdefs/mul_da.d +++ b/plugins/dalvik/v35/opdefs/mul_da.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title mul-int/lit8 +@id 218 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/neg_7b.d b/plugins/dalvik/v35/opdefs/neg_7b.d index c8ec7df..1e518e2 100644 --- a/plugins/dalvik/opdefs/neg_7b.d +++ b/plugins/dalvik/v35/opdefs/neg_7b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title neg-int +@id 123 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/neg_7d.d b/plugins/dalvik/v35/opdefs/neg_7d.d index 3d442c3..370aa5f 100644 --- a/plugins/dalvik/opdefs/neg_7d.d +++ b/plugins/dalvik/v35/opdefs/neg_7d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title neg-long +@id 125 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/neg_7f.d b/plugins/dalvik/v35/opdefs/neg_7f.d index d30ede6..39b8dcd 100644 --- a/plugins/dalvik/opdefs/neg_7f.d +++ b/plugins/dalvik/v35/opdefs/neg_7f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title neg-float +@id 127 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/neg_80.d b/plugins/dalvik/v35/opdefs/neg_80.d index 49d6bdd..e0faa70 100644 --- a/plugins/dalvik/opdefs/neg_80.d +++ b/plugins/dalvik/v35/opdefs/neg_80.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title neg-double +@id 128 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/new_22.d b/plugins/dalvik/v35/opdefs/new_22.d index 4af913c..f23307f 100644 --- a/plugins/dalvik/opdefs/new_22.d +++ b/plugins/dalvik/v35/opdefs/new_22.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title new-instance +@id 34 + +@desc { + + Construct a new instance of the indicated type, storing a reference to it in the destination. The type must refer to a non-array class. + +} + @encoding() { @format 21c | pool_type diff --git a/plugins/dalvik/opdefs/new_23.d b/plugins/dalvik/v35/opdefs/new_23.d index 0a6a863..7639e2c 100644 --- a/plugins/dalvik/opdefs/new_23.d +++ b/plugins/dalvik/v35/opdefs/new_23.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title new-array +@id 35 + +@desc { + + Construct a new array of the indicated type and size. The type must be an array type. + +} + @encoding() { @format 22c | pool_type diff --git a/plugins/dalvik/v35/opdefs/nop_00.d b/plugins/dalvik/v35/opdefs/nop_00.d new file mode 100644 index 0000000..b48d883 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/nop_00.d @@ -0,0 +1,40 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title nop + +@id 0 + +@desc { + + Waste cycles. + +<b>Note:</b> Data-bearing pseudo-instructions are tagged with this opb, in which case the high-order byte of the opb unit indicates the nature of the data. See "<b>packed-switch-payload</b> Format", "<b>sparse-switch-payload</b> Format", and "<b>fill-array-data-payload</b> Format" below. + +} + +@encoding() { + + @format 10x + +} diff --git a/plugins/dalvik/opdefs/not_7c.d b/plugins/dalvik/v35/opdefs/not_7c.d index d52ad8c..395dcb1 100644 --- a/plugins/dalvik/opdefs/not_7c.d +++ b/plugins/dalvik/v35/opdefs/not_7c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title not-int +@id 124 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/not_7e.d b/plugins/dalvik/v35/opdefs/not_7e.d index 4291d7a..0a50102 100644 --- a/plugins/dalvik/opdefs/not_7e.d +++ b/plugins/dalvik/v35/opdefs/not_7e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title not-long +@id 126 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/or_96.d b/plugins/dalvik/v35/opdefs/or_96.d index 62f24a5..cbdfd0b 100644 --- a/plugins/dalvik/opdefs/or_96.d +++ b/plugins/dalvik/v35/opdefs/or_96.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title or-int +@id 150 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/or_a1.d b/plugins/dalvik/v35/opdefs/or_a1.d index 2867a81..b5ec103 100644 --- a/plugins/dalvik/opdefs/or_a1.d +++ b/plugins/dalvik/v35/opdefs/or_a1.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title or-long +@id 161 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/or_b6.d b/plugins/dalvik/v35/opdefs/or_b6.d index 3d56801..8dd878a 100644 --- a/plugins/dalvik/opdefs/or_b6.d +++ b/plugins/dalvik/v35/opdefs/or_b6.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title or-int/2addr +@id 182 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/or_c1.d b/plugins/dalvik/v35/opdefs/or_c1.d index 8d13da3..d7224a4 100644 --- a/plugins/dalvik/opdefs/or_c1.d +++ b/plugins/dalvik/v35/opdefs/or_c1.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title or-long/2addr +@id 193 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/or_d6.d b/plugins/dalvik/v35/opdefs/or_d6.d index 71766a3..3543093 100644 --- a/plugins/dalvik/opdefs/or_d6.d +++ b/plugins/dalvik/v35/opdefs/or_d6.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title or-int/lit16 +@id 214 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/or_de.d b/plugins/dalvik/v35/opdefs/or_de.d index 1c293a5..582ed6a 100644 --- a/plugins/dalvik/opdefs/or_de.d +++ b/plugins/dalvik/v35/opdefs/or_de.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title or-int/lit8 +@id 222 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/rem_94.d b/plugins/dalvik/v35/opdefs/rem_94.d index 9238d14..54aeaa6 100644 --- a/plugins/dalvik/opdefs/rem_94.d +++ b/plugins/dalvik/v35/opdefs/rem_94.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-int +@id 148 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/rem_9f.d b/plugins/dalvik/v35/opdefs/rem_9f.d index 6aef568..1fe7291 100644 --- a/plugins/dalvik/opdefs/rem_9f.d +++ b/plugins/dalvik/v35/opdefs/rem_9f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-long +@id 159 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/rem_aa.d b/plugins/dalvik/v35/opdefs/rem_aa.d index 71a0d8b..54f6f08 100644 --- a/plugins/dalvik/opdefs/rem_aa.d +++ b/plugins/dalvik/v35/opdefs/rem_aa.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-float +@id 170 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/rem_af.d b/plugins/dalvik/v35/opdefs/rem_af.d index dc092a1..8441dad 100644 --- a/plugins/dalvik/opdefs/rem_af.d +++ b/plugins/dalvik/v35/opdefs/rem_af.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-double +@id 175 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/rem_b4.d b/plugins/dalvik/v35/opdefs/rem_b4.d index fada523..8c904c7 100644 --- a/plugins/dalvik/opdefs/rem_b4.d +++ b/plugins/dalvik/v35/opdefs/rem_b4.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-int/2addr +@id 180 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/rem_bf.d b/plugins/dalvik/v35/opdefs/rem_bf.d index b6b0997..85863b9 100644 --- a/plugins/dalvik/opdefs/rem_bf.d +++ b/plugins/dalvik/v35/opdefs/rem_bf.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-long/2addr +@id 191 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/rem_ca.d b/plugins/dalvik/v35/opdefs/rem_ca.d index 3c6d287..6d69082 100644 --- a/plugins/dalvik/opdefs/rem_ca.d +++ b/plugins/dalvik/v35/opdefs/rem_ca.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-float/2addr +@id 202 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/rem_cf.d b/plugins/dalvik/v35/opdefs/rem_cf.d index 1881502..502baad 100644 --- a/plugins/dalvik/opdefs/rem_cf.d +++ b/plugins/dalvik/v35/opdefs/rem_cf.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-double/2addr +@id 207 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/rem_d4.d b/plugins/dalvik/v35/opdefs/rem_d4.d index 84d12b8..faf7390 100644 --- a/plugins/dalvik/opdefs/rem_d4.d +++ b/plugins/dalvik/v35/opdefs/rem_d4.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-int/lit16 +@id 212 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/rem_dc.d b/plugins/dalvik/v35/opdefs/rem_dc.d index f70f9e9..a19c7df 100644 --- a/plugins/dalvik/opdefs/rem_dc.d +++ b/plugins/dalvik/v35/opdefs/rem_dc.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rem-int/lit8 +@id 220 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/return_0e.d b/plugins/dalvik/v35/opdefs/return_0e.d index 98fa1a8..7c42cb7 100644 --- a/plugins/dalvik/opdefs/return_0e.d +++ b/plugins/dalvik/v35/opdefs/return_0e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,13 +23,25 @@ @title return-void +@id 14 + +@desc { + + Return from a <b>void</b> method. + +} + @encoding() { @format 10x - @rules { + @syntax { + + @rules { + + call g_arch_instruction_set_flag(AIF_RETURN_POINT) - call SetInsFlag(AIF_RETURN_POINT) + } } diff --git a/plugins/dalvik/opdefs/return_0f.d b/plugins/dalvik/v35/opdefs/return_0f.d index 7e681ae..2051443 100644 --- a/plugins/dalvik/opdefs/return_0f.d +++ b/plugins/dalvik/v35/opdefs/return_0f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,13 +23,25 @@ @title return +@id 15 + +@desc { + + Return from a single-width (32-bit) non-object value-returning method. + +} + @encoding() { @format 11x - @rules { + @syntax { + + @rules { + + call g_arch_instruction_set_flag(AIF_RETURN_POINT) - call SetInsFlag(AIF_RETURN_POINT) + } } diff --git a/plugins/dalvik/opdefs/return_10.d b/plugins/dalvik/v35/opdefs/return_10.d index 644760c..7cf1ce3 100644 --- a/plugins/dalvik/opdefs/return_10.d +++ b/plugins/dalvik/v35/opdefs/return_10.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,13 +23,25 @@ @title return-wide +@id 16 + +@desc { + + Return from a double-width (64-bit) value-returning method. + +} + @encoding() { @format 11x - @rules { + @syntax { + + @rules { + + call g_arch_instruction_set_flag(AIF_RETURN_POINT) - call SetInsFlag(AIF_RETURN_POINT) + } } diff --git a/plugins/dalvik/opdefs/return_11.d b/plugins/dalvik/v35/opdefs/return_11.d index b8e4e60..4023de7 100644 --- a/plugins/dalvik/opdefs/return_11.d +++ b/plugins/dalvik/v35/opdefs/return_11.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,13 +23,25 @@ @title return-object +@id 17 + +@desc { + + Return from an object-returning method. + +} + @encoding() { @format 11x - @rules { + @syntax { + + @rules { + + call g_arch_instruction_set_flag(AIF_RETURN_POINT) - call SetInsFlag(AIF_RETURN_POINT) + } } diff --git a/plugins/dalvik/opdefs/rsub_d1.d b/plugins/dalvik/v35/opdefs/rsub_d1.d index 0d05c84..4385967 100644 --- a/plugins/dalvik/opdefs/rsub_d1.d +++ b/plugins/dalvik/v35/opdefs/rsub_d1.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rsub-int +@id 209 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/rsub_d9.d b/plugins/dalvik/v35/opdefs/rsub_d9.d index 0f2f656..890846c 100644 --- a/plugins/dalvik/opdefs/rsub_d9.d +++ b/plugins/dalvik/v35/opdefs/rsub_d9.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title rsub-int/lit8 +@id 217 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/sget_60.d b/plugins/dalvik/v35/opdefs/sget_60.d index 90090a2..e017ff8 100644 --- a/plugins/dalvik/opdefs/sget_60.d +++ b/plugins/dalvik/v35/opdefs/sget_60.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget +@id 96 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sget_61.d b/plugins/dalvik/v35/opdefs/sget_61.d index c3f132c..faa94e4 100644 --- a/plugins/dalvik/opdefs/sget_61.d +++ b/plugins/dalvik/v35/opdefs/sget_61.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget-wide +@id 97 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sget_62.d b/plugins/dalvik/v35/opdefs/sget_62.d index 97d41d9..310c7a1 100644 --- a/plugins/dalvik/opdefs/sget_62.d +++ b/plugins/dalvik/v35/opdefs/sget_62.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget-object +@id 98 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sget_63.d b/plugins/dalvik/v35/opdefs/sget_63.d index 0dca873..3027a44 100644 --- a/plugins/dalvik/opdefs/sget_63.d +++ b/plugins/dalvik/v35/opdefs/sget_63.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget-boolean +@id 99 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sget_64.d b/plugins/dalvik/v35/opdefs/sget_64.d index 507420e..307572d 100644 --- a/plugins/dalvik/opdefs/sget_64.d +++ b/plugins/dalvik/v35/opdefs/sget_64.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget-byte +@id 100 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sget_65.d b/plugins/dalvik/v35/opdefs/sget_65.d index 5236314..488c1ab 100644 --- a/plugins/dalvik/opdefs/sget_65.d +++ b/plugins/dalvik/v35/opdefs/sget_65.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget-char +@id 101 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sget_66.d b/plugins/dalvik/v35/opdefs/sget_66.d index 9f8b4fa..fb0f2ab 100644 --- a/plugins/dalvik/opdefs/sget_66.d +++ b/plugins/dalvik/v35/opdefs/sget_66.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sget-short +@id 102 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/shl_98.d b/plugins/dalvik/v35/opdefs/shl_98.d index bfb92bd..ed1ec68 100644 --- a/plugins/dalvik/opdefs/shl_98.d +++ b/plugins/dalvik/v35/opdefs/shl_98.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shl-int +@id 152 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/shl_a3.d b/plugins/dalvik/v35/opdefs/shl_a3.d index c3772b0..bc485a4 100644 --- a/plugins/dalvik/opdefs/shl_a3.d +++ b/plugins/dalvik/v35/opdefs/shl_a3.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shl-long +@id 163 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/shl_b8.d b/plugins/dalvik/v35/opdefs/shl_b8.d index 70f99e1..800398a 100644 --- a/plugins/dalvik/opdefs/shl_b8.d +++ b/plugins/dalvik/v35/opdefs/shl_b8.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shl-int/2addr +@id 184 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/shl_c3.d b/plugins/dalvik/v35/opdefs/shl_c3.d index 94d35e5..3b07705 100644 --- a/plugins/dalvik/opdefs/shl_c3.d +++ b/plugins/dalvik/v35/opdefs/shl_c3.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shl-long/2addr +@id 195 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/shl_e0.d b/plugins/dalvik/v35/opdefs/shl_e0.d index c5c8d50..a419946 100644 --- a/plugins/dalvik/opdefs/shl_e0.d +++ b/plugins/dalvik/v35/opdefs/shl_e0.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shl-int/lit8 +@id 224 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/shr_99.d b/plugins/dalvik/v35/opdefs/shr_99.d index 203e4d5..d8658bc 100644 --- a/plugins/dalvik/opdefs/shr_99.d +++ b/plugins/dalvik/v35/opdefs/shr_99.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shr-int +@id 153 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/shr_a4.d b/plugins/dalvik/v35/opdefs/shr_a4.d index 16e07a6..d12821b 100644 --- a/plugins/dalvik/opdefs/shr_a4.d +++ b/plugins/dalvik/v35/opdefs/shr_a4.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shr-long +@id 164 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/shr_b9.d b/plugins/dalvik/v35/opdefs/shr_b9.d index 5f48795..55c3e77 100644 --- a/plugins/dalvik/opdefs/shr_b9.d +++ b/plugins/dalvik/v35/opdefs/shr_b9.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shr-int/2addr +@id 185 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/shr_c4.d b/plugins/dalvik/v35/opdefs/shr_c4.d index 80cbfee..6f6862f 100644 --- a/plugins/dalvik/opdefs/shr_c4.d +++ b/plugins/dalvik/v35/opdefs/shr_c4.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shr-long/2addr +@id 196 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/shr_e1.d b/plugins/dalvik/v35/opdefs/shr_e1.d index 38a30dc..728798a 100644 --- a/plugins/dalvik/opdefs/shr_e1.d +++ b/plugins/dalvik/v35/opdefs/shr_e1.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title shr-int/lit8 +@id 225 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/sput_67.d b/plugins/dalvik/v35/opdefs/sput_67.d index 149337a..11c3faa 100644 --- a/plugins/dalvik/opdefs/sput_67.d +++ b/plugins/dalvik/v35/opdefs/sput_67.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput +@id 103 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sput_68.d b/plugins/dalvik/v35/opdefs/sput_68.d index 3709445..4009b2f 100644 --- a/plugins/dalvik/opdefs/sput_68.d +++ b/plugins/dalvik/v35/opdefs/sput_68.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput-wide +@id 104 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sput_69.d b/plugins/dalvik/v35/opdefs/sput_69.d index 89302eb..323a72e 100644 --- a/plugins/dalvik/opdefs/sput_69.d +++ b/plugins/dalvik/v35/opdefs/sput_69.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput-object +@id 105 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sput_6a.d b/plugins/dalvik/v35/opdefs/sput_6a.d index 91f5f4f..62a0aa6 100644 --- a/plugins/dalvik/opdefs/sput_6a.d +++ b/plugins/dalvik/v35/opdefs/sput_6a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput-boolean +@id 106 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sput_6b.d b/plugins/dalvik/v35/opdefs/sput_6b.d index 72338a0..104e75e 100644 --- a/plugins/dalvik/opdefs/sput_6b.d +++ b/plugins/dalvik/v35/opdefs/sput_6b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput-byte +@id 107 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sput_6c.d b/plugins/dalvik/v35/opdefs/sput_6c.d index 1f0a7c5..26814c5 100644 --- a/plugins/dalvik/opdefs/sput_6c.d +++ b/plugins/dalvik/v35/opdefs/sput_6c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput-char +@id 108 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sput_6d.d b/plugins/dalvik/v35/opdefs/sput_6d.d index d164858..ab9f6ee 100644 --- a/plugins/dalvik/opdefs/sput_6d.d +++ b/plugins/dalvik/v35/opdefs/sput_6d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sput-short +@id 109 + +@desc { + + Perform the identified object static field operation with the identified static field, loading or storing into the value register. + +<b>Note:</b> These opbs are reasonable candidates for static linking, altering the field argument to be a more direct offset. + +} + @encoding() { @format 21c | pool_field diff --git a/plugins/dalvik/opdefs/sub_91.d b/plugins/dalvik/v35/opdefs/sub_91.d index 34fd476..1c64a8e 100644 --- a/plugins/dalvik/opdefs/sub_91.d +++ b/plugins/dalvik/v35/opdefs/sub_91.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-int +@id 145 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/sub_9c.d b/plugins/dalvik/v35/opdefs/sub_9c.d index 566cb80..98c4032 100644 --- a/plugins/dalvik/opdefs/sub_9c.d +++ b/plugins/dalvik/v35/opdefs/sub_9c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-long +@id 156 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/sub_a7.d b/plugins/dalvik/v35/opdefs/sub_a7.d index 22851c6..eb148cd 100644 --- a/plugins/dalvik/opdefs/sub_a7.d +++ b/plugins/dalvik/v35/opdefs/sub_a7.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-float +@id 167 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/sub_ac.d b/plugins/dalvik/v35/opdefs/sub_ac.d index c818423..9af3ef9 100644 --- a/plugins/dalvik/opdefs/sub_ac.d +++ b/plugins/dalvik/v35/opdefs/sub_ac.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-double +@id 172 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/sub_b1.d b/plugins/dalvik/v35/opdefs/sub_b1.d index 4102367..a6edde2 100644 --- a/plugins/dalvik/opdefs/sub_b1.d +++ b/plugins/dalvik/v35/opdefs/sub_b1.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-int/2addr +@id 177 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/sub_bc.d b/plugins/dalvik/v35/opdefs/sub_bc.d index b0a22ae..62a7f80 100644 --- a/plugins/dalvik/opdefs/sub_bc.d +++ b/plugins/dalvik/v35/opdefs/sub_bc.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-long/2addr +@id 188 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/sub_c7.d b/plugins/dalvik/v35/opdefs/sub_c7.d index dc8fd47..072f960 100644 --- a/plugins/dalvik/opdefs/sub_c7.d +++ b/plugins/dalvik/v35/opdefs/sub_c7.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-float/2addr +@id 199 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/sub_cc.d b/plugins/dalvik/v35/opdefs/sub_cc.d index d24b702..6d68bf1 100644 --- a/plugins/dalvik/opdefs/sub_cc.d +++ b/plugins/dalvik/v35/opdefs/sub_cc.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title sub-double/2addr +@id 204 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/switch_2b.d b/plugins/dalvik/v35/opdefs/switch_2b.d index 2ff6b33..21111d7 100644 --- a/plugins/dalvik/opdefs/switch_2b.d +++ b/plugins/dalvik/v35/opdefs/switch_2b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title packed-switch +@id 43 + +@desc { + + Jump to a new instruction based on the value in the given register, using a table of offsets corresponding to each value in a particular integral range, or fall through to the next instruction if there is no match. + +} + @encoding() { @format 31t diff --git a/plugins/dalvik/opdefs/switch_2c.d b/plugins/dalvik/v35/opdefs/switch_2c.d index 0a4d248..66b6052 100644 --- a/plugins/dalvik/opdefs/switch_2c.d +++ b/plugins/dalvik/v35/opdefs/switch_2c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title sparse-switch +@id 44 + +@desc { + + Jump to a new instruction based on the value in the given register, using an ordered table of value-offset pairs, or fall through to the next instruction if there is no match. + +} + @encoding() { @format 31t diff --git a/plugins/dalvik/opdefs/throw_27.d b/plugins/dalvik/v35/opdefs/throw_27.d index 79c71dd..91c176f 100644 --- a/plugins/dalvik/opdefs/throw_27.d +++ b/plugins/dalvik/v35/opdefs/throw_27.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,13 +23,25 @@ @title throw +@id 39 + +@desc { + + Throw the indicated exception. + +} + @encoding() { @format 11x - @rules { + @syntax { + + @rules { + + call g_arch_instruction_set_flag(AIF_RETURN_POINT) - call SetInsFlag(AIF_RETURN_POINT) + } } diff --git a/plugins/dalvik/opdefs/to_81.d b/plugins/dalvik/v35/opdefs/to_81.d index e1b45b3..6e87d13 100644 --- a/plugins/dalvik/opdefs/to_81.d +++ b/plugins/dalvik/v35/opdefs/to_81.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title int-to-long +@id 129 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_82.d b/plugins/dalvik/v35/opdefs/to_82.d index 4d5e667..a0c2500 100644 --- a/plugins/dalvik/opdefs/to_82.d +++ b/plugins/dalvik/v35/opdefs/to_82.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title int-to-float +@id 130 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_83.d b/plugins/dalvik/v35/opdefs/to_83.d index 6f764c1..81931e4 100644 --- a/plugins/dalvik/opdefs/to_83.d +++ b/plugins/dalvik/v35/opdefs/to_83.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title int-to-double +@id 131 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_84.d b/plugins/dalvik/v35/opdefs/to_84.d index f3076ae..2694224 100644 --- a/plugins/dalvik/opdefs/to_84.d +++ b/plugins/dalvik/v35/opdefs/to_84.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title long-to-int +@id 132 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_85.d b/plugins/dalvik/v35/opdefs/to_85.d index 3ac252c..81a572b 100644 --- a/plugins/dalvik/opdefs/to_85.d +++ b/plugins/dalvik/v35/opdefs/to_85.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title long-to-float +@id 133 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_86.d b/plugins/dalvik/v35/opdefs/to_86.d index 80e9a28..34df6de 100644 --- a/plugins/dalvik/opdefs/to_86.d +++ b/plugins/dalvik/v35/opdefs/to_86.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title long-to-double +@id 134 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_87.d b/plugins/dalvik/v35/opdefs/to_87.d index 55028e3..06fb58f 100644 --- a/plugins/dalvik/opdefs/to_87.d +++ b/plugins/dalvik/v35/opdefs/to_87.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title float-to-int +@id 135 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_88.d b/plugins/dalvik/v35/opdefs/to_88.d index 2eaa85b..c0d2306 100644 --- a/plugins/dalvik/opdefs/to_88.d +++ b/plugins/dalvik/v35/opdefs/to_88.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title float-to-long +@id 136 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_89.d b/plugins/dalvik/v35/opdefs/to_89.d index 147f280..5f6a64c 100644 --- a/plugins/dalvik/opdefs/to_89.d +++ b/plugins/dalvik/v35/opdefs/to_89.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title float-to-double +@id 137 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_8a.d b/plugins/dalvik/v35/opdefs/to_8a.d index c089942..263c51d 100644 --- a/plugins/dalvik/opdefs/to_8a.d +++ b/plugins/dalvik/v35/opdefs/to_8a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title double-to-int +@id 138 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_8b.d b/plugins/dalvik/v35/opdefs/to_8b.d index e60ba2f..def5dc1 100644 --- a/plugins/dalvik/opdefs/to_8b.d +++ b/plugins/dalvik/v35/opdefs/to_8b.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title double-to-long +@id 139 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_8c.d b/plugins/dalvik/v35/opdefs/to_8c.d index b7ee496..4af8de3 100644 --- a/plugins/dalvik/opdefs/to_8c.d +++ b/plugins/dalvik/v35/opdefs/to_8c.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title double-to-float +@id 140 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_8d.d b/plugins/dalvik/v35/opdefs/to_8d.d index 28a194e..fb70951 100644 --- a/plugins/dalvik/opdefs/to_8d.d +++ b/plugins/dalvik/v35/opdefs/to_8d.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title int-to-byte +@id 141 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_8e.d b/plugins/dalvik/v35/opdefs/to_8e.d index c8b2598..bea9c71 100644 --- a/plugins/dalvik/opdefs/to_8e.d +++ b/plugins/dalvik/v35/opdefs/to_8e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title int-to-char +@id 142 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/to_8f.d b/plugins/dalvik/v35/opdefs/to_8f.d index 697c102..82e25d1 100644 --- a/plugins/dalvik/opdefs/to_8f.d +++ b/plugins/dalvik/v35/opdefs/to_8f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,14 @@ @title int-to-short +@id 143 + +@desc { + + Perform the identified unary operation on the source register, storing the result in the destination register. + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/add_90.d b/plugins/dalvik/v35/opdefs/unused_3e.d index 04168ab..2833fbb 100644 --- a/plugins/dalvik/opdefs/add_90.d +++ b/plugins/dalvik/v35/opdefs/unused_3e.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -21,10 +21,12 @@ */ -@title add-int +@title unused-3e + +@id 62 @encoding() { - @format 23x + @unused 10x } diff --git a/plugins/dalvik/opdefs/add_a6.d b/plugins/dalvik/v35/opdefs/unused_3f.d index 055358b..5f6a66d 100644 --- a/plugins/dalvik/opdefs/add_a6.d +++ b/plugins/dalvik/v35/opdefs/unused_3f.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -21,10 +21,12 @@ */ -@title add-float +@title unused-3f + +@id 63 @encoding() { - @format 23x + @unused 10x } diff --git a/plugins/dalvik/opdefs/add_9b.d b/plugins/dalvik/v35/opdefs/unused_40.d index fc40b13..3c93565 100644 --- a/plugins/dalvik/opdefs/add_9b.d +++ b/plugins/dalvik/v35/opdefs/unused_40.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -21,10 +21,12 @@ */ -@title add-long +@title unused-40 + +@id 64 @encoding() { - @format 23x + @unused 10x } diff --git a/plugins/dalvik/opdefs/add_ab.d b/plugins/dalvik/v35/opdefs/unused_41.d index 1506483..cad2943 100644 --- a/plugins/dalvik/opdefs/add_ab.d +++ b/plugins/dalvik/v35/opdefs/unused_41.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -21,10 +21,12 @@ */ -@title add-double +@title unused-41 + +@id 65 @encoding() { - @format 23x + @unused 10x } diff --git a/plugins/dalvik/v35/opdefs/unused_42.d b/plugins/dalvik/v35/opdefs/unused_42.d new file mode 100644 index 0000000..5e4b2c0 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_42.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-42 + +@id 66 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_43.d b/plugins/dalvik/v35/opdefs/unused_43.d new file mode 100644 index 0000000..c339cec --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_43.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-43 + +@id 67 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_73.d b/plugins/dalvik/v35/opdefs/unused_73.d new file mode 100644 index 0000000..09caa65 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_73.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-73 + +@id 115 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_79.d b/plugins/dalvik/v35/opdefs/unused_79.d new file mode 100644 index 0000000..063bbfb --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_79.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-79 + +@id 121 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_7a.d b/plugins/dalvik/v35/opdefs/unused_7a.d new file mode 100644 index 0000000..50f2d95 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_7a.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-7a + +@id 122 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e3.d b/plugins/dalvik/v35/opdefs/unused_e3.d new file mode 100644 index 0000000..e27f926 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e3.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e3 + +@id 227 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e4.d b/plugins/dalvik/v35/opdefs/unused_e4.d new file mode 100644 index 0000000..4c90e6a --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e4.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e4 + +@id 228 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e5.d b/plugins/dalvik/v35/opdefs/unused_e5.d new file mode 100644 index 0000000..e780c20 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e5.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e5 + +@id 229 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e6.d b/plugins/dalvik/v35/opdefs/unused_e6.d new file mode 100644 index 0000000..44d6e29 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e6.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e6 + +@id 230 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e7.d b/plugins/dalvik/v35/opdefs/unused_e7.d new file mode 100644 index 0000000..6d3fff7 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e7.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e7 + +@id 231 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e8.d b/plugins/dalvik/v35/opdefs/unused_e8.d new file mode 100644 index 0000000..f91c2e9 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e8.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e8 + +@id 232 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_e9.d b/plugins/dalvik/v35/opdefs/unused_e9.d new file mode 100644 index 0000000..6304670 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_e9.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-e9 + +@id 233 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_ea.d b/plugins/dalvik/v35/opdefs/unused_ea.d new file mode 100644 index 0000000..055a5e0 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_ea.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-ea + +@id 234 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_eb.d b/plugins/dalvik/v35/opdefs/unused_eb.d new file mode 100644 index 0000000..12cfd34 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_eb.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-eb + +@id 235 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_ec.d b/plugins/dalvik/v35/opdefs/unused_ec.d new file mode 100644 index 0000000..b00c7bf --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_ec.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-ec + +@id 236 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_ed.d b/plugins/dalvik/v35/opdefs/unused_ed.d new file mode 100644 index 0000000..94e7627 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_ed.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-ed + +@id 237 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_ee.d b/plugins/dalvik/v35/opdefs/unused_ee.d new file mode 100644 index 0000000..580cbe8 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_ee.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-ee + +@id 238 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_ef.d b/plugins/dalvik/v35/opdefs/unused_ef.d new file mode 100644 index 0000000..a04663b --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_ef.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-ef + +@id 239 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f0.d b/plugins/dalvik/v35/opdefs/unused_f0.d new file mode 100644 index 0000000..c238d44 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f0.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f0 + +@id 240 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f1.d b/plugins/dalvik/v35/opdefs/unused_f1.d new file mode 100644 index 0000000..405a792 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f1.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f1 + +@id 241 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f2.d b/plugins/dalvik/v35/opdefs/unused_f2.d new file mode 100644 index 0000000..58df50c --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f2.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f2 + +@id 242 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f3.d b/plugins/dalvik/v35/opdefs/unused_f3.d new file mode 100644 index 0000000..51280d7 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f3.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f3 + +@id 243 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f4.d b/plugins/dalvik/v35/opdefs/unused_f4.d new file mode 100644 index 0000000..015d988 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f4.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f4 + +@id 244 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f5.d b/plugins/dalvik/v35/opdefs/unused_f5.d new file mode 100644 index 0000000..63c6fd1 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f5.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f5 + +@id 245 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f6.d b/plugins/dalvik/v35/opdefs/unused_f6.d new file mode 100644 index 0000000..405c363 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f6.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f6 + +@id 246 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f7.d b/plugins/dalvik/v35/opdefs/unused_f7.d new file mode 100644 index 0000000..67ded78 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f7.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f7 + +@id 247 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f8.d b/plugins/dalvik/v35/opdefs/unused_f8.d new file mode 100644 index 0000000..aadd8a8 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f8.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f8 + +@id 248 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_f9.d b/plugins/dalvik/v35/opdefs/unused_f9.d new file mode 100644 index 0000000..84c8855 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_f9.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-f9 + +@id 249 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_fa.d b/plugins/dalvik/v35/opdefs/unused_fa.d new file mode 100644 index 0000000..66053c7 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_fa.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-fa + +@id 250 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_fb.d b/plugins/dalvik/v35/opdefs/unused_fb.d new file mode 100644 index 0000000..e0521e6 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_fb.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-fb + +@id 251 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_fc.d b/plugins/dalvik/v35/opdefs/unused_fc.d new file mode 100644 index 0000000..3b58e64 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_fc.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-fc + +@id 252 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_fd.d b/plugins/dalvik/v35/opdefs/unused_fd.d new file mode 100644 index 0000000..7c2a0f2 --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_fd.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-fd + +@id 253 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_fe.d b/plugins/dalvik/v35/opdefs/unused_fe.d new file mode 100644 index 0000000..e470bae --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_fe.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-fe + +@id 254 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/v35/opdefs/unused_ff.d b/plugins/dalvik/v35/opdefs/unused_ff.d new file mode 100644 index 0000000..ef0126d --- /dev/null +++ b/plugins/dalvik/v35/opdefs/unused_ff.d @@ -0,0 +1,32 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title unused-ff + +@id 255 + +@encoding() { + + @unused 10x + +} diff --git a/plugins/dalvik/opdefs/ushr_9a.d b/plugins/dalvik/v35/opdefs/ushr_9a.d index d3f48ba..234ad7b 100644 --- a/plugins/dalvik/opdefs/ushr_9a.d +++ b/plugins/dalvik/v35/opdefs/ushr_9a.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title ushr-int +@id 154 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/ushr_a5.d b/plugins/dalvik/v35/opdefs/ushr_a5.d index 11578c3..8ada091 100644 --- a/plugins/dalvik/opdefs/ushr_a5.d +++ b/plugins/dalvik/v35/opdefs/ushr_a5.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title ushr-long +@id 165 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/ushr_ba.d b/plugins/dalvik/v35/opdefs/ushr_ba.d index d9c0ab7..f5061e2 100644 --- a/plugins/dalvik/opdefs/ushr_ba.d +++ b/plugins/dalvik/v35/opdefs/ushr_ba.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title ushr-int/2addr +@id 186 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/ushr_c5.d b/plugins/dalvik/v35/opdefs/ushr_c5.d index b0117a7..322591b 100644 --- a/plugins/dalvik/opdefs/ushr_c5.d +++ b/plugins/dalvik/v35/opdefs/ushr_c5.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title ushr-long/2addr +@id 197 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/ushr_e2.d b/plugins/dalvik/v35/opdefs/ushr_e2.d index 5ade4f7..06fcdc7 100644 --- a/plugins/dalvik/opdefs/ushr_e2.d +++ b/plugins/dalvik/v35/opdefs/ushr_e2.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title ushr-int/lit8 +@id 226 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/dalvik/opdefs/xor_97.d b/plugins/dalvik/v35/opdefs/xor_97.d index 3bdfc05..c813a50 100644 --- a/plugins/dalvik/opdefs/xor_97.d +++ b/plugins/dalvik/v35/opdefs/xor_97.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title xor-int +@id 151 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/xor_a2.d b/plugins/dalvik/v35/opdefs/xor_a2.d index d651f66..045aa47 100644 --- a/plugins/dalvik/opdefs/xor_a2.d +++ b/plugins/dalvik/v35/opdefs/xor_a2.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title xor-long +@id 162 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the destination register. + +<b>Note:</b> Contrary to other <b>-long</b> mathematical operations (which take register pairs for both their first and their second source), <b>shl-long</b>, <b>shr-long</b>, and <b>ushr-long</b> take a register pair for their first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 23x diff --git a/plugins/dalvik/opdefs/xor_b7.d b/plugins/dalvik/v35/opdefs/xor_b7.d index b42da76..0425e1d 100644 --- a/plugins/dalvik/opdefs/xor_b7.d +++ b/plugins/dalvik/v35/opdefs/xor_b7.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title xor-int/2addr +@id 183 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/xor_c2.d b/plugins/dalvik/v35/opdefs/xor_c2.d index 3fd2660..76b6a05 100644 --- a/plugins/dalvik/opdefs/xor_c2.d +++ b/plugins/dalvik/v35/opdefs/xor_c2.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title xor-long/2addr +@id 194 + +@desc { + + Perform the identified binary operation on the two source registers, storing the result in the first source register. + +<b>Note:</b> Contrary to other <b>-long/2addr</b> mathematical operations (which take register pairs for both their destination/first source and their second source), <b>shl-long/2addr</b>, <b>shr-long/2addr</b>, and <b>ushr-long/2addr</b> take a register pair for their destination/first source (the value to be shifted), but a single register for their second source (the shifting distance). + +} + @encoding() { @format 12x diff --git a/plugins/dalvik/opdefs/xor_d7.d b/plugins/dalvik/v35/opdefs/xor_d7.d index 2351a21..5b2c637 100644 --- a/plugins/dalvik/opdefs/xor_d7.d +++ b/plugins/dalvik/v35/opdefs/xor_d7.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title xor-int/lit16 +@id 215 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> <b>rsub-int</b> does not have a suffix since this version is the main opb of its family. Also, see below for details on its semantics. + +} + @encoding() { @format 22s diff --git a/plugins/dalvik/opdefs/xor_df.d b/plugins/dalvik/v35/opdefs/xor_df.d index 04443f7..cd0d5d3 100644 --- a/plugins/dalvik/opdefs/xor_df.d +++ b/plugins/dalvik/v35/opdefs/xor_df.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions Dalvik * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,6 +23,16 @@ @title xor-int/lit8 +@id 223 + +@desc { + + Perform the indicated binary op on the indicated register (first argument) and literal value (second argument), storing the result in the destination register. + +<b>Note:</b> See below for details on the semantics of <b>rsub-int</b>. + +} + @encoding() { @format 22b diff --git a/plugins/arm/v7/opdefs/subs_B9320.d b/plugins/dalvik/v35/operand.h index 335e614..e2bc5e3 100644 --- a/plugins/arm/v7/opdefs/subs_B9320.d +++ b/plugins/dalvik/v35/operand.h @@ -1,8 +1,8 @@ /* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 + * operand.h - prototypes pour l'aide à la création d'opérandes Dalvik v35 * - * Copyright (C) 2014 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -21,24 +21,17 @@ */ -@title SUBS PC, LR and related instructions (ARM) +#ifndef _PLUGINS_DALVIK_V35_OPERAND_H +#define _PLUGINS_DALVIK_V35_OPERAND_H -@encoding(A1) { - @word cond(4) 0 0 1 opcode(4) 1 Rn(4) 1 1 1 1 imm12(12) +#include "../operand.h" - @syntax {c} <Rn> <#const> - @conv { - c = Condition(cond) - Rn = Register(Rn) - const = ExpandImmC32(imm12) +/* Procède à la lecture d'opérandes pour une instruction. */ +#define dalvik35_read_operands dalvik_read_operands - } - @rules { - } - -} +#endif /* _PLUGINS_DALVIK_V35_OPERAND_H */ diff --git a/plugins/dalvik/v35/processor.c b/plugins/dalvik/v35/processor.c new file mode 100644 index 0000000..17d447a --- /dev/null +++ b/plugins/dalvik/v35/processor.c @@ -0,0 +1,494 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * processor.c - manipulation du processeur de la VM Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "processor.h" + + +#include <assert.h> + + +#include "instruction.h" +#include "opcodes/identifiers.h" +#include "opcodes/opcodes.h" +#include "../processor-int.h" +#include "../pseudo/fill.h" +#include "../pseudo/switch.h" + + + +/* Définition du processeur de la VM Dalvik v35 (instance) */ +struct _GDalvik35Processor +{ + GDalvikProcessor parent; /* Instance parente */ + +}; + + +/* Définition du processeur de la VM Dalvik v35 (classe) */ +struct _GDalvik35ProcessorClass +{ + GDalvikProcessorClass parent; /* Classe parente */ + +}; + + +/* Initialise la classe des processeurs de VM Dalvik v35. */ +static void g_dalvik35_processor_class_init(GDalvik35ProcessorClass *); + +/* Initialise une instance de processeur de VM Dalvik v35. */ +static void g_dalvik35_processor_init(GDalvik35Processor *); + +/* Supprime toutes les références externes. */ +static void g_dalvik35_processor_dispose(GDalvik35Processor *); + +/* Procède à la libération totale de la mémoire. */ +static void g_dalvik35_processor_finalize(GDalvik35Processor *); + +/* Décode une instruction dans un flux de données. */ +static GArchInstruction *g_dalvik35_processor_disassemble(const GArchProcessor *, GDalvikContext *, const GBinContent *, vmpa2t *, GExeFormat *); + + + +/* Indique le type défini par la GLib pour le processeur Dalvik v35. */ +G_DEFINE_TYPE(GDalvik35Processor, g_dalvik35_processor, G_TYPE_DALVIK_PROCESSOR); + + +/****************************************************************************** +* * +* Paramètres : klass = classe à initialiser. * +* * +* Description : Initialise la classe des processeurs de VM Dalvik v35. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_processor_class_init(GDalvik35ProcessorClass *klass) +{ + GObjectClass *object; /* Autre version de la classe */ + GArchProcessorClass *proc; /* Encore une autre vision... */ + + object = G_OBJECT_CLASS(klass); + + object->dispose = (GObjectFinalizeFunc/* ! */)g_dalvik35_processor_dispose; + object->finalize = (GObjectFinalizeFunc)g_dalvik35_processor_finalize; + + proc = G_ARCH_PROCESSOR_CLASS(klass); + + proc->disassemble = (disass_instr_fc)g_dalvik35_processor_disassemble; + +} + + +/****************************************************************************** +* * +* Paramètres : proc = instance à initialiser. * +* * +* Description : Initialise une instance de processeur de VM Dalvik v35. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_processor_init(GDalvik35Processor *proc) +{ + +} + + +/****************************************************************************** +* * +* Paramètres : proc = instance d'objet GLib à traiter. * +* * +* Description : Supprime toutes les références externes. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_processor_dispose(GDalvik35Processor *proc) +{ + G_OBJECT_CLASS(g_dalvik35_processor_parent_class)->dispose(G_OBJECT(proc)); + +} + + +/****************************************************************************** +* * +* Paramètres : bookmark = instance d'objet GLib à traiter. * +* * +* Description : Procède à la libération totale de la mémoire. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void g_dalvik35_processor_finalize(GDalvik35Processor *proc) +{ + G_OBJECT_CLASS(g_dalvik35_processor_parent_class)->finalize(G_OBJECT(proc)); + +} + + +/****************************************************************************** +* * +* Paramètres : - * +* * +* Description : Crée le support de l'architecture Dalvik v35. * +* * +* Retour : Architecture mise en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +GArchProcessor *g_dalvik35_processor_new(void) +{ + GArchProcessor *result; /* Structure à retourner */ + + result = g_object_new(G_TYPE_DALVIK_PROCESSOR, NULL); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : proc = architecture visée par la procédure. * +* ctx = contexte lié à l'exécution du processeur. * +* content = flux de données à analyser. * +* pos = position courante dans ce flux. [OUT] * +* format = format du fichier contenant le code. * +* * +* Description : Désassemble une instruction dans un flux de données. * +* * +* Retour : Instruction mise en place ou NULL en cas d'échec. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static GArchInstruction *g_dalvik35_processor_disassemble(const GArchProcessor *proc, GDalvikContext *ctx, const GBinContent *content, vmpa2t *pos, GExeFormat *format) +{ + GArchInstruction *result; /* Instruction à renvoyer */ + uint8_t raw8; /* Donnée de 8 bits à analyser */ + Dalvik35Opcodes id; /* Identifiant d'instruction */ + + static const disass_instr_fc decodings[DOP35_COUNT] = { + + [DOP35_NOP] = dalvik35_read_instr_nop, + [DOP35_MOVE] = dalvik35_read_instr_move, + [DOP35_MOVE_FROM16] = dalvik35_read_instr_move_from16, + [DOP35_MOVE_16] = dalvik35_read_instr_move_16, + [DOP35_MOVE_WIDE] = dalvik35_read_instr_move_wide, + [DOP35_MOVE_WIDE_FROM16] = dalvik35_read_instr_move_wide_from16, + [DOP35_MOVE_WIDE_16] = dalvik35_read_instr_move_wide_16, + [DOP35_MOVE_OBJECT] = dalvik35_read_instr_move_object, + [DOP35_MOVE_OBJECT_FROM16] = dalvik35_read_instr_move_object_from16, + [DOP35_MOVE_OBJECT_16] = dalvik35_read_instr_move_object_16, + [DOP35_MOVE_RESULT] = dalvik35_read_instr_move_result, + [DOP35_MOVE_RESULT_WIDE] = dalvik35_read_instr_move_result_wide, + [DOP35_MOVE_RESULT_OBJECT] = dalvik35_read_instr_move_result_object, + [DOP35_MOVE_EXCEPTION] = dalvik35_read_instr_move_exception, + [DOP35_RETURN_VOID] = dalvik35_read_instr_return_void, + [DOP35_RETURN] = dalvik35_read_instr_return, + [DOP35_RETURN_WIDE] = dalvik35_read_instr_return_wide, + [DOP35_RETURN_OBJECT] = dalvik35_read_instr_return_object, + [DOP35_CONST_4] = dalvik35_read_instr_const_4, + [DOP35_CONST_16] = dalvik35_read_instr_const_16, + [DOP35_CONST] = dalvik35_read_instr_const, + [DOP35_CONST_HIGH16] = dalvik35_read_instr_const_high16, + [DOP35_CONST_WIDE_16] = dalvik35_read_instr_const_wide_16, + [DOP35_CONST_WIDE_32] = dalvik35_read_instr_const_wide_32, + [DOP35_CONST_WIDE] = dalvik35_read_instr_const_wide, + [DOP35_CONST_WIDE_HIGH16] = dalvik35_read_instr_const_wide_high16, + [DOP35_CONST_STRING] = dalvik35_read_instr_const_string, + [DOP35_CONST_STRING_JUMBO] = dalvik35_read_instr_const_string_jumbo, + [DOP35_CONST_CLASS] = dalvik35_read_instr_const_class, + [DOP35_MONITOR_ENTER] = dalvik35_read_instr_monitor_enter, + [DOP35_MONITOR_EXIT] = dalvik35_read_instr_monitor_exit, + [DOP35_CHECK_CAST] = dalvik35_read_instr_check_cast, + [DOP35_INSTANCE_OF] = dalvik35_read_instr_instance_of, + [DOP35_ARRAY_LENGTH] = dalvik35_read_instr_array_length, + [DOP35_NEW_INSTANCE] = dalvik35_read_instr_new_instance, + [DOP35_NEW_ARRAY] = dalvik35_read_instr_new_array, + [DOP35_FILLED_NEW_ARRAY] = dalvik35_read_instr_filled_new_array, + [DOP35_FILLED_NEW_ARRAY_RANGE] = dalvik35_read_instr_filled_new_array_range, + [DOP35_FILL_ARRAY_DATA] = dalvik35_read_instr_fill_array_data, + [DOP35_THROW] = dalvik35_read_instr_throw, + [DOP35_GOTO] = dalvik35_read_instr_goto, + [DOP35_GOTO_16] = dalvik35_read_instr_goto_16, + [DOP35_GOTO_32] = dalvik35_read_instr_goto_32, + [DOP35_PACKED_SWITCH] = dalvik35_read_instr_packed_switch, + [DOP35_SPARSE_SWITCH] = dalvik35_read_instr_sparse_switch, + [DOP35_CMPL_FLOAT] = dalvik35_read_instr_cmpl_float, + [DOP35_CMPG_FLOAT] = dalvik35_read_instr_cmpg_float, + [DOP35_CMPL_DOUBLE] = dalvik35_read_instr_cmpl_double, + [DOP35_CMPG_DOUBLE] = dalvik35_read_instr_cmpg_double, + [DOP35_CMP_LONG] = dalvik35_read_instr_cmp_long, + [DOP35_IF_EQ] = dalvik35_read_instr_if_eq, + [DOP35_IF_NE] = dalvik35_read_instr_if_ne, + [DOP35_IF_LT] = dalvik35_read_instr_if_lt, + [DOP35_IF_GE] = dalvik35_read_instr_if_ge, + [DOP35_IF_GT] = dalvik35_read_instr_if_gt, + [DOP35_IF_LE] = dalvik35_read_instr_if_le, + [DOP35_IF_EQZ] = dalvik35_read_instr_if_eqz, + [DOP35_IF_NEZ] = dalvik35_read_instr_if_nez, + [DOP35_IF_LTZ] = dalvik35_read_instr_if_ltz, + [DOP35_IF_GEZ] = dalvik35_read_instr_if_gez, + [DOP35_IF_GTZ] = dalvik35_read_instr_if_gtz, + [DOP35_IF_LEZ] = dalvik35_read_instr_if_lez, + [DOP35_UNUSED_3E] = dalvik35_read_instr_unused_3e, + [DOP35_UNUSED_3F] = dalvik35_read_instr_unused_3f, + [DOP35_UNUSED_40] = dalvik35_read_instr_unused_40, + [DOP35_UNUSED_41] = dalvik35_read_instr_unused_41, + [DOP35_UNUSED_42] = dalvik35_read_instr_unused_42, + [DOP35_UNUSED_43] = dalvik35_read_instr_unused_43, + [DOP35_AGET] = dalvik35_read_instr_aget, + [DOP35_AGET_WIDE] = dalvik35_read_instr_aget_wide, + [DOP35_AGET_OBJECT] = dalvik35_read_instr_aget_object, + [DOP35_AGET_BOOLEAN] = dalvik35_read_instr_aget_boolean, + [DOP35_AGET_BYTE] = dalvik35_read_instr_aget_byte, + [DOP35_AGET_CHAR] = dalvik35_read_instr_aget_char, + [DOP35_AGET_SHORT] = dalvik35_read_instr_aget_short, + [DOP35_APUT] = dalvik35_read_instr_aput, + [DOP35_APUT_WIDE] = dalvik35_read_instr_aput_wide, + [DOP35_APUT_OBJECT] = dalvik35_read_instr_aput_object, + [DOP35_APUT_BOOLEAN] = dalvik35_read_instr_aput_boolean, + [DOP35_APUT_BYTE] = dalvik35_read_instr_aput_byte, + [DOP35_APUT_CHAR] = dalvik35_read_instr_aput_char, + [DOP35_APUT_SHORT] = dalvik35_read_instr_aput_short, + [DOP35_IGET] = dalvik35_read_instr_iget, + [DOP35_IGET_WIDE] = dalvik35_read_instr_iget_wide, + [DOP35_IGET_OBJECT] = dalvik35_read_instr_iget_object, + [DOP35_IGET_BOOLEAN] = dalvik35_read_instr_iget_boolean, + [DOP35_IGET_BYTE] = dalvik35_read_instr_iget_byte, + [DOP35_IGET_CHAR] = dalvik35_read_instr_iget_char, + [DOP35_IGET_SHORT] = dalvik35_read_instr_iget_short, + [DOP35_IPUT] = dalvik35_read_instr_iput, + [DOP35_IPUT_WIDE] = dalvik35_read_instr_iput_wide, + [DOP35_IPUT_OBJECT] = dalvik35_read_instr_iput_object, + [DOP35_IPUT_BOOLEAN] = dalvik35_read_instr_iput_boolean, + [DOP35_IPUT_BYTE] = dalvik35_read_instr_iput_byte, + [DOP35_IPUT_CHAR] = dalvik35_read_instr_iput_char, + [DOP35_IPUT_SHORT] = dalvik35_read_instr_iput_short, + [DOP35_SGET] = dalvik35_read_instr_sget, + [DOP35_SGET_WIDE] = dalvik35_read_instr_sget_wide, + [DOP35_SGET_OBJECT] = dalvik35_read_instr_sget_object, + [DOP35_SGET_BOOLEAN] = dalvik35_read_instr_sget_boolean, + [DOP35_SGET_BYTE] = dalvik35_read_instr_sget_byte, + [DOP35_SGET_CHAR] = dalvik35_read_instr_sget_char, + [DOP35_SGET_SHORT] = dalvik35_read_instr_sget_short, + [DOP35_SPUT] = dalvik35_read_instr_sput, + [DOP35_SPUT_WIDE] = dalvik35_read_instr_sput_wide, + [DOP35_SPUT_OBJECT] = dalvik35_read_instr_sput_object, + [DOP35_SPUT_BOOLEAN] = dalvik35_read_instr_sput_boolean, + [DOP35_SPUT_BYTE] = dalvik35_read_instr_sput_byte, + [DOP35_SPUT_CHAR] = dalvik35_read_instr_sput_char, + [DOP35_SPUT_SHORT] = dalvik35_read_instr_sput_short, + [DOP35_INVOKE_VIRTUAL] = dalvik35_read_instr_invoke_virtual, + [DOP35_INVOKE_SUPER] = dalvik35_read_instr_invoke_super, + [DOP35_INVOKE_DIRECT] = dalvik35_read_instr_invoke_direct, + [DOP35_INVOKE_STATIC] = dalvik35_read_instr_invoke_static, + [DOP35_INVOKE_INTERFACE] = dalvik35_read_instr_invoke_interface, + [DOP35_UNUSED_73] = dalvik35_read_instr_unused_73, + [DOP35_INVOKE_VIRTUAL_RANGE] = dalvik35_read_instr_invoke_virtual_range, + [DOP35_INVOKE_SUPER_RANGE] = dalvik35_read_instr_invoke_super_range, + [DOP35_INVOKE_DIRECT_RANGE] = dalvik35_read_instr_invoke_direct_range, + [DOP35_INVOKE_STATIC_RANGE] = dalvik35_read_instr_invoke_static_range, + [DOP35_INVOKE_INTERFACE_RANGE] = dalvik35_read_instr_invoke_interface_range, + [DOP35_UNUSED_79] = dalvik35_read_instr_unused_79, + [DOP35_UNUSED_7A] = dalvik35_read_instr_unused_7a, + [DOP35_NEG_INT] = dalvik35_read_instr_neg_int, + [DOP35_NOT_INT] = dalvik35_read_instr_not_int, + [DOP35_NEG_LONG] = dalvik35_read_instr_neg_long, + [DOP35_NOT_LONG] = dalvik35_read_instr_not_long, + [DOP35_NEG_FLOAT] = dalvik35_read_instr_neg_float, + [DOP35_NEG_DOUBLE] = dalvik35_read_instr_neg_double, + [DOP35_INT_TO_LONG] = dalvik35_read_instr_int_to_long, + [DOP35_INT_TO_FLOAT] = dalvik35_read_instr_int_to_float, + [DOP35_INT_TO_DOUBLE] = dalvik35_read_instr_int_to_double, + [DOP35_LONG_TO_INT] = dalvik35_read_instr_long_to_int, + [DOP35_LONG_TO_FLOAT] = dalvik35_read_instr_long_to_float, + [DOP35_LONG_TO_DOUBLE] = dalvik35_read_instr_long_to_double, + [DOP35_FLOAT_TO_INT] = dalvik35_read_instr_float_to_int, + [DOP35_FLOAT_TO_LONG] = dalvik35_read_instr_float_to_long, + [DOP35_FLOAT_TO_DOUBLE] = dalvik35_read_instr_float_to_double, + [DOP35_DOUBLE_TO_INT] = dalvik35_read_instr_double_to_int, + [DOP35_DOUBLE_TO_LONG] = dalvik35_read_instr_double_to_long, + [DOP35_DOUBLE_TO_FLOAT] = dalvik35_read_instr_double_to_float, + [DOP35_INT_TO_BYTE] = dalvik35_read_instr_int_to_byte, + [DOP35_INT_TO_CHAR] = dalvik35_read_instr_int_to_char, + [DOP35_INT_TO_SHORT] = dalvik35_read_instr_int_to_short, + [DOP35_ADD_INT] = dalvik35_read_instr_add_int, + [DOP35_SUB_INT] = dalvik35_read_instr_sub_int, + [DOP35_MUL_INT] = dalvik35_read_instr_mul_int, + [DOP35_DIV_INT] = dalvik35_read_instr_div_int, + [DOP35_REM_INT] = dalvik35_read_instr_rem_int, + [DOP35_AND_INT] = dalvik35_read_instr_and_int, + [DOP35_OR_INT] = dalvik35_read_instr_or_int, + [DOP35_XOR_INT] = dalvik35_read_instr_xor_int, + [DOP35_SHL_INT] = dalvik35_read_instr_shl_int, + [DOP35_SHR_INT] = dalvik35_read_instr_shr_int, + [DOP35_USHR_INT] = dalvik35_read_instr_ushr_int, + [DOP35_ADD_LONG] = dalvik35_read_instr_add_long, + [DOP35_SUB_LONG] = dalvik35_read_instr_sub_long, + [DOP35_MUL_LONG] = dalvik35_read_instr_mul_long, + [DOP35_DIV_LONG] = dalvik35_read_instr_div_long, + [DOP35_REM_LONG] = dalvik35_read_instr_rem_long, + [DOP35_AND_LONG] = dalvik35_read_instr_and_long, + [DOP35_OR_LONG] = dalvik35_read_instr_or_long, + [DOP35_XOR_LONG] = dalvik35_read_instr_xor_long, + [DOP35_SHL_LONG] = dalvik35_read_instr_shl_long, + [DOP35_SHR_LONG] = dalvik35_read_instr_shr_long, + [DOP35_USHR_LONG] = dalvik35_read_instr_ushr_long, + [DOP35_ADD_FLOAT] = dalvik35_read_instr_add_float, + [DOP35_SUB_FLOAT] = dalvik35_read_instr_sub_float, + [DOP35_MUL_FLOAT] = dalvik35_read_instr_mul_float, + [DOP35_DIV_FLOAT] = dalvik35_read_instr_div_float, + [DOP35_REM_FLOAT] = dalvik35_read_instr_rem_float, + [DOP35_ADD_DOUBLE] = dalvik35_read_instr_add_double, + [DOP35_SUB_DOUBLE] = dalvik35_read_instr_sub_double, + [DOP35_MUL_DOUBLE] = dalvik35_read_instr_mul_double, + [DOP35_DIV_DOUBLE] = dalvik35_read_instr_div_double, + [DOP35_REM_DOUBLE] = dalvik35_read_instr_rem_double, + [DOP35_ADD_INT_2ADDR] = dalvik35_read_instr_add_int_2addr, + [DOP35_SUB_INT_2ADDR] = dalvik35_read_instr_sub_int_2addr, + [DOP35_MUL_INT_2ADDR] = dalvik35_read_instr_mul_int_2addr, + [DOP35_DIV_INT_2ADDR] = dalvik35_read_instr_div_int_2addr, + [DOP35_REM_INT_2ADDR] = dalvik35_read_instr_rem_int_2addr, + [DOP35_AND_INT_2ADDR] = dalvik35_read_instr_and_int_2addr, + [DOP35_OR_INT_2ADDR] = dalvik35_read_instr_or_int_2addr, + [DOP35_XOR_INT_2ADDR] = dalvik35_read_instr_xor_int_2addr, + [DOP35_SHL_INT_2ADDR] = dalvik35_read_instr_shl_int_2addr, + [DOP35_SHR_INT_2ADDR] = dalvik35_read_instr_shr_int_2addr, + [DOP35_USHR_INT_2ADDR] = dalvik35_read_instr_ushr_int_2addr, + [DOP35_ADD_LONG_2ADDR] = dalvik35_read_instr_add_long_2addr, + [DOP35_SUB_LONG_2ADDR] = dalvik35_read_instr_sub_long_2addr, + [DOP35_MUL_LONG_2ADDR] = dalvik35_read_instr_mul_long_2addr, + [DOP35_DIV_LONG_2ADDR] = dalvik35_read_instr_div_long_2addr, + [DOP35_REM_LONG_2ADDR] = dalvik35_read_instr_rem_long_2addr, + [DOP35_AND_LONG_2ADDR] = dalvik35_read_instr_and_long_2addr, + [DOP35_OR_LONG_2ADDR] = dalvik35_read_instr_or_long_2addr, + [DOP35_XOR_LONG_2ADDR] = dalvik35_read_instr_xor_long_2addr, + [DOP35_SHL_LONG_2ADDR] = dalvik35_read_instr_shl_long_2addr, + [DOP35_SHR_LONG_2ADDR] = dalvik35_read_instr_shr_long_2addr, + [DOP35_USHR_LONG_2ADDR] = dalvik35_read_instr_ushr_long_2addr, + [DOP35_ADD_FLOAT_2ADDR] = dalvik35_read_instr_add_float_2addr, + [DOP35_SUB_FLOAT_2ADDR] = dalvik35_read_instr_sub_float_2addr, + [DOP35_MUL_FLOAT_2ADDR] = dalvik35_read_instr_mul_float_2addr, + [DOP35_DIV_FLOAT_2ADDR] = dalvik35_read_instr_div_float_2addr, + [DOP35_REM_FLOAT_2ADDR] = dalvik35_read_instr_rem_float_2addr, + [DOP35_ADD_DOUBLE_2ADDR] = dalvik35_read_instr_add_double_2addr, + [DOP35_SUB_DOUBLE_2ADDR] = dalvik35_read_instr_sub_double_2addr, + [DOP35_MUL_DOUBLE_2ADDR] = dalvik35_read_instr_mul_double_2addr, + [DOP35_DIV_DOUBLE_2ADDR] = dalvik35_read_instr_div_double_2addr, + [DOP35_REM_DOUBLE_2ADDR] = dalvik35_read_instr_rem_double_2addr, + [DOP35_ADD_INT_LIT16] = dalvik35_read_instr_add_int_lit16, + [DOP35_RSUB_INT] = dalvik35_read_instr_rsub_int, + [DOP35_MUL_INT_LIT16] = dalvik35_read_instr_mul_int_lit16, + [DOP35_DIV_INT_LIT16] = dalvik35_read_instr_div_int_lit16, + [DOP35_REM_INT_LIT16] = dalvik35_read_instr_rem_int_lit16, + [DOP35_AND_INT_LIT16] = dalvik35_read_instr_and_int_lit16, + [DOP35_OR_INT_LIT16] = dalvik35_read_instr_or_int_lit16, + [DOP35_XOR_INT_LIT16] = dalvik35_read_instr_xor_int_lit16, + [DOP35_ADD_INT_LIT8] = dalvik35_read_instr_add_int_lit8, + [DOP35_RSUB_INT_LIT8] = dalvik35_read_instr_rsub_int_lit8, + [DOP35_MUL_INT_LIT8] = dalvik35_read_instr_mul_int_lit8, + [DOP35_DIV_INT_LIT8] = dalvik35_read_instr_div_int_lit8, + [DOP35_REM_INT_LIT8] = dalvik35_read_instr_rem_int_lit8, + [DOP35_AND_INT_LIT8] = dalvik35_read_instr_and_int_lit8, + [DOP35_OR_INT_LIT8] = dalvik35_read_instr_or_int_lit8, + [DOP35_XOR_INT_LIT8] = dalvik35_read_instr_xor_int_lit8, + [DOP35_SHL_INT_LIT8] = dalvik35_read_instr_shl_int_lit8, + [DOP35_SHR_INT_LIT8] = dalvik35_read_instr_shr_int_lit8, + [DOP35_USHR_INT_LIT8] = dalvik35_read_instr_ushr_int_lit8, + [DOP35_UNUSED_E3] = dalvik35_read_instr_unused_e3, + [DOP35_UNUSED_E4] = dalvik35_read_instr_unused_e4, + [DOP35_UNUSED_E5] = dalvik35_read_instr_unused_e5, + [DOP35_UNUSED_E6] = dalvik35_read_instr_unused_e6, + [DOP35_UNUSED_E7] = dalvik35_read_instr_unused_e7, + [DOP35_UNUSED_E8] = dalvik35_read_instr_unused_e8, + [DOP35_UNUSED_E9] = dalvik35_read_instr_unused_e9, + [DOP35_UNUSED_EA] = dalvik35_read_instr_unused_ea, + [DOP35_UNUSED_EB] = dalvik35_read_instr_unused_eb, + [DOP35_UNUSED_EC] = dalvik35_read_instr_unused_ec, + [DOP35_UNUSED_ED] = dalvik35_read_instr_unused_ed, + [DOP35_UNUSED_EE] = dalvik35_read_instr_unused_ee, + [DOP35_UNUSED_EF] = dalvik35_read_instr_unused_ef, + [DOP35_UNUSED_F0] = dalvik35_read_instr_unused_f0, + [DOP35_UNUSED_F1] = dalvik35_read_instr_unused_f1, + [DOP35_UNUSED_F2] = dalvik35_read_instr_unused_f2, + [DOP35_UNUSED_F3] = dalvik35_read_instr_unused_f3, + [DOP35_UNUSED_F4] = dalvik35_read_instr_unused_f4, + [DOP35_UNUSED_F5] = dalvik35_read_instr_unused_f5, + [DOP35_UNUSED_F6] = dalvik35_read_instr_unused_f6, + [DOP35_UNUSED_F7] = dalvik35_read_instr_unused_f7, + [DOP35_UNUSED_F8] = dalvik35_read_instr_unused_f8, + [DOP35_UNUSED_F9] = dalvik35_read_instr_unused_f9, + [DOP35_UNUSED_FA] = dalvik35_read_instr_unused_fa, + [DOP35_UNUSED_FB] = dalvik35_read_instr_unused_fb, + [DOP35_UNUSED_FC] = dalvik35_read_instr_unused_fc, + [DOP35_UNUSED_FD] = dalvik35_read_instr_unused_fd, + [DOP35_UNUSED_FE] = dalvik35_read_instr_unused_fe, + [DOP35_UNUSED_FF] = dalvik35_read_instr_unused_ff, + + }; + + /* Données brutes associées à une instruction ? */ + + result = g_dalvik_context_get_raw_data(ctx, content, pos); + + if (result != NULL) goto gdpd_done; + + /* Pseudo-instruction... */ + + if (!g_binary_content_read_u8(content, pos, &raw8)) + return NULL; + + result = g_dalvik_processor_disassemble_pseudo(proc, ctx, content, pos, raw8); + + if (result != NULL) goto gdpd_done; + + /* ... ou instruction classique */ + + assert(raw8 < DOP35_COUNT); + + id = (Dalvik35Opcodes)raw8; + + result = decodings[id](proc, G_PROC_CONTEXT(ctx), content, pos, format); + + gdpd_done: + + return result; + +} diff --git a/plugins/dalvik/v35/processor.h b/plugins/dalvik/v35/processor.h new file mode 100644 index 0000000..c7930de --- /dev/null +++ b/plugins/dalvik/v35/processor.h @@ -0,0 +1,55 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * processor.h - prototypes pour la manipulation du processeur de la VM Dalvik + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _PLUGINS_DALVIK_V35_PROCESSOR_H +#define _PLUGINS_DALVIK_V35_PROCESSOR_H + + +#include <arch/processor.h> + + + +#define G_TYPE_DALVIK35_PROCESSOR g_dalvik35_processor_get_type() +#define G_DALVIK35_PROCESSOR(obj) (G_TYPE_CHECK_INSTANCE_CAST((obj), G_TYPE_DALVIK35_PROCESSOR, GDalvik35Processor)) +#define G_IS_DALVIK35_PROCESSOR(obj) (G_TYPE_CHECK_INSTANCE_TYPE((obj), G_TYPE_DALVIK35_PROCESSOR)) +#define G_DALVIK35_PROCESSOR_CLASS(klass) (G_TYPE_CHECK_CLASS_CAST((klass), G_TYPE_DALVIK35_PROCESSOR, GDalvik35ProcessorClass)) +#define G_IS_DALVIK35_PROCESSOR_CLASS(klass) (G_TYPE_CHECK_CLASS_TYPE((klass), G_TYPE_DALVIK35_PROCESSOR)) +#define G_DALVIK35_PROCESSOR_GET_CLASS(obj) (G_TYPE_INSTANCE_GET_CLASS((obj), G_TYPE_DALVIK35_PROCESSOR, GDalvik35ProcessorClass)) + + +/* Définition du processeur de la VM Dalvik v35 (instance) */ +typedef struct _GDalvik35Processor GDalvik35Processor; + +/* Définition du processeur de la VM Dalvik v35 (classe) */ +typedef struct _GDalvik35ProcessorClass GDalvik35ProcessorClass; + + +/* Indique le type défini par la GLib pour le processeur Dalvik v35. */ +GType g_dalvik35_processor_get_type(void); + +/* Crée le support de l'architecture Dalvik v35. */ +GArchProcessor *g_dalvik35_processor_new(void); + + + +#endif /* _PLUGINS_DALVIK_V35_PROCESSOR_H */ diff --git a/plugins/dex/dex-int.c b/plugins/dex/dex-int.c index 3f3eccb..3a69bb2 100644 --- a/plugins/dex/dex-int.c +++ b/plugins/dex/dex-int.c @@ -32,7 +32,7 @@ #include <common/endianness.h> -#include <plugins/dalvik/instruction-def.h> +#include <plugins/dalvik/pseudo/identifiers.h> diff --git a/plugins/dex/format.c b/plugins/dex/format.c index fc49a15..44e9c0a 100755 --- a/plugins/dex/format.c +++ b/plugins/dex/format.c @@ -336,7 +336,7 @@ static SourceEndian g_dex_format_get_endianness(const GDexFormat *format) static const char *g_dex_format_get_target_machine(const GDexFormat *format) { - return "dalvik"; + return "dalvik35"; } diff --git a/src/arch/instruction-int.h b/src/arch/instruction-int.h index 081adba..782c827 100644 --- a/src/arch/instruction-int.h +++ b/src/arch/instruction-int.h @@ -40,6 +40,9 @@ typedef const char * (* get_instruction_keyword_fc) (GArchInstruction *, AsmSynt /* Construit un petit résumé concis de l'instruction. */ typedef char * (* build_instruction_tooltip_fc) (const GArchInstruction *); +/* Fournit une description pour l'instruction manipulée. */ +typedef const char * (* get_instruction_desc_fc) (const GArchInstruction *); + /* Ajoute à un tampon GLib le contenu de l'instance spécifiée. */ typedef GBufferLine * (* print_instruction_fc) (const GArchInstruction *, GBufferLine *, size_t, size_t, const GBinContent *); @@ -82,6 +85,8 @@ struct _GArchInstruction flat_array_t *from; /* Origines des références */ flat_array_t *to; /* Instructions visées */ + itid_t uid; /* Identifiant unique du type */ + ArchInstrFlag flags; /* Informations complémentaires*/ }; @@ -95,6 +100,7 @@ struct _GArchInstructionClass get_instruction_encoding_fc get_encoding; /* Obtention de l'encodage */ get_instruction_keyword_fc get_keyword; /* Texte humain équivalent */ build_instruction_tooltip_fc build_tooltip; /* Construction d'une bulle*/ + get_instruction_desc_fc get_desc; /* Description assez complète */ print_instruction_fc print; /* Imprime l'ensemble */ @@ -103,5 +109,13 @@ struct _GArchInstructionClass }; +/** + * Fournit une marge pour toutes les instructions particulières communes + * à l'ensemble des architectures (GRawInstruction, GUndefInstruction). + */ + +#define INSTR_TYPE_ID_OFFSET 5 + + #endif /* _ARCH_INSTRUCTION_INT_H */ diff --git a/src/arch/instruction.c b/src/arch/instruction.c index 0041129..9c0a47c 100644 --- a/src/arch/instruction.c +++ b/src/arch/instruction.c @@ -1089,6 +1089,30 @@ char *g_arch_instruction_build_tooltip(const GArchInstruction *instr) } +/****************************************************************************** +* * +* Paramètres : instr = instruction d'assemblage à consulter. * +* * +* Description : Fournit une description pour l'instruction manipulée. * +* * +* Retour : Chaîne de caractères avec balises éventuelles. * +* * +* Remarques : - * +* * +******************************************************************************/ + +const char *g_arch_instruction_get_description(const GArchInstruction *instr) +{ + const char *result; /* Description à retourner */ + + result = G_ARCH_INSTRUCTION_GET_CLASS(instr)->get_desc(instr); + + return result; + +} + + + /* ---------------------------------------------------------------------------------- */ /* OFFRE DE CAPACITES DE GENERATION */ /* ---------------------------------------------------------------------------------- */ diff --git a/src/arch/instruction.h b/src/arch/instruction.h index ca047b7..0f6eac6 100644 --- a/src/arch/instruction.h +++ b/src/arch/instruction.h @@ -53,12 +53,6 @@ typedef struct _GArchInstruction GArchInstruction; typedef struct _GArchInstructionClass GArchInstructionClass; -/* Indique le type défini pour une instruction d'architecture. */ -GType g_arch_instruction_get_type(void); - -/* Indique l'encodage d'une instruction de façon détaillée. */ -const char *g_arch_instruction_get_encoding(const GArchInstruction *); - /* Drapeaux pour informations complémentaires */ typedef enum _ArchInstrFlag { @@ -68,12 +62,36 @@ typedef enum _ArchInstrFlag } ArchInstrFlag; +/* Type pour les types d'instructions */ +typedef uint16_t itid_t; + +/* Types de crochet de traitement */ +typedef enum _InstrProcessHook +{ + IPH_FETCH, /* Itinéraire de désassemblage */ + IPH_LINK, /* Edition des liens */ + IPH_POST, /* Résolution des symboles */ + + IPH_COUNT + +} InstrProcessHook; + + +/* Indique le type défini pour une instruction d'architecture. */ +GType g_arch_instruction_get_type(void); + +/* Indique l'encodage d'une instruction de façon détaillée. */ +const char *g_arch_instruction_get_encoding(const GArchInstruction *); + /* Ajoute une information complémentaire à une instruction. */ bool g_arch_instruction_set_flag(GArchInstruction *, ArchInstrFlag); /* Fournit les informations complémentaires d'une instruction. */ ArchInstrFlag g_arch_instruction_get_flags(const GArchInstruction *); +/* Fournit l'identifiant unique pour un ensemble d'instructions. */ +itid_t g_arch_instruction_get_type_id(const GArchInstruction *instr); + /** * La définition de "GArchProcessor", utile aux traitements complémentaires, ne peut @@ -87,17 +105,6 @@ ArchInstrFlag g_arch_instruction_get_flags(const GArchInstruction *); typedef struct _GArchProcessor GArchProcessor; -/* Types de crochet de traitement */ -typedef enum _InstrProcessHook -{ - IPH_FETCH, /* Itinéraire de désassemblage */ - IPH_LINK, /* Edition des liens */ - IPH_POST, /* Résolution des symboles */ - - IPH_COUNT - -} InstrProcessHook; - /* Complète un désassemblage accompli pour une instruction. */ typedef void (* instr_hook_fc) (GArchInstruction *, GArchProcessor *, GProcContext *, GExeFormat *); @@ -251,6 +258,9 @@ const char *g_arch_instruction_get_keyword(GArchInstruction *, AsmSyntax); /* Construit un petit résumé concis de l'instruction. */ char *g_arch_instruction_build_tooltip(const GArchInstruction *); +/* Fournit une description pour l'instruction manipulée. */ +const char *g_arch_instruction_get_description(const GArchInstruction *); + #endif /* _ARCH_INSTRUCTION_H */ diff --git a/tools/d2c/Makefile.am b/tools/d2c/Makefile.am index 5b9eb48..c07e16f 100644 --- a/tools/d2c/Makefile.am +++ b/tools/d2c/Makefile.am @@ -22,26 +22,34 @@ bin_PROGRAMS = d2c d2c_SOURCES = \ coder.h coder.c \ - tokens.l \ - grammar.y \ + d2c.c \ + decl.h \ + encoding.h encoding.c \ helpers.h helpers.c \ manual.h \ pproc.h pproc.c \ qckcall.h qckcall.c \ - spec.h spec.c + syntax.h syntax.c \ + tokens.l \ + grammar.y # _GNU_SOURCE : asprintf d2c_CFLAGS = -D_GNU_SOURCE d2c_LDADD = \ + assert/libd2cassert.la \ bits/libd2cbits.la \ conv/libd2cconv.la \ + desc/libd2cdesc.la \ format/libd2cformat.la \ hooks/libd2chooks.la \ + id/libd2cid.la \ + pattern/libd2cpattern.la \ rules/libd2crules.la \ - syntax/libd2csyntax.la \ args/libd2cargs.la +d2c_LDFLAGS = -lm + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h @@ -51,4 +59,4 @@ CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h EXTRA_DIST = tokens.h d2c_genmakefile.sh -SUBDIRS = args bits conv format hooks rules syntax +SUBDIRS = args assert bits conv desc format hooks id pattern rules diff --git a/tools/d2c/args/Makefile.am b/tools/d2c/args/Makefile.am index 1a2647c..3c4ef38 100644 --- a/tools/d2c/args/Makefile.am +++ b/tools/d2c/args/Makefile.am @@ -26,6 +26,9 @@ libd2cargs_la_SOURCES = \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2cargs_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/args/grammar.y b/tools/d2c/args/grammar.y index 41512a9..b038e22 100644 --- a/tools/d2c/args/grammar.y +++ b/tools/d2c/args/grammar.y @@ -78,7 +78,8 @@ right_op : FORCE_EXPR arg_expr { operand->func = NULL; operand->expr = $2; } call : NAME OP arg_list CP { $$.func = $1; $$.args = $3; } -arg_list : arg_expr { $$ = build_arg_list($1); } +arg_list : /* empty */ { $$ = build_empty_arg_list(); } + | arg_expr { $$ = build_arg_list($1); } | arg_list COMMA arg_expr { $$ = extend_arg_list($1, $3); } arg_expr : NAME { $$ = build_arg_expr_from_name($1); } diff --git a/tools/d2c/args/manager.c b/tools/d2c/args/manager.c index 3cd215d..8e1ef4d 100644 --- a/tools/d2c/args/manager.c +++ b/tools/d2c/args/manager.c @@ -132,10 +132,10 @@ struct _arg_expr_t /* Visite une expression en traitant en premier ses composantes. */ -typedef bool (* visit_expr_fc) (arg_expr_t *, int, const coding_bits *, const conv_list *, void *); +typedef bool (* visit_expr_fc) (arg_expr_t *); /* Visite une expression en traitant en premier ses composantes. */ -static bool visit_arg_expr(arg_expr_t *, visit_expr_fc, int, const coding_bits *, const conv_list *, void *); +static bool visit_arg_expr(arg_expr_t *, visit_expr_fc); /* Retrouve si elle existe une variable manipulée. */ static bool find_var_by_name(const coding_bits *, const conv_list *, const char *, raw_bitfield **, conv_func **); @@ -641,11 +641,8 @@ bool compute_arg_expr_size(const arg_expr_t *expr, const coding_bits *bits, cons /****************************************************************************** * * -* Paramètres : expr = première expression à encapsuler. * -* fd = descripteur d'un flux ouvert en écriture. * -* bits = gestionnaire des bits d'encodage. * -* list = liste de l'ensemble des fonctions de conversion. * -* data = éventuelle donnée à transmettre à chaque visite. * +* Paramètres : expr = première expression encapsulée. * +* visit = fonction à appeler pour chaque élément recontré. * * * * Description : Visite une expression en traitant en premier ses composantes.* * * @@ -655,29 +652,32 @@ bool compute_arg_expr_size(const arg_expr_t *expr, const coding_bits *bits, cons * * ******************************************************************************/ -static bool visit_arg_expr(arg_expr_t *expr, visit_expr_fc visit, int fd, const coding_bits *bits, const conv_list *list, void *data) +static bool visit_arg_expr(arg_expr_t *expr, visit_expr_fc visit) { bool result; /* Bilan à retourner */ switch (expr->type) { case CET_LOGICAL: - result = visit_arg_expr(expr->logical_expr1, visit, fd, bits, list, data); - result = visit_arg_expr(expr->logical_expr2, visit, fd, bits, list, data); + result = visit_arg_expr(expr->logical_expr1, visit); + if (result) + result = visit_arg_expr(expr->logical_expr2, visit); break; case CET_UNARY: - result = visit_arg_expr(expr->un_expr, visit, fd, bits, list, data); + result = visit_arg_expr(expr->un_expr, visit); break; case CET_CONDITIONAL: - result = visit_arg_expr(expr->cond_expr1, visit, fd, bits, list, data); - result = visit_arg_expr(expr->cond_expr2, visit, fd, bits, list, data); + result = visit_arg_expr(expr->cond_expr1, visit); + if (result) + result = visit_arg_expr(expr->cond_expr2, visit); break; case CET_BINARY: - result = visit_arg_expr(expr->bin_expr1, visit, fd, bits, list, data); - result = visit_arg_expr(expr->bin_expr2, visit, fd, bits, list, data); + result = visit_arg_expr(expr->bin_expr1, visit); + if (result) + result = visit_arg_expr(expr->bin_expr2, visit); break; default: @@ -686,7 +686,8 @@ static bool visit_arg_expr(arg_expr_t *expr, visit_expr_fc visit, int fd, const } - result &= visit(expr, fd, bits, list, data); + if (result) + result = visit(expr); return result; @@ -729,9 +730,6 @@ static bool find_var_by_name(const coding_bits *bits, const conv_list *list, con if (field != NULL) *field = cached_field; if (func != NULL) *func = cached_func; - if (!result) - fprintf(stderr, "Variable '%s' not found!\n", name); - return result; } @@ -753,31 +751,27 @@ static bool find_var_by_name(const coding_bits *bits, const conv_list *list, con bool ensure_arg_expr_content_fully_marked(arg_expr_t *expr, const coding_bits *bits, const conv_list *list) { - bool mark_sub_expr(arg_expr_t *sub, int dummy, const coding_bits *bts, const conv_list *lst, void *unused) + bool mark_sub_expr(arg_expr_t *sub) { bool result; /* Bilan à retourner */ size_t i; /* Boucle de parcours */ - bool mark_by_name(const coding_bits *_bts, const conv_list *_lst, const char *name) + bool mark_by_name(const char *name) { bool found; /* Bilan d'opération à renvoyer*/ raw_bitfield *field; /* Eventuel champ brut associé */ conv_func *func; /* Eventuelle fonction liée */ - found = find_var_by_name(bts, lst, name, &field, &func); + found = find_var_by_name(bits, list, name, &field, &func); if (found) { if (field != NULL) mark_raw_bitfield_as_used(field); else /*if (func != NULL) */ - mark_conv_func(func, true, bts, lst); - - printf(" VAR '%s' found (bf=%d fc=%d)\n", name, !!field, !!func); - + mark_conv_func(func, true, bits, list); } - else printf(" VAR '%s' not found...\n", name); return found; @@ -787,7 +781,7 @@ bool ensure_arg_expr_content_fully_marked(arg_expr_t *expr, const coding_bits *b switch (sub->type) { case CET_NAME: - /* result = */mark_by_name(bits, lst, sub->name); + /* result = */mark_by_name(sub->name); result = true; break; @@ -795,7 +789,7 @@ bool ensure_arg_expr_content_fully_marked(arg_expr_t *expr, const coding_bits *b result = true; for (i = 0; i < sub->comp_count && result; i++) if (!isdigit(sub->comp_items[i][0])) - result = mark_by_name(bits, lst, sub->comp_items[i]); + result = mark_by_name(sub->comp_items[i]); break; default: @@ -808,7 +802,7 @@ bool ensure_arg_expr_content_fully_marked(arg_expr_t *expr, const coding_bits *b } - return visit_arg_expr(expr, (visit_expr_fc)mark_sub_expr, -1, bits, list, NULL); + return visit_arg_expr(expr, (visit_expr_fc)mark_sub_expr); } @@ -820,8 +814,7 @@ bool ensure_arg_expr_content_fully_marked(arg_expr_t *expr, const coding_bits *b * arch = architecture visée par l'opération globale. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * -* wide = taille des mots décodés. * +* tab = décalage éventuel selon l'inclusion. * * * * Description : S'assure de la déclaration des expressions pre-requises. * * * @@ -831,15 +824,17 @@ bool ensure_arg_expr_content_fully_marked(arg_expr_t *expr, const coding_bits *b * * ******************************************************************************/ -bool ensure_arg_expr_content_fully_declared(arg_expr_t *expr, int fd, const coding_bits *bits, const conv_list *list, const pre_processor *pp, unsigned int wide) +bool ensure_arg_expr_content_fully_declared(arg_expr_t *expr, int fd, const coding_bits *bits, const conv_list *list, const char *tab) { - bool declare_sub_expr(arg_expr_t *sub, int f, const coding_bits *bts, const conv_list *lst, unsigned int *wideptr) + bool declare_sub_expr(arg_expr_t *sub) { bool result; /* Bilan à retourner */ size_t i; /* Boucle de parcours */ - /* Si l'expression a déjà été définie lors d'un précédent besoin... */ - printf(" sub declared ? %d -- type = %d\n", sub->declared, sub->type); + /** + * Si l'expression a déjà été définie lors d'un précédent besoin... + */ + if (sub->declared) return true; bool declare_by_name(const char *name) @@ -847,30 +842,10 @@ bool ensure_arg_expr_content_fully_declared(arg_expr_t *expr, int fd, const codi bool found; /* Bilan d'opération à renvoyer*/ conv_func *func; /* Eventuelle fonction liée */ - found = find_var_by_name(bts, lst, name, NULL, &func); + found = find_var_by_name(bits, list, name, NULL, &func); if (found && func != NULL) - { - printf("========= DECLARE for '%s'\n", name); - found = declare_conv_func(func, fd, bits, list, pp, wide); - printf("========= END DECLARE for '%s'\n", name); - - /** - * Si on déclare les variables suivantes dans declare_conv_func(), - * elles seront également déclarées pour les fonctions de conversion - * racine à partir de declare_syntax_items(), ce qui ne convient pas - * car les appels racine servent directement d'arguments. - */ - - /* - if (is_conv_func_expression(func)) - dprintf(_f, "\t\tuint%u_t val_%s; // Ho\n", _wide, name); // FIXME - else - dprintf(_f, "\t\tGArchOperand *val_%s;;;;;\n", name); // FIXME - */ - - - } + found = declare_conv_func(func, fd, bits, list, tab); return found; @@ -903,7 +878,7 @@ bool ensure_arg_expr_content_fully_declared(arg_expr_t *expr, int fd, const codi } - return visit_arg_expr(expr, (visit_expr_fc)declare_sub_expr, fd, bits, list, &wide); + return visit_arg_expr(expr, (visit_expr_fc)declare_sub_expr); } @@ -912,10 +887,9 @@ bool ensure_arg_expr_content_fully_declared(arg_expr_t *expr, int fd, const codi * * * Paramètres : expr = première expression à encapsuler. * * fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération globale. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * +* tab = décalage éventuel selon l'inclusion. * * exit = exprime le besoin d'une voie de sortie. [OUT] * * * * Description : S'assure de la définition des expressions pre-requises. * @@ -926,18 +900,9 @@ bool ensure_arg_expr_content_fully_declared(arg_expr_t *expr, int fd, const codi * * ******************************************************************************/ -bool ensure_arg_expr_content_fully_defined(arg_expr_t *expr, int fd, const char *arch, const coding_bits *bits, const conv_list *list, const pre_processor *pp, bool *exit) +bool ensure_arg_expr_content_fully_defined(arg_expr_t *expr, int fd, const coding_bits *bits, const conv_list *list, const char *tab, bool *exit) { - typedef struct _def_info - { - const char *arch; - const pre_processor *pp; - - } def_info; - - def_info info; /* Transmissions au visiteur */ - - bool define_sub_expr(arg_expr_t *sub, int f, const coding_bits *bts, const conv_list *lst, def_info *info) + bool define_sub_expr(arg_expr_t *sub) { bool result; /* Bilan à retourner */ size_t i; /* Boucle de parcours */ @@ -945,15 +910,15 @@ bool ensure_arg_expr_content_fully_defined(arg_expr_t *expr, int fd, const char /* Si l'expression a déjà été définie lors d'un précédent besoin... */ if (sub->defined) return true; - bool define_by_name(int _f, const coding_bits *_bts, const conv_list *_lst, def_info *_info, const char *name) + bool define_by_name(const char *name) { bool found; /* Bilan d'opération à renvoyer*/ conv_func *func; /* Eventuelle fonction liée */ - found = find_var_by_name(bts, lst, name, NULL, &func); + found = find_var_by_name(bits, list, name, NULL, &func); if (found && func != NULL) - found = define_conv_func(func, false, false, _f, _info->arch, _bts, _lst, _info->pp, exit); + found = define_conv_func(func, fd, bits, list, tab, false, exit); return found; @@ -963,7 +928,7 @@ bool ensure_arg_expr_content_fully_defined(arg_expr_t *expr, int fd, const char switch (sub->type) { case CET_NAME: - /* result = */define_by_name(f, bits, lst, info, sub->name); + /* result = */define_by_name(sub->name); result = true; break; @@ -971,7 +936,7 @@ bool ensure_arg_expr_content_fully_defined(arg_expr_t *expr, int fd, const char result = true; for (i = 0; i < sub->comp_count && result; i++) if (!isdigit(sub->comp_items[i][0])) - result = define_by_name(f, bits, lst, info, sub->comp_items[i]); + result = define_by_name(sub->comp_items[i]); break; default: @@ -986,10 +951,7 @@ bool ensure_arg_expr_content_fully_defined(arg_expr_t *expr, int fd, const char } - info.arch = arch; - info.pp = pp; - - return visit_arg_expr(expr, (visit_expr_fc)define_sub_expr, fd, bits, list, &info); + return visit_arg_expr(expr, (visit_expr_fc)define_sub_expr); } @@ -1031,9 +993,9 @@ bool define_arg_expr(const arg_expr_t *expr, int fd, const coding_bits *bits, co else { if (field != NULL) - dprintf(fd, "raw_%s", expr->name); + write_raw_bitfield(field, fd); else - dprintf(fd, "val_%s", expr->name); + write_conv_func(func, fd, true); } break; @@ -1103,17 +1065,15 @@ bool define_arg_expr(const arg_expr_t *expr, int fd, const coding_bits *bits, co if (field != NULL) { - if (max_size == 0) - dprintf(fd, "raw_%s", cname); - else - dprintf(fd, "raw_%s << %u", cname, max_size); + write_raw_bitfield(field, fd); + if (max_size > 0) + dprintf(fd, " << %u", max_size); } else { - if (max_size == 0) - dprintf(fd, "val_%s", cname); - else - dprintf(fd, "val_%s << %u", cname, max_size); + write_conv_func(func, fd, true); + if (max_size > 0) + dprintf(fd, " << %u", max_size); } } @@ -1204,6 +1164,32 @@ bool define_arg_expr(const arg_expr_t *expr, int fd, const coding_bits *bits, co /****************************************************************************** * * +* Paramètres : - * +* * +* Description : Crée une liste vide d'arguments de conversion. * +* * +* Retour : Nouvelle structure mise en place. * +* * +* Remarques : - * +* * +******************************************************************************/ + +arg_list_t *build_empty_arg_list(void) +{ + arg_list_t *result; /* Structure à retourner */ + + result = (arg_list_t *)calloc(1, sizeof(arg_list_t)); + + result->items = NULL; + result->count = 0; + + return result; + +} + + +/****************************************************************************** +* * * Paramètres : expr = expression initial pour constituer une liste. * * * * Description : Crée une liste d'arguments de conversion. * @@ -1283,6 +1269,26 @@ arg_list_t *extend_arg_list(arg_list_t *list, arg_expr_t *expr) /****************************************************************************** * * +* Paramètres : args = liste d'expressions à traiter. * +* * +* Description : Indique le nombre d'arguments présents dans la liste. * +* * +* Retour : Nombre positif ou nul. * +* * +* Remarques : - * +* * +******************************************************************************/ +#ifndef NDEBUG +size_t get_arg_list_size(const arg_list_t *args) +{ + return args->count; + +} +#endif + + +/****************************************************************************** +* * * Paramètres : args = liste d'expressions à supprimer de la mémoire. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * @@ -1316,8 +1322,7 @@ bool ensure_arg_list_content_fully_marked(arg_list_t *args, const coding_bits *b * fd = descripteur d'un flux ouvert en écriture. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * -* wide = taille des mots décodés. * +* tab = décalage éventuel selon l'inclusion. * * * * Description : S'assure de la déclaration des expressions pre-requises. * * * @@ -1327,7 +1332,7 @@ bool ensure_arg_list_content_fully_marked(arg_list_t *args, const coding_bits *b * * ******************************************************************************/ -bool ensure_arg_list_content_fully_declared(arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list, const pre_processor *pp, unsigned int wide) +bool ensure_arg_list_content_fully_declared(arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list, const char *tab) { bool result; /* Bilan à remonter */ size_t i; /* Boucle de parcours */ @@ -1335,7 +1340,7 @@ bool ensure_arg_list_content_fully_declared(arg_list_t *args, int fd, const codi result = true; for (i = 0; i < args->count && result; i++) - result = ensure_arg_expr_content_fully_declared(args->items[i], fd, bits, list, pp, wide); + result = ensure_arg_expr_content_fully_declared(args->items[i], fd, bits, list, tab); return result; @@ -1346,10 +1351,9 @@ bool ensure_arg_list_content_fully_declared(arg_list_t *args, int fd, const codi * * * Paramètres : args = liste d'expressions à supprimer de la mémoire. * * fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération globale. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * +* tab = décalage éventuel selon l'inclusion. * * exit = exprime le besoin d'une voie de sortie. [OUT] * * * * Description : S'assure de la définition des expressions pre-requises. * @@ -1360,7 +1364,7 @@ bool ensure_arg_list_content_fully_declared(arg_list_t *args, int fd, const codi * * ******************************************************************************/ -bool ensure_arg_list_content_fully_defined(arg_list_t *args, int fd, const char *arch, const coding_bits *bits, const conv_list *list, const pre_processor *pp, bool *exit) +bool ensure_arg_list_content_fully_defined(arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list, const char *tab, bool *exit) { bool result; /* Bilan à remonter */ size_t i; /* Boucle de parcours */ @@ -1368,7 +1372,7 @@ bool ensure_arg_list_content_fully_defined(arg_list_t *args, int fd, const char result = true; for (i = 0; i < args->count && result; i++) - result = ensure_arg_expr_content_fully_defined(args->items[i], fd, arch, bits, list, pp, exit); + result = ensure_arg_expr_content_fully_defined(args->items[i], fd, bits, list, tab, exit); return result; diff --git a/tools/d2c/args/manager.h b/tools/d2c/args/manager.h index 9332b2b..de69105 100644 --- a/tools/d2c/args/manager.h +++ b/tools/d2c/args/manager.h @@ -25,7 +25,10 @@ #define _TOOLS_D2C_ARGS_MANAGER_H -#include "../pproc.h" +#ifndef NDEBUG +# include <sys/types.h> +#endif + #include "../bits/manager.h" @@ -105,10 +108,10 @@ bool compute_arg_expr_size(const arg_expr_t *, const coding_bits *, const conv_l bool ensure_arg_expr_content_fully_marked(arg_expr_t *, const coding_bits *, const conv_list *); /* S'assure de la déclaration des expressions pre-requises. */ -bool ensure_arg_expr_content_fully_declared(arg_expr_t *, int, const coding_bits *, const conv_list *, const pre_processor *, unsigned int); +bool ensure_arg_expr_content_fully_declared(arg_expr_t *, int, const coding_bits *, const conv_list *, const char *); /* S'assure de la définition des expressions pre-requises. */ -bool ensure_arg_expr_content_fully_defined(arg_expr_t *, int, const char *, const coding_bits *, const conv_list *, const pre_processor *, bool *); +bool ensure_arg_expr_content_fully_defined(arg_expr_t *, int, const coding_bits *, const conv_list *, const char *, bool *); /* Définit une expression utilisée dans une conversion. */ bool define_arg_expr(const arg_expr_t *, int, const coding_bits *, const conv_list *); @@ -122,6 +125,9 @@ bool define_arg_expr(const arg_expr_t *, int, const coding_bits *, const conv_li typedef struct _arg_list_t arg_list_t; +/* Crée une liste vide d'arguments de conversion. */ +arg_list_t *build_empty_arg_list(void); + /* Crée une liste d'arguments de conversion. */ arg_list_t *build_arg_list(arg_expr_t *); @@ -131,14 +137,19 @@ void delete_arg_list(arg_list_t *); /* Ajoute un élément à une liste d'arguments de conversion. */ arg_list_t *extend_arg_list(arg_list_t *, arg_expr_t *); +/* Indique le nombre d'arguments présents dans la liste. */ +#ifndef NDEBUG +size_t get_arg_list_size(const arg_list_t *); +#endif + /* S'assure du marquage des expressions pre-requises. */ bool ensure_arg_list_content_fully_marked(arg_list_t *, const coding_bits *, const conv_list *); /* S'assure de la déclaration des expressions pre-requises. */ -bool ensure_arg_list_content_fully_declared(arg_list_t *, int, const coding_bits *, const conv_list *, const pre_processor *, unsigned int); +bool ensure_arg_list_content_fully_declared(arg_list_t *, int, const coding_bits *, const conv_list *, const char *); /* S'assure de la définition des expressions pre-requises. */ -bool ensure_arg_list_content_fully_defined(arg_list_t *, int, const char *, const coding_bits *, const conv_list *, const pre_processor *, bool *); +bool ensure_arg_list_content_fully_defined(arg_list_t *, int, const coding_bits *, const conv_list *, const char *, bool *); /* Définit les variables associées à un appel de fonction. */ bool define_arg_list(const arg_list_t *, int, const coding_bits *, const conv_list *); diff --git a/tools/d2c/args/tokens.l b/tools/d2c/args/tokens.l index 9851f62..9645ba2 100644 --- a/tools/d2c/args/tokens.l +++ b/tools/d2c/args/tokens.l @@ -51,7 +51,7 @@ <binval>[01][01]* { yylvalp->string = strdup(yytext); return BINVAL; } <binval>"'" { yy_pop_state(); } -\"[^\"]*\" { yylvalp->string = strndup(yytext + 1, strlen(yytext) - 2); printf("str = '%s'\n", yylvalp->string); return STRING; } +\"[^\"]*\" { yylvalp->string = strndup(yytext + 1, strlen(yytext) - 2); return STRING; } "0x" { yy_push_state(hexval); } <hexval>[0-9a-f][0-9a-f]* { yylvalp->string = strdup(yytext); yy_pop_state(); return HEXVAL; } @@ -71,5 +71,12 @@ [ ]+ { } +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c args block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + %% diff --git a/tools/d2c/assert/Makefile.am b/tools/d2c/assert/Makefile.am new file mode 100644 index 0000000..34d5b1c --- /dev/null +++ b/tools/d2c/assert/Makefile.am @@ -0,0 +1,37 @@ + +BUILT_SOURCES = grammar.h + + +# On évite d'utiliser les variables personnalisées de type *_la_[YL]FLAGS +# afin de conserver des noms de fichiers simples, ie sans le nom de la +# bibliothèque de sortie en préfixe. + +AM_YFLAGS = -v -d -p assert_ + +AM_LFLAGS = -P assert_ -o lex.yy.c --header-file=tokens.h \ + -Dyyget_lineno=assert_get_lineno \ + -Dyy_scan_string=assert__scan_string \ + -Dyy_delete_buffer=assert__delete_buffer + +AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) + + +noinst_LTLIBRARIES = libd2cassert.la + +.NOTPARALLEL: $(noinst_LTLIBRARIES) + +libd2cassert_la_SOURCES = \ + decl.h \ + manager.h manager.c \ + tokens.l \ + grammar.y + +# _GNU_SOURCE : asprintf +libd2cassert_la_CFLAGS = -D_GNU_SOURCE + + +# Automake fait les choses à moitié +CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h + +# Pareil : de tous les fichiers générés, seule la sortie de Flex saute pour les distributions ! +EXTRA_DIST = tokens.h diff --git a/tools/d2c/assert/decl.h b/tools/d2c/assert/decl.h new file mode 100644 index 0000000..b18edbc --- /dev/null +++ b/tools/d2c/assert/decl.h @@ -0,0 +1,37 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * decl.h - déclarations de prototypes utiles + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _TOOLS_D2C_ASSERT_DECL_H +#define _TOOLS_D2C_ASSERT_DECL_H + + +#include "manager.h" + + + +/* Interprête des données relatives à une série de conditions. */ +bool load_assertions_from_raw_block(disass_assert *, const char *); + + + +#endif /* _TOOLS_D2C_ASSERT_DECL_H */ diff --git a/tools/d2c/assert/grammar.y b/tools/d2c/assert/grammar.y new file mode 100644 index 0000000..3db47e6 --- /dev/null +++ b/tools/d2c/assert/grammar.y @@ -0,0 +1,133 @@ + +%{ + +#include "tokens.h" + + +/* Affiche un message d'erreur suite à l'analyse en échec. */ +static int yyerror(disass_assert *, char *); + +%} + + +%code requires { + +#include "decl.h" + +} + + +%union { + + char *string; /* Chaîne de caractères */ + + struct + { + char *field; /* Nom de champ de bits */ + DisassCondOp op; /* Opération impliquée */ + char *value; /* Valeur soumise à condition */ + + } cond_info; + +} + + +%define api.pure full + +%parse-param { disass_assert *dassert } + +%code provides { + +#define YY_DECL \ + int assert_lex(YYSTYPE *yylvalp) + +YY_DECL; + +} + + +%token CR +%token EQ NE +%token AND OR +%token FIELD VALUE + +%type <cond_info> condition +%type <string> FIELD +%type <string> VALUE + + +%% + + +assert : /* empty */ + | conditions assert + +conditions : condition { register_disass_assert(dassert, DCG_UNIQ, $1.field, $1.op, $1.value); } + | condition AND and_conds { extend_disass_assert(dassert, $1.field, $1.op, $1.value); } + | condition OR or_conds { extend_disass_assert(dassert, $1.field, $1.op, $1.value); } + +and_conds : condition { register_disass_assert(dassert, DCG_AND, $1.field, $1.op, $1.value); } + | condition AND and_conds { extend_disass_assert(dassert, $1.field, $1.op, $1.value); } + +or_conds : condition { register_disass_assert(dassert, DCG_OR, $1.field, $1.op, $1.value); } + | condition AND or_conds { extend_disass_assert(dassert, $1.field, $1.op, $1.value); } + +condition : FIELD EQ VALUE { $$.field = $1; $$.op = DCO_EQ; $$.value = $3; } + | FIELD NE VALUE { $$.field = $1; $$.op = DCO_NE; $$.value = $3; } + + +%% + + +/****************************************************************************** +* * +* Paramètres : dassert = structure impliquée dans le processus. * +* msg = message d'erreur. * +* * +* Description : Affiche un message d'erreur suite à l'analyse en échec. * +* * +* Retour : 0 * +* * +* Remarques : - * +* * +******************************************************************************/ + +static int yyerror(disass_assert *dassert, char *msg) +{ + printf("assert yyerror line %d: %s\n", yyget_lineno(), msg); + + return 0; + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = structure à constituer à partir de données lues. * +* raw = données brutes à analyser. * +* * +* Description : Interprête des données relatives à une série de conditions. * +* * +* Retour : true si l'opération s'est bien déroulée, false sinon. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool load_assertions_from_raw_block(disass_assert *dassert, const char *raw) +{ + bool result; /* Bilan à faire remonter */ + YY_BUFFER_STATE state; /* Support d'analyse */ + int status; /* Bilan de l'analyse */ + + state = yy_scan_string(raw); + + status = yyparse(dassert); + + result = (status == 0); + + yy_delete_buffer(state); + + return result; + +} diff --git a/tools/d2c/assert/manager.c b/tools/d2c/assert/manager.c new file mode 100644 index 0000000..54e9101 --- /dev/null +++ b/tools/d2c/assert/manager.c @@ -0,0 +1,365 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * manager.c - désassemblage sous condition + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "manager.h" + + +#include <assert.h> +#include <malloc.h> +#include <string.h> + + +#include "../helpers.h" + + + +/* Elément d'une condition décodée */ +typedef struct _def_cond +{ + char *field; /* Désignation du champ */ + DisassCondOp op; /* Opération de comparaison */ + char *value; /* Désignation de la valeur */ + + char *lower; /* Version minuscule */ + +} def_cond; + +/* Ligne de condition(s) */ +typedef struct _cond_line +{ + def_cond *conditions; /* Conditions à vérifier */ + size_t count; /* Taille de cette liste */ + + DisassCondGroup group; /* Type du groupe */ + +} cond_line; + +/* Représentation de l'ensemble de conditions préalables */ +struct _disass_assert +{ + cond_line *lines; /* Lignes de conditions */ + size_t count; /* Taille de cette liste */ + +}; + + + +/****************************************************************************** +* * +* Paramètres : - * +* * +* Description : Crée un nouveau gestionnaire de conditions de désassemblage. * +* * +* Retour : Nouvelle structure prête à emploi. * +* * +* Remarques : - * +* * +******************************************************************************/ + +disass_assert *create_disass_assert(void) +{ + disass_assert *result; /* Définition vierge à renvoyer*/ + + result = (disass_assert *)calloc(1, sizeof(disass_assert)); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = gestionnaire d'un ensemble de conditions à libérer.* +* * +* Description : Supprime de la mémoire un gestionnaire de conditions. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void delete_disass_assert(disass_assert *dassert) +{ + size_t i; /* Boucle de parcours #1 */ + cond_line *line; /* Ligne à compléter */ + size_t j; /* Boucle de parcours #2 */ + + for (i = 0; i < dassert->count; i++) + { + line = &dassert->lines[i]; + + for (j = 0; j < line->count; j++) + { + free(line->conditions[j].field); + free(line->conditions[j].value); + + free(line->conditions[j].lower); + + } + + if (line->conditions != NULL) + free(line->conditions); + + } + + if (dassert->lines != NULL) + free(dassert->lines); + + free(dassert); + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = gestionnaire de conditions à consulter. * +* group = type du groupe de conditions attendues. * +* field = champ de bits à prendre en compte. * +* op = type d'opération impliquée. * +* value = valeur soumise à condition. * +* * +* Description : Initie une nouvelle condition à vérifier. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void register_disass_assert(disass_assert *dassert, DisassCondGroup group, char *field, DisassCondOp op, char *value) +{ + cond_line *new; /* Nouvelle ligne de conditions*/ + + dassert->lines = (cond_line *)realloc(dassert->lines, + ++dassert->count * sizeof(cond_line)); + + new = &dassert->lines[dassert->count - 1]; + + new->conditions = NULL; + new->count = 0; + + new->group = group; + + extend_disass_assert(dassert, field, op, value); + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = gestionnaire de conditions à consulter. * +* field = champ de bits à prendre en compte. * +* op = type d'opération impliquée. * +* value = valeur soumise à condition. * +* * +* Description : Enregistre une nouvelle condition à vérifier. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void extend_disass_assert(disass_assert *dassert, char *field, DisassCondOp op, char *value) +{ + cond_line *line; /* Ligne à compléter */ + def_cond *new; /* Nouvelle définition */ + + assert(dassert->count > 0); + + line = &dassert->lines[dassert->count - 1]; + + line->conditions = (def_cond *)realloc(line->conditions, + ++line->count * sizeof(def_cond)); + + new = &line->conditions[line->count - 1]; + + new->field = field; + new->op = op; + new->value = value; + + new->lower = strdup(field); + make_string_lower(new->lower); + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = gestionnaire de conditions à consulter. * +* * +* Description : Indique la présence de conditions à vérifier. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool is_disass_assert_empty(const disass_assert *dassert) +{ + bool result; /* Bilan à retourner */ + + result = (dassert->count == 0); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = gestionnaire d'un ensemble de conditions à marquer.* +* bits = gestionnaire des bits d'encodage. * +* * +* Description : Marque les éléments de condition effectivement utilisés. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool mark_disass_assert(const disass_assert *dassert, const coding_bits *bits) +{ + bool result; /* Bilan à retourner */ + size_t i; /* Boucle de parcours #1 */ + cond_line *line; /* Ligne de condition(s) */ + size_t j; /* Boucle de parcours #2 */ + def_cond *cond; /* Condition à marquer */ + raw_bitfield *rf; /* Champ de bits à marquer */ + + result = true; + + for (i = 0; i < dassert->count && result; i++) + { + line = &dassert->lines[i]; + + for (j = 0; j < line->count && result; j++) + { + cond = &line->conditions[j]; + + rf = find_named_field_in_bits(bits, cond->lower); + + if (rf == NULL) + { + fprintf(stderr, "Unknown bitfield '%s' for condition!\n", cond->field); + result = false; + } + + else + mark_raw_bitfield_as_used(rf); + + } + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : dassert = gestionnaire d'un ensemble de conditions à définir.* +* fd = descripteur d'un flux ouvert en écriture. * +* bits = gestionnaire des bits d'encodage. * +* * +* Description : Définit les éléments de condition à appliquer. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool define_disass_assert(const disass_assert *dassert, int fd, const coding_bits *bits) +{ + size_t i; /* Boucle de parcours #1 */ + cond_line *line; /* Ligne de condition(s) */ + size_t j; /* Boucle de parcours #2 */ + def_cond *cond; /* Condition à marquer */ + raw_bitfield *rf; /* Champ de bits à marquer */ + + for (i = 0; i < dassert->count; i++) + { + line = &dassert->lines[i]; + + if (i > 0) + dprintf(fd, " && "); + + if (dassert->count > 1 && line->count > 1) + dprintf(fd, "("); + + for (j = 0; j < line->count; j++) + { + cond = &line->conditions[j]; + + rf = find_named_field_in_bits(bits, cond->lower); + + assert(rf != NULL); + + if (j > 0) + switch (line->group) + { + case DCG_UNIQ: + assert(false); + break; + + case DCG_AND: + dprintf(fd, " && "); + break; + + case DCG_OR: + dprintf(fd, " || "); + break; + + } + + write_raw_bitfield(rf, fd); + + switch (cond->op) + { + case DCO_EQ: + dprintf(fd, " == "); + break; + + case DCO_NE: + dprintf(fd, " != "); + break; + + } + + dprintf(fd, "b%s", cond->value); + + } + + if (dassert->count > 1 && line->count > 1) + dprintf(fd, ")"); + + } + + return true; + +} diff --git a/tools/d2c/assert/manager.h b/tools/d2c/assert/manager.h new file mode 100644 index 0000000..042c2e0 --- /dev/null +++ b/tools/d2c/assert/manager.h @@ -0,0 +1,80 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * manager.h - prototypes pour le désassemblage sous condition + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _TOOLS_D2C_ASSERT_MANAGER_H +#define _TOOLS_D2C_ASSERT_MANAGER_H + + +#include <stdbool.h> + + +#include "../bits/manager.h" + + + +/* Définition d'opération conditionnelle */ + +typedef enum _DisassCondOp +{ + DCO_EQ, /* Egalité */ + DCO_NE /* Différence */ + +} DisassCondOp; + +typedef enum _DisassCondGroup +{ + DCG_UNIQ, /* Condition unique */ + DCG_AND, /* Obligation */ + DCG_OR /* Complémentarité */ + +} DisassCondGroup; + + +/* Représentation de l'ensemble de conditions préalables */ +typedef struct _disass_assert disass_assert; + + +/* Crée un nouveau gestionnaire de conditions de désassemblage. */ +disass_assert *create_disass_assert(void); + +/* Supprime de la mémoire un gestionnaire de conditions. */ +void delete_disass_assert(disass_assert *); + +/* Initie une nouvelle condition à vérifier. */ +void register_disass_assert(disass_assert *, DisassCondGroup, char *, DisassCondOp, char *); + +/* Enregistre une nouvelle condition à vérifier. */ +void extend_disass_assert(disass_assert *, char *, DisassCondOp, char *); + +/* Indique la présence de conditions à vérifier. */ +bool is_disass_assert_empty(const disass_assert *); + +/* Marque les éléments de condition effectivement utilisés. */ +bool mark_disass_assert(const disass_assert *, const coding_bits *); + +/* Définit les éléments de condition à appliquer. */ +bool define_disass_assert(const disass_assert *, int, const coding_bits *); + + + +#endif /* _TOOLS_D2C_ASSERT_MANAGER_H */ diff --git a/tools/d2c/assert/tokens.l b/tools/d2c/assert/tokens.l new file mode 100644 index 0000000..192bcc7 --- /dev/null +++ b/tools/d2c/assert/tokens.l @@ -0,0 +1,41 @@ + +%top { + +#include "grammar.h" + +} + + +%option noyywrap +%option nounput +%option noinput +%option yylineno +%option stack +%option noyy_top_state +%option noyy_push_state +%option noyy_pop_state + + +%% + + +[ \t\n] { } + +"==" { return EQ; } +"!=" { return NE; } + +"&&" { return AND; } +"||" { return OR; } + +[A-Za-z_][A-Za-z0-9_]* { yylvalp->string = strdup(yytext); return FIELD; } + +[01]+ { yylvalp->string = strdup(yytext); return VALUE; } + +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c assert block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + +%% diff --git a/tools/d2c/bits/Makefile.am b/tools/d2c/bits/Makefile.am index b1d79b6..0d8beb8 100644 --- a/tools/d2c/bits/Makefile.am +++ b/tools/d2c/bits/Makefile.am @@ -26,6 +26,9 @@ libd2cbits_la_SOURCES = \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2cbits_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/bits/manager.c b/tools/d2c/bits/manager.c index 4999680..560bade 100644 --- a/tools/d2c/bits/manager.c +++ b/tools/d2c/bits/manager.c @@ -29,6 +29,7 @@ #include <malloc.h> #include <stdint.h> #include <string.h> +#include <unistd.h> #include "../helpers.h" @@ -114,6 +115,25 @@ void mark_raw_bitfield_as_used(raw_bitfield *field) } +/****************************************************************************** +* * +* Paramètres : field = champ de bits à traiter. * +* fd = descripteur d'un flux ouvert en écriture. * +* * +* Description : Imprime la désignation d'un champ de bits dans du code. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void write_raw_bitfield(const raw_bitfield *field, int fd) +{ + dprintf(fd, "raw_%s", field->name); + +} + @@ -294,13 +314,30 @@ raw_bitfield *find_named_field_in_bits(const coding_bits *bits, const char *name * * ******************************************************************************/ -bool declare_used_bits_fields(const coding_bits *bits, int fd, unsigned int wide) +bool declare_used_bits_fields(const coding_bits *bits, int fd) { + unsigned int wide; /* Taille des mots */ size_t i; /* Boucle de parcours */ + off_t start; /* Point de départ dans le code*/ + off_t end; /* Point d'arrivée dans le code*/ + + wide = count_coded_bits(bits); for (i = 0; i < bits->bf_count; i++) if (bits->fields[i].used) - dprintf(fd, "\t\tuint%u_t raw_%s;\n", wide, bits->fields[i].name); + { + start = lseek(fd, 0, SEEK_CUR); + + dprintf(fd, "\tuint%u_t ", wide); + write_raw_bitfield(&bits->fields[i], fd); + dprintf(fd, ";"); + + end = lseek(fd, 0, SEEK_CUR); + + dprintf(fd, "%*s", 42 - (int)(end - start), "/"); + dprintf(fd, "* Champ brut à décoder */\n"); + + } return true; @@ -325,22 +362,22 @@ bool check_bits_correctness(const coding_bits *bits, int fd) switch (bits->curpos) { case 8: - dprintf(fd, "\t\tif ((raw & 0x%" PRIx8 ") != 0x%" PRIx8 ") return NULL;\n", + dprintf(fd, "\tif ((raw & 0x%" PRIx8 ") != 0x%" PRIx8 ") return NULL;\n", (uint8_t)bits->mask, (uint8_t)bits->bits); break; case 16: - dprintf(fd, "\t\tif ((raw & 0x%" PRIx16 ") != 0x%" PRIx16 ") return NULL;\n", + dprintf(fd, "\tif ((raw & 0x%" PRIx16 ") != 0x%" PRIx16 ") return NULL;\n", (uint16_t)bits->mask, (uint16_t)bits->bits); break; case 32: - dprintf(fd, "\t\tif ((raw & 0x%" PRIx32 ") != 0x%" PRIx32 ") return NULL;\n", + dprintf(fd, "\tif ((raw & 0x%" PRIx32 ") != 0x%" PRIx32 ") return NULL;\n", (uint32_t)bits->mask, (uint32_t)bits->bits); break; case 64: - dprintf(fd, "\t\tif ((raw & 0x%" PRIx64 ") != 0x%" PRIx64 ") return NULL;\n", + dprintf(fd, "\tif ((raw & 0x%" PRIx64 ") != 0x%" PRIx64 ") return NULL;\n", bits->mask, bits->bits); break; @@ -377,7 +414,9 @@ bool define_used_bits_fields(const coding_bits *bits, int fd) rf = &bits->fields[i]; if (!rf->used) continue; - dprintf(fd, "\t\traw_%s = (_raw >> %u) & 0x%llx;\n", rf->name, rf->start, (1ull << rf->length) - 1); + dprintf(fd, "\t"); + write_raw_bitfield(rf, fd); + dprintf(fd, " = (raw >> %u) & 0x%llx;\n", rf->start, (1ull << rf->length) - 1); got_one = true; diff --git a/tools/d2c/bits/manager.h b/tools/d2c/bits/manager.h index f696250..71d9055 100644 --- a/tools/d2c/bits/manager.h +++ b/tools/d2c/bits/manager.h @@ -44,6 +44,8 @@ unsigned int get_raw_bitfield_length(const raw_bitfield *); /* Marque un champ de bits comme étant utile. */ void mark_raw_bitfield_as_used(raw_bitfield *); +/* Imprime la désignation d'un champ de bits dans du code. */ +void write_raw_bitfield(const raw_bitfield *, int); @@ -74,7 +76,7 @@ unsigned int count_coded_bits(const coding_bits *); raw_bitfield *find_named_field_in_bits(const coding_bits *, const char *); /* Déclare les variables C associées aux champs de bits. */ -bool declare_used_bits_fields(const coding_bits *, int, unsigned int); +bool declare_used_bits_fields(const coding_bits *, int); /* Vérifie que les bits fixes correspondent au masque attendu. */ bool check_bits_correctness(const coding_bits *, int); diff --git a/tools/d2c/bits/tokens.l b/tools/d2c/bits/tokens.l index 99fb96d..4879f4f 100644 --- a/tools/d2c/bits/tokens.l +++ b/tools/d2c/bits/tokens.l @@ -29,5 +29,11 @@ [01] { yylvalp->integer = atoi(yytext); return BIT; } +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c bits block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } %% diff --git a/tools/d2c/coder.c b/tools/d2c/coder.c index 65e9605..e286a1d 100644 --- a/tools/d2c/coder.c +++ b/tools/d2c/coder.c @@ -27,13 +27,10 @@ #include <assert.h> #include <fcntl.h> #include <malloc.h> -#include <regex.h> -#include <stdint.h> #include <stdio.h> #include <string.h> +#include <time.h> #include <unistd.h> -#include <sys/stat.h> -#include <sys/types.h> #include "helpers.h" @@ -47,8 +44,6 @@ struct _rented_coder { const char *input; /* Fichier de définitions */ - InputOutputType type; /* Type des définitions (E/S) */ - const char *outdir; /* Lieu d'enregistrement */ const char *arch; /* Architecture à traiter */ const char *header; /* En-tête pour les en-têtes */ const char *const_prefix; /* Préfixe pour les opérandes */ @@ -61,6 +56,11 @@ struct _rented_coder char *raw_details; /* Eventuels compléments bruts */ char *details; /* Eventuels compléments */ + instr_id *id; /* Gestionnaire d'identifiant */ + instr_desc *desc; /* Gestionnaire de description */ + + bool useless; /* Instruction non utilisée */ + encoding_spec **specs; /* Définitions déjà en place */ size_t specs_count; /* Nombre de ces définitions */ encoding_spec *cur_spec; /* Définition courante */ @@ -69,32 +69,58 @@ struct _rented_coder +/* --------------------------- REPRESENTATION D'ENCODAGES --------------------------- */ + + +/* Détermine le nombre de bits analysés lors d'un désassemblage. */ +static unsigned int get_bit_width_for_encoding_spec(const rented_coder *, const string_exch *); + + + /* --------------------------- GENERATIONS DE CODE SOURCE --------------------------- */ -/* S'assure de la présence du répertoire de sortie du code. */ -static bool check_gen_dir(const rented_coder *); +/* Ouvre un fichier principal en écriture pour y placer du code. */ +static int open_instr_header_file(const rented_coder *, const output_info *, const char *, bool *); + +/* Ouvre un fichier principal en écriture pour y placer du code. */ +static int open_instr_code_file(const rented_coder *, const output_info *, const char *, bool *); + +/* Ouvre un fichier global en écriture pour y placer du code. */ +static int open_global_header_file(const rented_coder *, const output_info *, const char *, bool *); + +/* Imprime dans un flux donné un commentaire de propriété. */ +static void write_header_file_license(int, const output_info *, const char *, const char *); /* Imprime dans un flux donné un commentaire de propriété. */ -static void write_owner_comments(const rented_coder *, int, const char *, const char *, char); +static void write_code_file_license(int, const output_info *, const char *, const char *); + +/* Initialise le contenu utile du fichier des instructions. */ +static void init_coder_opcodes_file(int, const output_info *, const char *); + +/* Initialise le contenu utile d'un fichier d'instructions. */ +static void init_coder_code_file(int, const char *); + +/* Centralise l'impression du nom de fonction de désassemblage. */ +static void write_read_function_name(int fd, const char *, const string_exch *, const char *); -/* Construit un chemin d'accès à un modèle de fichier de code. */ -static char *build_template_filename(const rented_coder *, const char *, const char *, char); +/* Génère ou complète un fichier contenant le code C principal. */ +static bool output_coder_raw(const rented_coder *, const output_info *, const string_exch *, const encoding_spec *, int, int); -/* Définit un modèle d'en-tête de définitions. */ -static bool create_template_file(const rented_coder *, const char *, const char *, char); +/* Génère ou complète un fichier contenant le code C principal. */ +static bool output_coder_main_raw(const rented_coder *, const output_info *, const string_exch *, int, int); -/* Construit un chemin d'accès à un fichier de code source. */ -static char *build_code_filename(const rented_coder *, const char *, const char *, const char *, char); +/* Génère ou complète un fichier contenant le code C principal. */ +static bool output_coder_format(const rented_coder *, const output_info *, const string_exch *, const encoding_spec *, int, int); -/* Ouvre un fichier en écriture pour y placer du code. */ -static int create_code_file(const rented_coder *, const char *, const char *, const char *, char); +/* Initialise le contenu utile du fichier des identifiants. */ +static void init_coder_identifiers_file(int, const output_info *); -/* Ecrit une partie des fonctions issues des spécifications. */ -static bool dump_all_matching_specs_in_coder(const rented_coder *, const string_exch *, int, int); +/* Initialise le contenu utile du fichier des mots clefs. */ +static void init_coder_keywords_file(int, const output_info *); -/* Ecrit une partie des fonctions issues des spécifications. */ -static bool dump_all_matching_specs_from_format(const rented_coder *, const string_exch *, int, int); +/* Initialise le contenu utile du fichier des descriptions. */ +static void init_coder_descriptions_file(int, const output_info *); @@ -105,7 +131,7 @@ static bool dump_all_matching_specs_from_format(const rented_coder *, const stri /****************************************************************************** * * -* Paramètres : - * +* Paramètres : pp = préprocesseur déjà chargé à intégrer. * * * * Description : Débute la définition d'une fonction de désassemblage. * * * @@ -115,16 +141,21 @@ static bool dump_all_matching_specs_from_format(const rented_coder *, const stri * * ******************************************************************************/ -rented_coder *create_coder(void) +rented_coder *create_coder(pre_processor *pp) { rented_coder *result; /* Structure à renvoyer */ result = (rented_coder *)calloc(1, sizeof(rented_coder)); - result->pp = create_pre_processor(); + result->pp = pp; + + result->id = create_instruction_id(); + result->desc = create_instruction_description(); result->cur_spec = create_encoding_spec(); + result->useless = false; + return result; } @@ -157,6 +188,9 @@ void delete_coder(rented_coder *coder) free(coder->details); } + delete_instruction_id(coder->id); + delete_instruction_description(coder->desc); + for (i = 0; i < coder->specs_count; i++) delete_encoding_spec(coder->specs[i]); @@ -184,15 +218,14 @@ void delete_coder(rented_coder *coder) bool do_basic_checks_with_coder(const rented_coder *coder) { - bool result; /* Validité à retourner */ - + /* result = coder->type != IOT_UNDEFINED && coder->outdir != NULL; result &= coder->arch != NULL && coder->header != NULL; if (coder->type == IOT_FORMAT) result &= (coder->const_prefix != NULL); - - return result; + */ + return false; } @@ -248,32 +281,13 @@ void set_coder_input_file(rented_coder *coder, const char *input) * Remarques : - * * * ******************************************************************************/ - +/* void set_coder_input_type(rented_coder *coder, InputOutputType type) { coder->type = type; } - - -/****************************************************************************** -* * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * -* outdir = répertoire de génération des fichiers. * -* * -* Description : Spécifie le répertoire de base pour les sorties de code. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -void set_coder_output_directory(rented_coder *coder, const char *outdir) -{ - coder->outdir = outdir; - -} +*/ /****************************************************************************** @@ -336,23 +350,10 @@ void set_coder_const_prefix(rented_coder *coder, const char *prefix) } -/****************************************************************************** -* * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * -* * -* Description : Fournit le pré-processeur du compilateur. * -* * -* Retour : Pré-processeur à manipuler. * -* * -* Remarques : - * -* * -******************************************************************************/ - -pre_processor *get_coder_pre_proc(const rented_coder *coder) -{ - return coder->pp; -} +/* ---------------------------------------------------------------------------------- */ +/* INFORMATIONS GENERALES */ +/* ---------------------------------------------------------------------------------- */ /****************************************************************************** @@ -392,6 +393,110 @@ void save_notes_for_coder(rented_coder *coder, char *copy, char *ins, char sep, } +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* * +* Description : Fournit la désignation nominale d'une instruction. * +* * +* Retour : Désignation nominale à libérer de la mémoire. * +* * +* Remarques : - * +* * +******************************************************************************/ + +char *get_coder_nominal_name(const rented_coder *coder) +{ + char *result; /* Désignation à retourner */ + + if (coder->separator == '\0') + result = strdup(coder->ins); + + else + asprintf(&result, "%s%c%s", coder->ins, coder->separator, coder->raw_details); + + return result; + +} + +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* * +* Description : Fournit la désignation complète d'une instruction. * +* * +* Retour : Désignation complète à libérer de la mémoire. * +* * +* Remarques : - * +* * +******************************************************************************/ + +char *get_coder_code_name(const rented_coder *coder) +{ + char *result; /* Désignation à retourner */ + char *keyword; /* Mot clef appelable en code */ + char *details; /* Compléments de distinction */ + + keyword = make_callable(coder->ins, false); + + if (coder->separator == '\0') + result = keyword; + + else + { + details = make_callable(coder->raw_details, true); + + asprintf(&result, "%s%s", keyword, details); + + free(keyword); + + free(details); + + } + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* * +* Description : Fournit le gestionnaire des définitions d'identifiant. * +* * +* Retour : Structure assurant la définition d'identifiant. * +* * +* Remarques : - * +* * +******************************************************************************/ + +instr_id *get_coder_instruction_id(const rented_coder *coder) +{ + return coder->id; + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* * +* Description : Fournit le gestionnaire de description d'identifiant. * +* * +* Retour : Structure assurant la description d'identifiant. * +* * +* Remarques : - * +* * +******************************************************************************/ + +instr_desc *get_coder_instruction_desc(const rented_coder *coder) +{ + return coder->desc; + +} + + /* ---------------------------------------------------------------------------------- */ /* REPRESENTATION D'ENCODAGES */ @@ -400,7 +505,7 @@ void save_notes_for_coder(rented_coder *coder, char *copy, char *ins, char sep, /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * * * * Description : Fournit un lien vers les spécifications courantes. * * * @@ -448,66 +553,58 @@ void push_encoding_spec(rented_coder *coder, char *prefix, unsigned int index) } - -/* ---------------------------------------------------------------------------------- */ -/* GENERATIONS DE CODE SOURCE */ -/* ---------------------------------------------------------------------------------- */ - - /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* Paramètres : coder = gestion automatique de l'écriture de code. * +* enc_name = désignation du type d'encodage visé. * * * -* Description : S'assure de la présence du répertoire de sortie du code. * +* Description : Détermine le nombre de bits analysés lors d'un désassemblage.* * * -* Retour : Bilan de l'opération. * +* Retour : Nombre de bits interprété. * * * * Remarques : - * * * ******************************************************************************/ -static bool check_gen_dir(const rented_coder *coder) +static unsigned int get_bit_width_for_encoding_spec(const rented_coder *coder, const string_exch *enc_name) { - bool has_gen; /* Répertoire de sortie présent*/ - int ret; /* Bilan d'un appel externe */ + unsigned int result; /* Taille à retourner */ + size_t i; /* Boucle de parcours */ + encoding_spec *spec; /* Définition à traiter */ + coding_bits *bits; /* Gestionnaire de bits */ - has_gen = (access(".gen", F_OK) == 0); + result = -1; - if (has_gen) + for (i = 0; i < coder->specs_count; i++) { - ret = access(".gen", W_OK | X_OK); - if (ret == -1) - { - perror("access()"); - return false; - } + spec = coder->specs[i]; - } - else - { - ret = mkdir(".gen", 0777); - if (ret != 0) - { - perror("mkdir()"); - return false; - } + if (!has_encoding_spec_prefix(spec, enc_name->src)) + continue; + + bits = get_bits_in_encoding_spec(spec); + result = count_coded_bits(bits); + break; } - return true; + /** + * Rien n'a été trouvé à faire... + * Cette situation doit normalement être écartée par l'appelant, + * afin d'éviter de constituer des fichiers vides. + */ + assert(result != -1); + + return result; } /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * -* fd = descripteur de flux ouvert en écriture. * -* prefix = type d'encodage à répercuter sur le nom de fichier. * -* name = nom brut du fichier à ouvrir. * -* ext = extension à donner au fichier à ouvrir. * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * * * -* Description : Imprime dans un flux donné un commentaire de propriété. * +* Description : Marque une instruction comme non utilisée. * * * * Retour : - * * * @@ -515,69 +612,59 @@ static bool check_gen_dir(const rented_coder *coder) * * ******************************************************************************/ -static void write_owner_comments(const rented_coder *coder, int fd, const char *prefix, const char *name, char ext) +void mark_coder_as_useless(rented_coder *coder) { - dprintf(fd, "\n"); + coder->useless = true; - dprintf(fd, "/* Chrysalide - Outil d'analyse de fichiers binaires\n"); - dprintf(fd, " * %s%s.%c - traduction d'instructions ARMv7\n", prefix, name, ext); - dprintf(fd, " *\n"); - dprintf(fd, " * %s\n", coder->copyright); - dprintf(fd, " *\n"); - dprintf(fd, " * This file is part of Chrysalide.\n"); - dprintf(fd, " *\n"); - dprintf(fd, " * Chrysalide is free software; you can redistribute it and/or modify\n"); - dprintf(fd, " * it under the terms of the GNU General Public License as published by\n"); - dprintf(fd, " * the Free Software Foundation; either version 3 of the License, or\n"); - dprintf(fd, " * (at your option) any later version.\n"); - dprintf(fd, " *\n"); - dprintf(fd, " * Chrysalide is distributed in the hope that it will be useful,\n"); - dprintf(fd, " * but WITHOUT ANY WARRANTY; without even the implied warranty of\n"); - dprintf(fd, " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"); - dprintf(fd, " * GNU General Public License for more details.\n"); - dprintf(fd, " *\n"); - dprintf(fd, " * You should have received a copy of the GNU General Public License\n"); - dprintf(fd, " * along with Foobar. If not, see <http://www.gnu.org/licenses/>.\n"); - dprintf(fd, " */\n"); +} - dprintf(fd, "\n"); - dprintf(fd, "\n"); -} + +/* ---------------------------------------------------------------------------------- */ +/* GENERATIONS DE CODE SOURCE */ +/* ---------------------------------------------------------------------------------- */ /****************************************************************************** * * * Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * * prefix = type d'encodage à répercuter sur le nom de fichier. * -* name = nom brut du fichier à ouvrir. * -* ext = extension à donner au fichier à ouvrir. * +* new = dit si l'opération a abouti à une création. [OUT] * * * -* Description : Construit un chemin d'accès à un modèle de fichier de code. * +* Description : Ouvre un fichier principal en écriture pour y placer du code.* * * -* Retour : Chaîne de caractères à libérer de la mémoire après usage. * +* Retour : Descripteur du fichier ouvert ou -1 en cas d'échec. * * * * Remarques : - * * * ******************************************************************************/ -static char *build_template_filename(const rented_coder *coder, const char *prefix, const char *name, char ext) +static int open_instr_header_file(const rented_coder *coder, const output_info *info, const char *prefix, bool *new) { - char *result; /* Chaîne construite à renvoyer*/ - size_t length; /* Taille du nom de fichier */ + int result; /* Descripteur à retourner */ + char *pathname; /* Chemin d'accès à constituer */ + int ret; /* Test d'existence du fichier */ + int flags; /* Mode d'accès au fichier */ - if (prefix == NULL) - { - length = strlen(".gen") + 1 + strlen("template") + 1 + strlen(name) + 3; - result = (char *)calloc(length, sizeof(char)); - snprintf(result, length, ".gen/%s.tmpl.%c", name, ext); - } + if (prefix != NULL) + asprintf(&pathname, "%s%s_opcodes.h", info->directory, prefix); else - { - length = strlen(".gen") + 1 + strlen("template") + 1 + strlen(prefix) + 1 + strlen(name) + 3; - result = (char *)calloc(length, sizeof(char)); - snprintf(result, length, ".gen/%s.%s.tmpl.%c", prefix, name, ext); - } + asprintf(&pathname, "%sopcodes.h", info->directory); + + ret = access(pathname, F_OK); + + *new = (ret != 0); + + if (*new) + flags = O_WRONLY | O_CREAT; + else + flags = O_WRONLY | O_APPEND; + + result = open(pathname, flags, 0644); + if (result == -1) perror("open()"); + + free(pathname); return result; @@ -587,320 +674,365 @@ static char *build_template_filename(const rented_coder *coder, const char *pref /****************************************************************************** * * * Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * * prefix = type d'encodage à répercuter sur le nom de fichier. * -* name = nom brut du fichier à ouvrir. * -* ext = extension à donner au fichier à ouvrir. * +* new = dit si l'opération a abouti à une création. [OUT] * * * -* Description : Définit un modèle d'en-tête de définitions. * +* Description : Ouvre un fichier principal en écriture pour y placer du code.* * * -* Retour : Bilan de l'opération. * +* Retour : Descripteur du fichier ouvert ou -1 en cas d'échec. * * * * Remarques : - * * * ******************************************************************************/ -static bool create_template_file(const rented_coder *coder, const char *prefix, const char *name, char ext) +static int open_instr_code_file(const rented_coder *coder, const output_info *info, const char *prefix, bool *new) { + int result; /* Descripteur à retourner */ + char *group; /* Regroupement des similarités*/ + char *sep; /* Eventuelle séparation */ char *pathname; /* Chemin d'accès à constituer */ - bool exist; /* Note une présence établie */ - int fd; /* Flux ouvert pour création */ - const char *valid_prefix; /* Prefix vide au besoin */ - char *uprefix; /* Préfixe en majuscule */ - char *uname; /* Nom en majuscule */ - - if (!check_gen_dir(coder)) - return false; + int ret; /* Test d'existence du fichier */ + int flags; /* Mode d'accès au fichier */ - pathname = build_template_filename(coder, prefix, name, ext); - - exist = (access(pathname, W_OK) == 0); - if (exist) - { - free(pathname); - return true; - } + group = strdup(coder->ins); - fd = open(pathname, O_WRONLY | O_CREAT/* | O_TRUNC*/, 0644); - if (fd == -1) perror("open()"); + sep = index(group, '-'); - free(pathname); - - if (fd != -1) - { - valid_prefix = prefix != NULL ? prefix : ""; - - write_owner_comments(coder, fd, valid_prefix, name, ext); - - if (ext == 'h') - { - uprefix = make_string_upper(strdup(valid_prefix)); - uname = make_string_upper(strdup(name)); + if (sep != NULL) + *sep = '\0'; - dprintf(fd, "#ifndef %s_%s%s_H\n", coder->header, uprefix, uname); - dprintf(fd, "#define %s_%s%s_H\n", coder->header, uprefix, uname); + if (prefix != NULL) + asprintf(&pathname, "%s%s_%s.c", info->directory, prefix, group); + else + asprintf(&pathname, "%s%s.c", info->directory, group); - free(uprefix); - free(uname); + free(group); - dprintf(fd, "\n"); - dprintf(fd, "\n"); - dprintf(fd, "##INCLUDES##\n"); - dprintf(fd, "\n"); - dprintf(fd, "\n"); - dprintf(fd, "\n"); + ret = access(pathname, F_OK); - } - else - { - dprintf(fd, "#include \"%sopcodes.h\"\n", valid_prefix); - dprintf(fd, "\n"); - dprintf(fd, "##INCLUDES##\n"); + *new = (ret != 0); - } + if (*new) + flags = O_WRONLY | O_CREAT; + else + flags = O_WRONLY | O_APPEND; - close(fd); + result = open(pathname, flags, 0644); + if (result == -1) perror("open()"); - } + free(pathname); - return (fd != -1); + return result; } /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * -* intput = fichier d'entrée initial à référencer. * -* prefix = type d'encodage à répercuter sur le nom de fichier. * -* name = nom brut du fichier à ouvrir. * -* ext = extension à donner au fichier à ouvrir. * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * +* name = nom du fichier ciblé par l'opération. * +* new = indique si l'opération a créé le fichier ciblé. [OUT]* * * -* Description : Construit un chemin d'accès à un fichier de code source. * +* Description : Ouvre un fichier global en écriture pour y placer du code. * * * -* Retour : Chaîne de caractères à libérer de la mémoire après usage. * +* Retour : Descripteur du fichier ouvert ou -1 en cas d'échec. * * * * Remarques : - * * * ******************************************************************************/ -static char *build_code_filename(const rented_coder *coder, const char *input, const char *prefix, const char *name, char ext) +static int open_global_header_file(const rented_coder *coder, const output_info *info, const char *name, bool *new) { - char *result; /* Chaîne construite à renvoyer*/ - char *orig; /* Fichier d'origine tronqué */ - char *point; /* Position d'un point */ - size_t length; /* Taille du nom de fichier */ + int result; /* Descripteur à retourner */ + char *pathname; /* Chemin d'accès à constituer */ + int ret; /* Test d'existence du fichier */ + int flags; /* Mode d'accès au fichier */ - orig = strdup(input); + asprintf(&pathname, "%s%s.h", info->directory, name); - point = strstr(orig, "."); - if (point != NULL) *point = '\0'; + ret = access(pathname, F_OK); - if (prefix == NULL) - { - length = strlen(".gen") + 1 + strlen(orig) + 1 + strlen(name) + 3; - result = (char *)calloc(length, sizeof(char)); - snprintf(result, length, ".gen/%s.%s.%c", orig, name, ext); - } + *new = (ret != 0); + + if (*new) + flags = O_WRONLY | O_CREAT; else - { - length = strlen(".gen") + 1 + strlen(orig) + 1 + strlen(prefix) + 1 + strlen(name) + 3; - result = (char *)calloc(length, sizeof(char)); - snprintf(result, length, ".gen/%s.%s.%s.%c", orig, prefix, name, ext); - } + flags = O_WRONLY | O_APPEND; + + result = open(pathname, flags, 0644); + if (result == -1) perror("open()"); - free(orig); + free(pathname); return result; } + /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement de l'humain. * -* intput = fichier d'entrée initial à référencer. * -* prefix = type d'encodage à répercuter sur le nom de fichier. * -* name = nom brut du fichier à ouvrir. * -* ext = extension à donner au fichier à ouvrir. * +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* info = précisions quant à la génération. * +* name = nom du fichier ciblé par l'opération. * +* msg = complément d'information à faire paraître. * * * -* Description : Ouvre un fichier en écriture pour y placer du code. * +* Description : Imprime dans un flux donné un commentaire de propriété. * * * -* Retour : Descripteur du fichier ouvert ou -1 en cas d'échec. * +* Retour : - * * * * Remarques : - * * * ******************************************************************************/ -static int create_code_file(const rented_coder *coder, const char *input, const char *prefix, const char *name, char ext) +static void write_header_file_license(int fd, const output_info *info, const char *name, const char *msg) { - int result; /* Descripteur à retourner */ - char *pathname; /* Chemin d'accès à constituer */ - - if (!check_gen_dir(coder)) - return -1; + time_t seconds; /* Temps écoulé depuis T0 */ + struct tm cur_date; /* Informations sur la date */ - pathname = build_code_filename(coder, input, prefix, name, ext); + time(&seconds); + localtime_r(&seconds, &cur_date); - result = open(pathname, O_WRONLY | O_CREAT | O_TRUNC, 0644); - if (result == -1) perror("open()"); + dprintf(fd, "\n"); - free(pathname); + dprintf(fd, "/* Chrysalide - Outil d'analyse de fichiers binaires\n"); + dprintf(fd, " * %s.h - %s %s\n", name, msg, info->arch); + dprintf(fd, " *\n"); + dprintf(fd, " * Copyright (C) %d Cyrille Bagard\n", 1900 + cur_date.tm_year); + dprintf(fd, " *\n"); + dprintf(fd, " * This file is part of Chrysalide.\n"); + dprintf(fd, " *\n"); + dprintf(fd, " * Chrysalide is free software; you can redistribute it and/or modify\n"); + dprintf(fd, " * it under the terms of the GNU General Public License as published by\n"); + dprintf(fd, " * the Free Software Foundation; either version 3 of the License, or\n"); + dprintf(fd, " * (at your option) any later version.\n"); + dprintf(fd, " *\n"); + dprintf(fd, " * Chrysalide is distributed in the hope that it will be useful,\n"); + dprintf(fd, " * but WITHOUT ANY WARRANTY; without even the implied warranty of\n"); + dprintf(fd, " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"); + dprintf(fd, " * GNU General Public License for more details.\n"); + dprintf(fd, " *\n"); + dprintf(fd, " * You should have received a copy of the GNU General Public License\n"); + dprintf(fd, " * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.\n"); + dprintf(fd, " */\n"); - return result; + dprintf(fd, "\n"); + dprintf(fd, "\n"); } /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement de l'humain.* +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* info = précisions quant à la génération. * +* name = nom du fichier ciblé par l'opération. * +* copyright = droits d'auteur à faire valoir. * * * -* Description : Débute la définition des fonctions issues des spécifications.* +* Description : Imprime dans un flux donné un commentaire de propriété. * * * -* Retour : Bilan de l'opération. * +* Retour : - * * * * Remarques : - * * * ******************************************************************************/ -bool dump_all_routines_using_coder(const rented_coder *coder) +static void write_code_file_license(int fd, const output_info *info, const char *name, const char *copyright) { - bool result; /* Bilan à retourner */ - size_t i; /* Boucle de parcours #1 */ - const string_exch *encoding; /* Type d'encodage visé */ - size_t j; /* Boucle de parcours #2 */ - char *remove; /* Chemin de suppression */ - int header_fd; /* Fichier de déclarations */ - char *dash; /* Présence d'un tiret ? */ - char *filename; /* Nom de fichier commun */ - int code_fd; /* Fichier de définitions */ + dprintf(fd, "\n"); - result = true; + dprintf(fd, "/* Chrysalide - Outil d'analyse de fichiers binaires\n"); + dprintf(fd, " * %s.c - traduction d'instructions %s\n", name, info->arch); + dprintf(fd, " *\n"); + dprintf(fd, " * %s\n", copyright); + dprintf(fd, " *\n"); + dprintf(fd, " * This file is part of Chrysalide.\n"); + dprintf(fd, " *\n"); + dprintf(fd, " * Chrysalide is free software; you can redistribute it and/or modify\n"); + dprintf(fd, " * it under the terms of the GNU General Public License as published by\n"); + dprintf(fd, " * the Free Software Foundation; either version 3 of the License, or\n"); + dprintf(fd, " * (at your option) any later version.\n"); + dprintf(fd, " *\n"); + dprintf(fd, " * Chrysalide is distributed in the hope that it will be useful,\n"); + dprintf(fd, " * but WITHOUT ANY WARRANTY; without even the implied warranty of\n"); + dprintf(fd, " * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\n"); + dprintf(fd, " * GNU General Public License for more details.\n"); + dprintf(fd, " *\n"); + dprintf(fd, " * You should have received a copy of the GNU General Public License\n"); + dprintf(fd, " * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>.\n"); + dprintf(fd, " */\n"); - for (i = 0; i < count_encodings(coder->pp) && result; i++) - { - encoding = find_encoding(coder->pp, i); + dprintf(fd, "\n"); + dprintf(fd, "\n"); - /* On s'assure qu'il existe bien une version pour l'encodage visé... */ +} - for (j = 0; j < coder->specs_count; j++) - if (has_encoding_spec_prefix(coder->specs[j], encoding->src)) - break; - /* Suppressions ? */ - if (j == coder->specs_count) - { - /* Fichier de déclarations */ +/****************************************************************************** +* * +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* info = précisions quant à la génération. * +* prefix = préfixe lié à une sous-branche de l'architecture. * +* * +* Description : Initialise le contenu utile du fichier des instructions. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ - /* - remove = build_template_filename(coder, encoding->dest, "opcodes", 'h'); - unlink(remove); - free(remove); - */ +static void init_coder_opcodes_file(int fd, const output_info *info, const char *prefix) +{ + char *sub; /* Sous-partie à intégrer */ - remove = build_code_filename(coder, coder->input, encoding->dest, "opcodes", 'h'); - unlink(remove); - free(remove); + if (prefix != NULL) + { + sub = strdup(prefix); + make_string_upper(sub); - /* Fichier de définitions */ + dprintf(fd, "#ifndef _%s_%s_OPCODES_H\n", info->guard, sub); + dprintf(fd, "#define _%s_%s_OPCODES_H\n", info->guard, sub); - dash = strchr(coder->ins, '-'); + free(sub); - if (dash == NULL) - { - /* - remove = build_template_filename(coder, encoding->dest, coder->ins, 'c'); - unlink(remove); - free(remove); - */ + } - remove = build_code_filename(coder, coder->input, encoding->dest, coder->ins, 'c'); - unlink(remove); - free(remove); + else + { + dprintf(fd, "#ifndef _%s_OPCODES_H\n", info->guard); + dprintf(fd, "#define _%s_OPCODES_H\n", info->guard); + } - } + dprintf(fd, "\n"); + dprintf(fd, "\n"); - else - { - filename = strdup(coder->ins); + dprintf(fd, "##INCLUDES##\n"); - dash = strchr(filename, '-'); - *dash = '\0'; + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); - /* - remove = build_template_filename(coder, encoding->dest, filename, 'c'); - unlink(remove); - free(remove); - */ +} - remove = build_code_filename(coder, coder->input, encoding->dest, filename, 'c'); - unlink(remove); - free(remove); - } +/****************************************************************************** +* * +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* prefix = type d'encodage à répercuter sur un nom de fichier. * +* * +* Description : Initialise le contenu utile d'un fichier d'instructions. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ - } +static void init_coder_code_file(int fd, const char *prefix) +{ + if (prefix != NULL) + dprintf(fd, "#include \"%s_opcodes.h\"\n", prefix); + else + dprintf(fd, "#include \"opcodes.h\"\n"); - /* Créations ? */ - else - { - /* Fichier de déclarations */ + dprintf(fd, "\n"); + dprintf(fd, "\n"); - if (!create_template_file(coder, encoding->dest, "opcodes", 'h')) - return false; + dprintf(fd, "##INCLUDES##\n"); - header_fd = create_code_file(coder, coder->input, encoding->dest, "opcodes", 'h'); - if (header_fd == -1) return false; + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); - /* Fichier de définitions */ +} - dash = strchr(coder->ins, '-'); - if (dash == NULL) - { - if (!create_template_file(coder, encoding->dest, coder->ins, 'c')) - return false; +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * +* * +* Description : Génère ou complète un fichier contenant le code C principal. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ - code_fd = create_code_file(coder, coder->input, encoding->dest, coder->ins, 'c'); +bool output_coder_body(const rented_coder *coder, const output_info *info) +{ + bool result; /* Bilan à retourner */ + size_t i; /* Boucle de parcours #1 */ + const string_exch *enc_name; /* Type d'encodage visé */ + size_t j; /* Boucle de parcours #2 */ + int header_fd; /* Fichier de déclarations */ + char *file; /* Nom de fichier final */ + bool header_new; /* Note une création d'entête */ + int code_fd; /* Fichier de définitions */ + bool code_new; /* Note une création de code */ - } + result = true; - else + for (i = 0; i < count_encodings(coder->pp) && result; i++) + { + enc_name = find_encoding(coder->pp, i); + + for (j = 0; j < coder->specs_count; j++) + { + /* On s'assure qu'il existe bien une version pour l'encodage visé... */ + if (!has_encoding_spec_prefix(coder->specs[j], enc_name->src)) + continue; + + header_fd = open_instr_header_file(coder, info, enc_name->dest, &header_new); + if (header_fd == -1) { - filename = strdup(coder->ins); + result = false; + goto ocb_exit; + } - dash = strchr(filename, '-'); - *dash = '\0'; + if (header_new) + { + if (enc_name->dest == NULL) + file = strdup("opcodes"); + else + asprintf(&file, "%s_opcodes", enc_name->dest); - if (!create_template_file(coder, encoding->dest, filename, 'c')) - return false; + write_header_file_license(header_fd, info, file, "prototypes pour la traduction d'instructions"); - code_fd = create_code_file(coder, coder->input, encoding->dest, filename, 'c'); + free(file); - free(filename); + init_coder_opcodes_file(header_fd, info, enc_name->dest); } + code_fd = open_instr_code_file(coder, info, enc_name->dest, &code_new); if (code_fd == -1) { - close(header_fd); + result = false; + goto ocb_exit; + } - /* - remove = build_template_filename(coder, encoding->dest, "opcodes", 'h'); - unlink(remove); - free(remove); - */ + if (code_new) + { + if (enc_name->dest == NULL) + file = strdup(coder->ins); + else + asprintf(&file, "%s_%s", enc_name->dest, coder->ins); - remove = build_code_filename(coder, coder->input, encoding->dest, "opcodes", 'h'); - unlink(remove); - free(remove); + write_code_file_license(code_fd, info, file, coder->copyright); - return false; + free(file); - } + init_coder_code_file(code_fd, enc_name->dest); - /* Production de code... */ + } + else + dprintf(code_fd, "\n"); - switch (coder->type) + switch (info->type) { case IOT_UNDEFINED: assert(false); @@ -908,22 +1040,56 @@ bool dump_all_routines_using_coder(const rented_coder *coder) break; case IOT_RAW: - result = dump_all_matching_specs_in_coder(coder, encoding, header_fd, code_fd); + result = output_coder_raw(coder, info, enc_name, coder->specs[j], header_fd, code_fd); break; case IOT_FORMAT: - result = dump_all_matching_specs_from_format(coder, encoding, header_fd, code_fd); + assert(enc_name->dest == NULL); + result = output_coder_format(coder, info, enc_name, coder->specs[j], header_fd, code_fd); break; } - close(header_fd); - close(code_fd); + } + + /* La suite ne concerne que les formats bruts aboutis... */ + if (!result) break; + if (info->type != IOT_RAW) continue; + + for (j = 0; j < coder->specs_count; j++) + { + /* On s'assure de retrouver une version de l'encodage visé juste avant... */ + if (!has_encoding_spec_prefix(coder->specs[j], enc_name->src)) + continue; + + header_fd = open_instr_header_file(coder, info, enc_name->dest, &header_new); + if (header_fd == -1) + { + result = false; + goto ocb_exit; + } + + assert(!header_new); + + code_fd = open_instr_code_file(coder, info, enc_name->dest, &code_new); + if (code_fd == -1) + { + result = false; + goto ocb_exit; + } + + assert(!code_new); + + result = output_coder_main_raw(coder, info, enc_name, header_fd, code_fd); + + break; } } + ocb_exit: + return result; } @@ -931,12 +1097,39 @@ bool dump_all_routines_using_coder(const rented_coder *coder) /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement d'humain. * +* Paramètres : fd = flux ouvert en écriture. * +* arch = architecture en cours de traitement. * +* sub = encodage choisi comme sous-ensemble d'architecture. * +* name = désignation complète d'une instruction. * +* * +* Description : Centralise l'impression du nom de fonction de désassemblage. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void write_read_function_name(int fd, const char *arch, const string_exch *sub, const char *name) +{ + if (sub->dest == NULL) + dprintf(fd, "%s_read_instr_%s", arch, name); + else + dprintf(fd, "%s_read_%s_instr_%s", arch, sub->dest, name); + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion automatique de l'écriture de code. * +* info = précisions quant à la génération. * +* enc_name = désignation du type d'encodage visé. * * encoding = sélection de l'encodage à traiter. * * hfd = flux ouvert en écriture pour les déclarations. * * cfd = flux ouvert en écriture pour les définitions. * * * -* Description : Ecrit une partie des fonctions issues des spécifications. * +* Description : Génère ou complète un fichier contenant le code C principal. * * * * Retour : Bilan de l'opération. * * * @@ -944,55 +1137,152 @@ bool dump_all_routines_using_coder(const rented_coder *coder) * * ******************************************************************************/ -static bool dump_all_matching_specs_in_coder(const rented_coder *coder, const string_exch *encoding, int hfd, int cfd) +static bool output_coder_raw(const rented_coder *coder, const output_info *info, const string_exch *enc_name, const encoding_spec *encoding, int hfd, int cfd) { bool result; /* Bilan à retourner */ - char *keyword; /* Mot clef appelable en code */ - unsigned int wide; /* Taille des mots */ - size_t i; /* Boucle de parcours */ - encoding_spec *spec; /* Définition à traiter */ + char *arch; /* Architecture à traiter */ + char *name; /* Désignation à manipuler */ + char *prefix; /* Préfixe employé en suffixe */ coding_bits *bits; /* Gestionnaire de bits */ + unsigned int wide; /* Taille des mots */ size_t maxlen; /* Taille à compléter */ - result = true; + arch = strdup(info->arch_cn); + make_string_lower(arch); - keyword = make_callable(coder->ins, false); + name = get_coder_code_name(coder); - /* Recherche de la taille des mots */ + prefix = build_encoding_spec_prefix(encoding); - wide = -1; + bits = get_bits_in_encoding_spec(encoding); + wide = count_coded_bits(bits); - for (i = 0; i < coder->specs_count; i++) + /* Désassemblage : déclaration */ + + if (0 /* TODO : export seulement */) { - spec = coder->specs[i]; + dprintf(hfd, "/* Décode une forme d'instruction de type '%s'. */\n", coder->ins); - if (!has_encoding_spec_prefix(spec, encoding->src)) - continue; + dprintf(hfd, "GArchInstruction *"); + write_read_function_name(hfd, arch, enc_name, name); + dprintf(hfd, "_%s", prefix); - bits = get_bits_in_encoding_spec(spec); - wide = count_coded_bits(bits); - break; + dprintf(hfd, "("); + dprintf(hfd, "uint%u_t raw", wide); + dprintf(hfd, ");\n"); + + dprintf(hfd, "\n"); } - /** - * Rien n'a été trouvé à faire... - * Cette situation doit normalement être écartée par l'appelant, - * afin d'éviter de constituer des fichiers vides. - */ - assert(wide != -1); + /* Désassemblage : définitions */ + + dprintf(cfd, "/******************************************************************************\n"); + dprintf(cfd, "* *\n"); + dprintf(cfd, "* Paramètres : raw = données brutes à analyser. *\n"); + dprintf(cfd, "* *\n"); + dprintf(cfd, "* Description : Décode une forme d'instruction de type '%s'.", coder->ins); + + maxlen = 20 - strlen(coder->ins); + + if (maxlen < 20) + dprintf(cfd, "%*s\n", (int)maxlen, "*"); + else + dprintf(cfd, "*\n"); + + dprintf(cfd, "* *\n"); + dprintf(cfd, "* Retour : Instruction mise en place ou NULL en cas d'échec. *\n"); + dprintf(cfd, "* *\n"); + dprintf(cfd, "* Remarques : - *\n"); + dprintf(cfd, "* *\n"); + dprintf(cfd, "******************************************************************************/\n"); + + dprintf(cfd, "\n"); + + if (1 /* TODO : si pas exportée */) + dprintf(cfd, "static "); + + dprintf(cfd, "GArchInstruction *"); + write_read_function_name(cfd, arch, enc_name, name); + dprintf(cfd, "_%s", prefix); + + dprintf(cfd, "("); + dprintf(cfd, "uint%u_t raw", wide); + dprintf(cfd, ")"); + + dprintf(cfd, "\n"); + dprintf(cfd, "{"); + dprintf(cfd, "\n"); + + result = write_encoding_spec_raw_disass(encoding, cfd, arch, coder->id, coder->pp); + + dprintf(cfd, "}\n"); + dprintf(cfd, "\n"); + + /* Conclusion */ + + free(prefix); + + free(name); + + free(arch); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion automatique de l'écriture de code. * +* info = précisions quant à la génération. * +* enc_name = désignation du type d'encodage visé. * +* hfd = flux ouvert en écriture pour les déclarations. * +* cfd = flux ouvert en écriture pour les définitions. * +* * +* Description : Génère ou complète un fichier contenant le code C principal. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +static bool output_coder_main_raw(const rented_coder *coder, const output_info *info, const string_exch *enc_name, int hfd, int cfd) +{ + bool result; /* Bilan à retourner */ + char *arch; /* Architecture à traiter */ + char *name; /* Désignation à manipuler */ + unsigned int wide; /* Taille des mots */ + size_t maxlen; /* Taille à compléter */ + bool first; /* Note un premier appel */ + size_t i; /* Boucle de parcours */ + char *prefix; /* Préfixe employé en suffixe */ + + result = false; + + arch = strdup(info->arch_cn); + make_string_lower(arch); + + name = get_coder_code_name(coder); + + wide = get_bit_width_for_encoding_spec(coder, enc_name); /* Désassemblage : déclaration */ dprintf(hfd, "/* Décode une instruction de type '%s'. */\n", coder->ins); - dprintf(hfd, "GArchInstruction *%s_read_%sinstr_%s%s(uint%u_t);\n", - coder->arch, encoding->dest, keyword, coder->details, wide); + + dprintf(hfd, "GArchInstruction *"); + write_read_function_name(hfd, arch, enc_name, name); + + dprintf(hfd, "("); + dprintf(hfd, "uint%u_t raw", wide); + dprintf(hfd, ");\n"); + dprintf(hfd, "\n"); /* Désassemblage : définitions */ - dprintf(cfd, "\n"); - dprintf(cfd, "/******************************************************************************\n"); dprintf(cfd, "* *\n"); dprintf(cfd, "* Paramètres : raw = données brutes à analyser. *\n"); @@ -1006,7 +1296,7 @@ static bool dump_all_matching_specs_in_coder(const rented_coder *coder, const st else dprintf(cfd, "*\n"); - dprintf(cfd, " *\n"); + dprintf(cfd, "* *\n"); dprintf(cfd, "* Retour : Instruction mise en place ou NULL en cas d'échec. *\n"); dprintf(cfd, "* *\n"); dprintf(cfd, "* Remarques : - *\n"); @@ -1015,27 +1305,55 @@ static bool dump_all_matching_specs_in_coder(const rented_coder *coder, const st dprintf(cfd, "\n"); - dprintf(cfd, "GArchInstruction *%s_read_%sinstr_%s%s(uint%u_t raw)", - coder->arch, encoding->dest, keyword, coder->details, wide); + dprintf(cfd, "GArchInstruction *"); + write_read_function_name(cfd, arch, enc_name, name); + + dprintf(cfd, "("); + dprintf(cfd, "uint%u_t raw", wide); + dprintf(cfd, ")"); + dprintf(cfd, "\n"); dprintf(cfd, "{"); dprintf(cfd, "\n"); dprintf(cfd, "\tGArchInstruction *result; /* Instruction créée à renvoyer*/\n"); - - dprintf(cfd, "\n"); - dprintf(cfd, "\tresult = NULL;\n"); dprintf(cfd, "\n"); - for (i = 0; i < coder->specs_count && result; i++) - { - spec = coder->specs[i]; + first = true; - if (!has_encoding_spec_prefix(spec, encoding->src)) + for (i = 0; i < coder->specs_count; i++) + { + if (!has_encoding_spec_prefix(coder->specs[i], enc_name->src)) continue; - result = write_encoding_spec_disass(spec, cfd, coder->arch, encoding->dest, - coder->ins, coder->details, wide, coder->pp); + result = true; + + prefix = build_encoding_spec_prefix(coder->specs[i]); + + if (first) + { + dprintf(cfd, "\tresult = "); + write_read_function_name(cfd, arch, enc_name, name); + dprintf(cfd, "_%s(raw);\n", prefix); + + dprintf(cfd, "\n"); + + first = false; + + } + else + { + dprintf(cfd, "\tif (result == NULL)\n"); + + dprintf(cfd, "\t\tresult = "); + write_read_function_name(cfd, arch, enc_name, name); + dprintf(cfd, "_%s(raw);\n", prefix); + + dprintf(cfd, "\n"); + + } + + free(prefix); } @@ -1045,7 +1363,11 @@ static bool dump_all_matching_specs_in_coder(const rented_coder *coder, const st dprintf(cfd, "}\n"); dprintf(cfd, "\n"); - free(keyword); + /* Conclusion */ + + free(name); + + free(arch); return result; @@ -1054,12 +1376,14 @@ static bool dump_all_matching_specs_in_coder(const rented_coder *coder, const st /****************************************************************************** * * -* Paramètres : coder = gestion par la machine en remplacement d'humain. * +* Paramètres : coder = gestion automatique de l'écriture de code. * +* info = précisions quant à la génération. * +* enc_name = désignation du type d'encodage visé. * * encoding = sélection de l'encodage à traiter. * * hfd = flux ouvert en écriture pour les déclarations. * * cfd = flux ouvert en écriture pour les définitions. * * * -* Description : Ecrit une partie des fonctions issues des spécifications. * +* Description : Génère ou complète un fichier contenant le code C principal. * * * * Retour : Bilan de l'opération. * * * @@ -1067,25 +1391,24 @@ static bool dump_all_matching_specs_in_coder(const rented_coder *coder, const st * * ******************************************************************************/ -static bool dump_all_matching_specs_from_format(const rented_coder *coder, const string_exch *encoding, int hfd, int cfd) +static bool output_coder_format(const rented_coder *coder, const output_info *info, const string_exch *enc_name, const encoding_spec *encoding, int hfd, int cfd) { bool result; /* Bilan à retourner */ - char *keyword; /* Mot clef appelable en code */ + char *arch; /* Architecture à traiter */ + char *name; /* Désignation à manipuler */ size_t maxlen; /* Taille à compléter */ - encoding_spec *spec; /* Définition à traiter */ - keyword = make_callable(coder->ins, false); + arch = strdup(info->arch_cn); + make_string_lower(arch); + + name = get_coder_code_name(coder); /* Désassemblage : déclaration */ dprintf(hfd, "/* Décode une instruction de type '%s'. */\n", coder->ins); - if (encoding->dest == NULL) - dprintf(hfd, "GArchInstruction *%s_read_instr_%s%s", - coder->arch, keyword, coder->details); - else - dprintf(hfd, "GArchInstruction *%s_read_%sinstr_%s%s", - coder->arch, encoding->dest, keyword, coder->details); + dprintf(hfd, "GArchInstruction *"); + write_read_function_name(hfd, arch, enc_name, name); dprintf(hfd, "("); dprintf(hfd, "const GArchProcessor *, GProcContext *, const GBinContent *, "); @@ -1096,8 +1419,6 @@ static bool dump_all_matching_specs_from_format(const rented_coder *coder, const /* Désassemblage : définitions */ - dprintf(cfd, "\n"); - dprintf(cfd, "/******************************************************************************\n"); dprintf(cfd, "* *\n"); dprintf(cfd, "* Paramètres : proc = processeur de l'architecture d'exécution. *\n"); @@ -1115,7 +1436,7 @@ static bool dump_all_matching_specs_from_format(const rented_coder *coder, const else dprintf(cfd, "*\n"); - dprintf(cfd, " *\n"); + dprintf(cfd, "* *\n"); dprintf(cfd, "* Retour : Instruction mise en place ou NULL en cas d'échec. *\n"); dprintf(cfd, "* *\n"); dprintf(cfd, "* Remarques : - *\n"); @@ -1124,12 +1445,8 @@ static bool dump_all_matching_specs_from_format(const rented_coder *coder, const dprintf(cfd, "\n"); - if (encoding->dest == NULL) - dprintf(cfd, "GArchInstruction *%s_read_instr_%s%s", - coder->arch, keyword, coder->details); - else - dprintf(cfd, "GArchInstruction *%s_read_%sinstr_%s%s", - coder->arch, encoding->dest, keyword, coder->details); + dprintf(cfd, "GArchInstruction *"); + write_read_function_name(cfd, arch, enc_name, name); dprintf(cfd, "("); dprintf(cfd, "const GArchProcessor *proc, GProcContext *ctx, const GBinContent *content, "); @@ -1140,20 +1457,523 @@ static bool dump_all_matching_specs_from_format(const rented_coder *coder, const dprintf(cfd, "{"); dprintf(cfd, "\n"); - assert(coder->specs_count == 1); + result = write_encoding_spec_format_disass(encoding, cfd, arch, coder->id, info->fmt_prefix); - spec = coder->specs[0]; + dprintf(cfd, "}\n"); + dprintf(cfd, "\n"); - assert(has_encoding_spec_prefix(spec, encoding->src)); + /* Conclusion */ - result = write_encoding_spec_format_disass(spec, cfd, coder->arch, encoding->dest, - coder->ins, coder->separator, coder->raw_details, - coder->pp, coder->const_prefix); + free(name); - dprintf(cfd, "}\n"); - dprintf(cfd, "\n"); + free(arch); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : pathname = chemin d'accès au fichier à traiter. * +* info = précisions quant à la génération. * +* * +* Description : Finalise le contenu utile du fichier des instructions. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool fini_coder_opcodes_file(const char *pathname, const output_info *info) +{ + bool result; /* Bilan à retourner */ + int fd; /* Flux ouvert en écriture */ + char *temp; /* Zone de travail temporaire */ + char *base; /* Identification de fichier */ + + result = false; + + fd = open(pathname, O_WRONLY | O_APPEND, 0644); + if (fd == -1) + { + perror("open()"); + goto fcif_exit; + } + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + temp = strdup(pathname); + base = basename(temp); + + base[strlen(base) - 2] = '\0'; + + make_string_upper(base); + + dprintf(fd, "#endif /* _%s_%s_H */\n", info->guard, base); + + free(temp); + + result = true; + + fcif_exit: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* info = précisions quant à la génération. * +* * +* Description : Initialise le contenu utile du fichier des identifiants. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void init_coder_identifiers_file(int fd, const output_info *info) +{ + dprintf(fd, "#ifndef _%s_IDENTIFIERS_H\n", info->guard); + dprintf(fd, "#define _%s_IDENTIFIERS_H\n", info->guard); + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + dprintf(fd, "/* Enumération de tous les opcodes */\n"); + dprintf(fd, "typedef enum _%sOpcodes\n", info->arch_cn); + dprintf(fd, "{\n"); + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * +* * +* Description : Génère ou complète un fichier constituant les identifiants. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool output_coder_identifier(const rented_coder *coder, const output_info *info) +{ + bool result; /* Bilan à retourner */ + bool created; /* Note une création */ + int fd; /* Flux ouvert en écriture */ + char *name; /* Désignation à manipuler */ + instr_id *id; /* Gestionnaire d'identifiant */ + unsigned int iid; /* Identifiant unique attribué */ + char *constant; /* Définition d'une constante */ + char *comment; /* Contenu du commentaire */ + + result = false; + + /* Ouverture de la destination */ + + fd = open_global_header_file(coder, info, "identifiers", &created); + if (fd == -1) goto oci_exit; + + if (created) + { + write_header_file_license(fd, info, "identifiers", "définition des identifiants uniques pour"); + init_coder_identifiers_file(fd, info); + } + + /* Constitution de la constante */ + + name = get_coder_code_name(coder); + make_string_upper(name); + + asprintf(&constant, "%s_%s,", info->id_prefix, name); + + free(name); + + /* Définition du commentaire */ + + name = get_coder_nominal_name(coder); + + id = get_coder_instruction_id(coder); + iid = get_instruction_id_value(id); + + asprintf(&comment, "%s (0x%0*x)", name, info->id_len, iid); + + free(name); + + /* Impression de la ligne */ + + dprintf(fd, " %-40s/* %-28s*/\n", constant, comment); + + free(constant); + free(comment); + + result = true; + + oci_exit: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : pathname = chemin d'accès au fichier à traiter. * +* info = précisions quant à la génération. * +* * +* Description : Finalise le contenu utile du fichier des identifiants. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool fini_coder_identifiers_file(const char *pathname, const output_info *info) +{ + bool result; /* Bilan à retourner */ + int fd; /* Flux ouvert en écriture */ + + result = false; + + fd = open(pathname, O_WRONLY | O_APPEND, 0644); + if (fd == -1) + { + perror("open()"); + goto fcif_exit; + } + + dprintf(fd, "\n"); + dprintf(fd, " %s_COUNT\n", info->id_prefix); + dprintf(fd, "\n"); + + dprintf(fd, "} %sOpcodes;\n", info->arch_cn); + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + dprintf(fd, "#endif /* _%s_IDENTIFIERS_H */\n", info->guard); + + result = true; + + fcif_exit: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* info = précisions quant à la génération. * +* * +* Description : Initialise le contenu utile du fichier des mots clefs. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void init_coder_keywords_file(int fd, const output_info *info) +{ + char *larch; /* Architecture en minuscules */ + + dprintf(fd, "#ifndef _%s_KEYWORDS_H\n", info->guard); + dprintf(fd, "#define _%s_KEYWORDS_H\n", info->guard); + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "#include \"identifiers.h\"\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + larch = strdup(info->arch_cn); + make_string_lower(larch); + + dprintf(fd, "/* Enumération de tous les mots clefs */\n"); + dprintf(fd, "static char *_%s_keywords[%s_COUNT] = {\n", larch, info->id_prefix); + dprintf(fd, "\n"); + + free(larch); + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * +* * +* Description : Génère ou complète un fichier constituant les mots clefs. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool output_coder_keyword(const rented_coder *coder, const output_info *info) +{ + bool result; /* Bilan à retourner */ + bool created; /* Note une création */ + int fd; /* Flux ouvert en écriture */ + char *name; /* Désignation à manipuler */ + + result = false; + + /* S'il n'y a pas lieu de traiter l'instruction */ + + if (coder->useless) + { + result = true; + goto ock_exit; + } + + /* Ouverture de la destination */ + + fd = open_global_header_file(coder, info, "keywords", &created); + if (fd == -1) goto ock_exit; + + if (created) + { + write_header_file_license(fd, info, "keywords", "définition des mots clefs des instructions"); + init_coder_keywords_file(fd, info); + } + + /* Impression de la colonne */ + + name = get_coder_code_name(coder); + make_string_upper(name); + + dprintf(fd, "\t[%s_%s] = ", info->id_prefix, name); + + free(name); + + /* Impression du mot clef */ + + name = get_coder_nominal_name(coder); + + dprintf(fd, "\"%s\",\n", name); + + free(name); + + result = true; + + ock_exit: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : pathname = chemin d'accès au fichier à traiter. * +* info = précisions quant à la génération. * +* * +* Description : Finalise le contenu utile du fichier des mots clefs. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool fini_coder_keywords_file(const char *pathname, const output_info *info) +{ + bool result; /* Bilan à retourner */ + int fd; /* Flux ouvert en écriture */ + + result = false; + + fd = open(pathname, O_WRONLY | O_APPEND, 0644); + if (fd == -1) + { + perror("open()"); + goto fckf_exit; + } + + dprintf(fd, "\n"); + dprintf(fd, "};\n"); + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + dprintf(fd, "#endif /* _%s_KEYWORDS_H */\n", info->guard); + + result = true; + + fckf_exit: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : fd = flux ouvert en écriture mis à disposition. * +* info = précisions quant à la génération. * +* * +* Description : Initialise le contenu utile du fichier des descriptions. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void init_coder_descriptions_file(int fd, const output_info *info) +{ + char *larch; /* Architecture en minuscules */ + + dprintf(fd, "#ifndef _%s_DESCRIPTIONS_H\n", info->guard); + dprintf(fd, "#define _%s_DESCRIPTIONS_H\n", info->guard); + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "#include \"identifiers.h\"\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + larch = strdup(info->arch_cn); + make_string_lower(larch); + + dprintf(fd, "/* Enumération de tous les mots clefs */\n"); + dprintf(fd, "static char *_%s_descriptions[%s_COUNT] = {\n", larch, info->id_prefix); + dprintf(fd, "\n"); + + free(larch); + +} + + +/****************************************************************************** +* * +* Paramètres : coder = gestion par la machine en remplacement de l'humain. * +* info = précisions quant à la génération. * +* * +* Description : Génère ou complète un fichier constituant les descriptions. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool output_coder_description(const rented_coder *coder, const output_info *info) +{ + bool result; /* Bilan à retourner */ + bool created; /* Note une création */ + int fd; /* Flux ouvert en écriture */ + char *name; /* Désignation à manipuler */ + + result = false; + + /* S'il n'y a pas lieu de traiter l'instruction */ + + if (coder->useless) + { + result = true; + goto ock_exit; + } + + /* Ouverture de la destination */ + + fd = open_global_header_file(coder, info, "descriptions", &created); + if (fd == -1) goto ock_exit; + + if (created) + { + write_header_file_license(fd, info, "descriptions", "définition des descriptions des instructions"); + init_coder_descriptions_file(fd, info); + } + + /* Impression de la colonne */ + + name = get_coder_code_name(coder); + make_string_upper(name); + + dprintf(fd, "\t[%s_%s] = ", info->id_prefix, name); + + free(name); + + /* Impression du mot clef */ + + name = get_coder_nominal_name(coder); + + dprintf(fd, "\""); + + write_instruction_description(coder->desc, fd); + + dprintf(fd, "\",\n"); + + free(name); + + result = true; + + ock_exit: + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : pathname = chemin d'accès au fichier à traiter. * +* info = précisions quant à la génération. * +* * +* Description : Finalise le contenu utile du fichier des descriptions. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool fini_coder_descriptions_file(const char *pathname, const output_info *info) +{ + bool result; /* Bilan à retourner */ + int fd; /* Flux ouvert en écriture */ + + result = false; + + fd = open(pathname, O_WRONLY | O_APPEND, 0644); + if (fd == -1) + { + perror("open()"); + goto fckf_exit; + } + + dprintf(fd, "\n"); + dprintf(fd, "};\n"); + + dprintf(fd, "\n"); + dprintf(fd, "\n"); + dprintf(fd, "\n"); + + dprintf(fd, "#endif /* _%s_DESCRIPTIONS_H */\n", info->guard); + + result = true; - free(keyword); + fckf_exit: return result; diff --git a/tools/d2c/coder.h b/tools/d2c/coder.h index 682dfe6..66ab66c 100644 --- a/tools/d2c/coder.h +++ b/tools/d2c/coder.h @@ -28,8 +28,10 @@ #include <stdbool.h> +#include "encoding.h" #include "pproc.h" -#include "spec.h" +#include "desc/manager.h" +#include "id/manager.h" @@ -41,18 +43,8 @@ typedef struct _rented_coder rented_coder; /* -------------------------- CONSTRUCTION SELON COMMANDES -------------------------- */ -/* Type d'entrée/sortie attendues */ -typedef enum _InputOutputType -{ - IOT_UNDEFINED, /* Type non défini */ - IOT_RAW, /* Lecture de contenu brut */ - IOT_FORMAT /* Définition d'opérandes */ - -} InputOutputType; - - /* Débute la définition d'une fonction de désassemblage. */ -rented_coder *create_coder(void); +rented_coder *create_coder(pre_processor *); /* Supprime le codeur de la mémoire. */ void delete_coder(rented_coder *); @@ -67,10 +59,7 @@ const char *get_coder_input_file(const rented_coder *); void set_coder_input_file(rented_coder *, const char *); /* Spécifie le type de format à prendre en compte (E/S). */ -void set_coder_input_type(rented_coder *, InputOutputType); - -/* Spécifie le répertoire de base pour les sorties de code. */ -void set_coder_output_directory(rented_coder *, const char *); +//void set_coder_input_type(rented_coder *, InputOutputType); /* Détermine l'architecture visée par les traitements. */ void set_coder_arch(rented_coder *, const char *); @@ -81,66 +70,94 @@ void set_coder_header_base(rented_coder *, const char *); /* Définit le préfixe pour les opérandes chargées par format. */ void set_coder_const_prefix(rented_coder *, const char *); -/* Fournit le pré-processeur du compilateur. */ -pre_processor *get_coder_pre_proc(const rented_coder *); -/* Enregistre les contours d'une instruction d'assemblage. */ -void save_notes_for_coder(rented_coder *, char *, char *, char, const char *); +/* ----------------------------- INFORMATIONS GENERALES ----------------------------- */ -/* --------------------------- REPRESENTATION D'ENCODAGES --------------------------- */ +/* Enregistre les contours d'une instruction d'assemblage. */ +void save_notes_for_coder(rented_coder *, char *, char *, char, const char *); +/* Fournit la désignation nominale d'une instruction. */ +char *get_coder_nominal_name(const rented_coder *); -/* Fournit un lien vers les spécifications courantes. */ -encoding_spec *get_current_encoding_spec(const rented_coder *); +/* Fournit la désignation complète d'une instruction. */ +char *get_coder_code_name(const rented_coder *); -/* Enregistre une définition supplémentaire. */ -void push_encoding_spec(rented_coder *, char *, unsigned int); +/* Fournit le gestionnaire des définitions d'identifiant. */ +instr_id *get_coder_instruction_id(const rented_coder *); +/* Fournit le gestionnaire de description d'identifiant. */ +instr_desc *get_coder_instruction_desc(const rented_coder *); -/* --------------------------- GESTION DES CHAMPS DE BITS --------------------------- */ +/* --------------------------- REPRESENTATION D'ENCODAGES --------------------------- */ -/* Note la présence d'un champ remarquable dans une définition. */ -void register_named_field_in_coder(rented_coder *, char *, unsigned int); -/* Note la présence d'un bit invariable dans une définition. */ -void register_bit_in_coder(rented_coder *, int); +/* Fournit un lien vers les spécifications courantes. */ +encoding_spec *get_current_encoding_spec(const rented_coder *); -/* Indique le nombre de bits traités. */ -//unsigned int count_coder_bits(const rented_coder *); +/* Enregistre une définition supplémentaire. */ +void push_encoding_spec(rented_coder *, char *, unsigned int); +/* Marque une instruction comme non utilisée. */ +void mark_coder_as_useless(rented_coder *coder); -/* ---------------------------- SYNTAXE DES INSTRUCTIONS ---------------------------- */ +/* --------------------------- GENERATIONS DE CODE SOURCE --------------------------- */ -/* Enregistre la présence d'un nouvel opérande. */ -void register_syntax_item_in_coder(rented_coder *, char *, bool); +/* Type d'entrée/sortie attendues */ +typedef enum _InputOutputType +{ + IOT_UNDEFINED, /* Type non défini */ + IOT_RAW, /* Lecture de contenu brut */ + IOT_FORMAT /* Définition d'opérandes */ +} InputOutputType; -/* ---------------------------- CONVERSION DES ARGUMENTS ---------------------------- */ +/* Regroupement des informations utiles à la génération */ +typedef struct _output_info +{ + const char *directory; /* Répertoire de destination */ + InputOutputType type; /* Type des définitions (E/S) */ + const char *arch; /* Architecture à traiter */ + const char *arch_cn; /* Nom de code de l'archi. */ + const char *guard; /* Portion de macro globale */ + const char *fmt_prefix; /* Préfixe pour les opérandes */ -/* Enregistre la function de conversion du brut à l'utile. */ -void register_conversion_in_coder(rented_coder *, conv_func *); + const char *id_prefix; /* Préfixe pour les constantes */ + int id_len; /* Largeur des identifiants */ +} output_info; -/* --------------------------- CONDITIONS ET CONSEQUENCES --------------------------- */ +/* Génère ou complète un fichier contenant le code C principal. */ +bool output_coder_body(const rented_coder *, const output_info *); +/* Finalise le contenu utile du fichier des instructions. */ +bool fini_coder_opcodes_file(const char *, const output_info *); +/* Génère ou complète un fichier constituant les identifiants. */ +bool output_coder_identifier(const rented_coder *, const output_info *); +/* Finalise le contenu utile du fichier des identifiants. */ +bool fini_coder_identifiers_file(const char *, const output_info *); +/* Génère ou complète un fichier constituant les mots clefs. */ +bool output_coder_keyword(const rented_coder *, const output_info *); -/* --------------------------- GENERATIONS DE CODE SOURCE --------------------------- */ +/* Finalise le contenu utile du fichier des mots clefs. */ +bool fini_coder_keywords_file(const char *, const output_info *); +/* Génère ou complète un fichier constituant les descriptions. */ +bool output_coder_description(const rented_coder *, const output_info *); -/* Débute la définition des fonctions issues des spécifications. */ -bool dump_all_routines_using_coder(const rented_coder *); +/* Finalise le contenu utile du fichier des descriptions. */ +bool fini_coder_descriptions_file(const char *, const output_info *); diff --git a/tools/d2c/conv/Makefile.am b/tools/d2c/conv/Makefile.am index d2d495b..a22d5f7 100644 --- a/tools/d2c/conv/Makefile.am +++ b/tools/d2c/conv/Makefile.am @@ -26,6 +26,9 @@ libd2cconv_la_SOURCES = \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2cconv_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/conv/manager.c b/tools/d2c/conv/manager.c index 555ea38..33518db 100644 --- a/tools/d2c/conv/manager.c +++ b/tools/d2c/conv/manager.c @@ -29,6 +29,7 @@ #include <malloc.h> #include <stdbool.h> #include <string.h> +#include <unistd.h> #include "../helpers.h" @@ -42,11 +43,6 @@ /* Fonction de conversion */ struct _conv_func { - bool used; /* Conversion utilisée ? */ - bool intermediate; /* Variable intermédiaire ? */ - bool declared; /* Expression déjà déclarée ? */ - bool defined; /* Expression déjà définie ? */ - char *dest; /* Variable de destination */ bool is_expr; /* Choix du contenu réel */ @@ -64,9 +60,18 @@ struct _conv_func }; + bool used_as_inter; /* Variable intermédiaire ? */ + bool used_as_op; /* Opérande finale d'instruct° */ + bool declared; /* Expression déjà déclarée ? */ + bool defined; /* Expression déjà définie ? */ + }; +/* Indique si l'utilisation en intermédiaire est brute ou non. */ +static bool is_conv_func_raw_as_inter(const conv_func *); + + /* ---------------------------- ENSEMBLES DE CONVERSIONS ---------------------------- */ @@ -196,25 +201,6 @@ const char *get_conv_dest_name(const conv_func *func) /****************************************************************************** * * * Paramètres : func = fonction de conversion à consulter. * -* * -* Description : Indique la nature d'une conversion : fonction ou expression ?* -* * -* Retour : Indication sur la constitution interne de la conversion. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool is_conv_func_expression(const conv_func *func) -{ - return func->is_expr; - -} - - -/****************************************************************************** -* * -* Paramètres : func = fonction de conversion à consulter. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * * size = taille déterminée avec précision. [OUT] * @@ -260,8 +246,13 @@ bool mark_conv_func(conv_func *func, bool inter, const coding_bits *bits, const { bool result; /* Bilan à remonter */ - func->used = true; - func->intermediate |= inter; + if (inter) + func->used_as_inter = true; + else + { + assert(!func->is_expr); + func->used_as_op = true; + } if (func->is_expr) result = ensure_arg_expr_content_fully_marked(func->expr, bits, list); @@ -275,69 +266,160 @@ bool mark_conv_func(conv_func *func, bool inter, const coding_bits *bits, const /****************************************************************************** * * -* Paramètres : func = fonction de conversion à manipuler. * -* fd = descripteur d'un flux ouvert en écriture. * -* bits = gestionnaire des bits d'encodage. * -* list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * -* wide = taille des mots décodés. * +* Paramètres : func = fonction de conversion à consulter. * * * -* Description : Déclare les variables associées à une fonction de conversion.* +* Description : Indique si l'utilisation en intermédiaire est brute ou non. * * * -* Retour : Bilan de l'opération. * +* Retour : true si une variable brute est à manipuler, false sinon. * * * * Remarques : - * * * ******************************************************************************/ -bool declare_conv_func(conv_func *func, int fd, const coding_bits *bits, const conv_list *list, const pre_processor *pp, unsigned int wide) +static bool is_conv_func_raw_as_inter(const conv_func *func) { - bool result; /* Bilan à remonter */ + bool result; /* Résultat à faire remonter */ - printf(" -> declaration for '%s': declared ? %d - expr ? %d\n", - func->dest, func->declared, func->is_expr); + if (func->is_expr) + result = true; + else + result = (strcmp(func->name, "UInt") == 0); - assert(func->used); + return result; - /* Si la fonction a déjà été définie lors d'un précédent besoin... */ - if (func->declared) return true; +} - if (func->is_expr) - result = ensure_arg_expr_content_fully_declared(func->expr, fd, bits, list, pp, wide); - else - result = ensure_arg_list_content_fully_declared(func->args, fd, bits, list, pp, wide); - if (result && func->intermediate) - { - if (!func->is_expr && is_operand_producer(pp, func->name)) - dprintf(fd, "\t\tGArchOperand *val_%s;\n", func->dest); - else - dprintf(fd, "\t\tuint%u_t val_%s;\n", wide, func->dest); - } - func->declared = result; +/****************************************************************************** +* * +* Paramètres : func = fonction de conversion à manipuler. * +* fd = descripteur d'un flux ouvert en écriture. * +* inter = note un résultat de conversion comme intermédiaire. * +* * +* Description : Imprime la désignation de la destination d'une conversion. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ - return result; +void write_conv_func(conv_func *func, int fd, bool inter) +{ + bool as_raw; /* Choix logique du format */ + + if (inter) + as_raw = is_conv_func_raw_as_inter(func); + else + as_raw = false; + + if (as_raw) + dprintf(fd, "val_%s", func->dest); + else + dprintf(fd, "op_%s", func->dest); } /****************************************************************************** * * -* Paramètres : func = fonction de conversion à consulter. * +* Paramètres : func = fonction de conversion à manipuler. * +* fd = descripteur d'un flux ouvert en écriture. * +* bits = gestionnaire des bits d'encodage. * +* list = liste de l'ensemble des fonctions de conversion. * +* tab = décalage éventuel selon l'inclusion. * * * -* Description : Indique si une conversion a déjà été définie. * +* Description : Déclare les variables associées à une fonction de conversion.* * * -* Retour : Etat de la définition. * +* Retour : Bilan de l'opération. * * * * Remarques : - * * * ******************************************************************************/ -bool is_conv_func_already_defined(const conv_func *func) +bool declare_conv_func(conv_func *func, int fd, const coding_bits *bits, const conv_list *list, const char *tab) { - return func->defined; + bool result; /* Bilan à remonter */ + bool as_raw; /* Choix logique du format */ + unsigned int wide; /* Taille des mots */ + off_t start; /* Point de départ dans le code*/ + off_t end; /* Point d'arrivée dans le code*/ + + assert(func->used_as_inter || func->used_as_op); + + /** + * Si la fonction a déjà été définie lors d'un précédent besoin... + */ + if (func->declared) return true; + + if (func->is_expr) + result = ensure_arg_expr_content_fully_declared(func->expr, fd, bits, list, tab); + + else + result = ensure_arg_list_content_fully_declared(func->args, fd, bits, list, tab); + + if (result) + { + if (func->used_as_inter) + { + as_raw = is_conv_func_raw_as_inter(func); + + /** + * Si la variable intermédiaire n'est pas brute, deux cas de figure + * sont possibles : + * + * - la variable est un objet purement intermédiaire. + * - la variable est un object qui sera également utilisé en opérande. + * + * Dans les deux cas, on laisse la déclaration en tant qu'opérande + * rédiger la déclaration car il s'agit de déclarations identiques. + */ + + if (as_raw) + { + wide = count_coded_bits(bits); + + start = lseek(fd, 0, SEEK_CUR); + + dprintf(fd, "\t%suint%u_t ", tab, wide); + + write_conv_func(func, fd, true); + + dprintf(fd, ";"); + + end = lseek(fd, 0, SEEK_CUR); + + dprintf(fd, "%*s", (tab[0] == '\0' ? 42 : 39) - (int)(end - start), "/"); + dprintf(fd, "* Champ brut à décoder */\n"); + + } + + } + + if (func->used_as_op || (func->used_as_inter && !as_raw)) + { + start = lseek(fd, 0, SEEK_CUR); + + dprintf(fd, "\t%sGArchOperand *", tab); + + write_conv_func(func, fd, false); + + dprintf(fd, ";"); + + end = lseek(fd, 0, SEEK_CUR); + + dprintf(fd, "%*s", (tab[0] == '\0' ? 42 : 39) - (int)(end - start), "/"); + dprintf(fd, "* Opérande à intégrer */\n"); + + } + + } + + func->declared = result; + + return result; } @@ -345,13 +427,11 @@ bool is_conv_func_already_defined(const conv_func *func) /****************************************************************************** * * * Paramètres : func = fonction de conversion à manipuler. * -* last = précise si la conversion est la dernière. * -* internal = indique le type de manipulation finale. * * fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération globale. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * +* tab = décalage éventuel selon l'inclusion. * +* optional = indique si l'opérande finale est optionnelle. * * exit = exprime le besoin d'une voie de sortie. [OUT] * * * * Description : Définit les variables associées à une fonction de conversion.* @@ -362,89 +442,109 @@ bool is_conv_func_already_defined(const conv_func *func) * * ******************************************************************************/ -bool define_conv_func(conv_func *func, bool last, bool internal, int fd, const char *arch, const coding_bits *bits, const conv_list *list, const pre_processor *pp, bool *exit) +bool define_conv_func(conv_func *func, int fd, const coding_bits *bits, const conv_list *list, const char *tab, bool optional, bool *exit) { bool result; /* Bilan à remonter */ - const char *callable; /* Fonction à appeler */ + bool as_raw; /* Choix logique du format */ - /* Si la fonction a déjà été définie lors d'un précédent besoin... */ - if (func->defined) return true; + /** + * Si la fonction a déjà été définie lors d'un précédent besoin... + */ + if (func->defined) + { + // TODO : faire un object_ref() si c'est un objet + //assert(0); + + return true; + + } if (func->is_expr) - result = ensure_arg_expr_content_fully_defined(func->expr, fd, arch, bits, list, pp, exit); + result = ensure_arg_expr_content_fully_defined(func->expr, fd, bits, list, tab, exit); else - result = ensure_arg_list_content_fully_defined(func->args, fd, arch, bits, list, pp, exit); - - /* Nom de la fonction effectivement appelée */ + result = ensure_arg_list_content_fully_defined(func->args, fd, bits, list, tab, exit); - if (!func->is_expr) + if (result) { - callable = find_macro(pp, func->name); + if (func->used_as_inter) + { + as_raw = is_conv_func_raw_as_inter(func); - if (callable == NULL) - callable = func->name; + /** + * Se référer au besoin aux commentaires de declare_conv_func(). + */ - } - else callable = NULL; + if (as_raw) + { + dprintf(fd, "\t%s", tab); - if (last && callable == NULL) - { - fprintf(stderr, "Error: expected function to store '%s'.\n", func->dest); - return false; - } + write_conv_func(func, fd, true); - /* Dernier niveau : la variable de destination est imposée ! */ - if (last) - { - /* Si l'on doit manipuler une propriété d'instructon... */ - if (internal) - result = checked_call_instr_func(false, callable, func->args, fd, bits, list, pp); + dprintf(fd, " = "); - /* Si on doit constituer un opérande à ajouter... */ - else - { - if (strchr(callable, '(') == NULL) - dprintf(fd, "\t\top = %s(", callable); - else - dprintf(fd, "\t\top = %s", callable); + if (func->is_expr) + result = define_arg_expr(func->expr, fd, bits, list); - result &= define_arg_list(func->args, fd, bits, list); + else + { + assert(strcmp(func->name, "UInt") == 0); + assert(get_arg_list_size(func->args) == 1); - dprintf(fd, ");\n"); + result = define_arg_list(func->args, fd, bits, list); - } + } - } + dprintf(fd, ";\n"); + dprintf(fd, "\n"); - /* On constitue une variable intermédiaire, dont on peut conserver le nom ! */ - else - { - dprintf(fd, "\t\tval_%s = ", func->dest); + } - if (func->is_expr) - result &= define_arg_expr(func->expr, fd, bits, list); + } - else + if (func->used_as_op || (func->used_as_inter && !as_raw)) { - dprintf(fd, "%s(", callable); + dprintf(fd, "\t%s", tab); + + write_conv_func(func, fd, false); + + dprintf(fd, " = %s(", func->name); result = define_arg_list(func->args, fd, bits, list); - dprintf(fd, ")"); + dprintf(fd, ");\n"); - } + if (optional) + { + if (as_raw) + { + fprintf(stderr, "%s can not be optional and used as intermediate value as the same time!\n", + func->dest); - dprintf(fd, ";\n"); + result = false; + + } + + } + + else + { + dprintf(fd, "\t%sif (", tab); + + write_conv_func(func, fd, false); + + dprintf(fd, " == NULL) goto bad_exit;\n"); + + *exit = true; + + } + + dprintf(fd, "\n"); - if (!func->is_expr && is_operand_producer(pp, func->name)) - { - dprintf(fd, "\t\tif (val_%s == NULL) goto bad_exit;\n", func->dest); - *exit = true; } - } + func->defined = result; - func->defined = result; + } return result; @@ -562,91 +662,3 @@ conv_func *find_named_conv_in_list(const conv_list *list, const char *name) return result; } - - -/****************************************************************************** -* * -* Paramètres : list = liste de fonctions de conversion à consulter. * -* fd = descripteur d'un flux ouvert en écriture. * -* bits = gestionnaire des bits d'encodage. * -* pp = pré-processeur pour les échanges de chaînes. * -* wide = taille des mots décodés. * -* * -* Description : Déclare l'ensemble des variables intermédiaires. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool declare_used_intermediate_conversions(const conv_list *list, int fd, const coding_bits *bits, const pre_processor *pp, unsigned int wide) -{ - bool result; /* Bilan à remonter */ - size_t i; /* Boucle de parcours */ - conv_func *func; /* Conversion à traiter */ - - result = true; - - for (i = 0; i < list->func_count && result; i++) - { - func = list->functions[i]; - - if (func->used && func->intermediate) - result = declare_conv_func(func, fd, bits, list, pp, wide); - - } - - return result; - -} - - -/****************************************************************************** -* * -* Paramètres : list = liste de fonctions de conversion à consulter. * -* fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération globale. * -* bits = gestionnaire des bits d'encodage. * -* pp = pré-processeur pour les échanges de chaînes. * -* exit = exprime le besoin d'une voie de sortie. [OUT] * -* * -* Description : Définit l'ensemble des variables intermédiaires. * -* * -* Retour : Bilan de l'opération. * -* * -* Remarques : - * -* * -******************************************************************************/ - -bool define_used_intermediate_conversions(const conv_list *list, int fd, const char *arch, const coding_bits *bits, const pre_processor *pp, bool *exit) -{ - bool result; /* Bilan à remonter */ - bool got_one; /* Suit le nombre d'impressions*/ - size_t i; /* Boucle de parcours */ - conv_func *func; /* Conversion à traiter */ - - result = true; - - got_one = false; - - for (i = 0; i < list->func_count && result; i++) - { - func = list->functions[i]; - - if (func->used && func->intermediate) - { - result = define_conv_func(func, false, false, fd, arch, bits, list, pp, exit); - - got_one = true; - - } - - } - - if (got_one) - dprintf(fd, "\n"); - - return result; - -} diff --git a/tools/d2c/conv/manager.h b/tools/d2c/conv/manager.h index db6e325..035635c 100644 --- a/tools/d2c/conv/manager.h +++ b/tools/d2c/conv/manager.h @@ -53,23 +53,20 @@ void delete_conv_func(conv_func *); /* Indique la variable de destination d'une conversion. */ const char *get_conv_dest_name(const conv_func *); -/* Indique la nature d'une conversion : fonction ou expression ? */ -bool is_conv_func_expression(const conv_func *); - /* Détermine la taille en bits du résultat d'une fonction. */ bool compute_conv_func_size(const conv_func *, const coding_bits *, const conv_list *, unsigned int *); /* Marque les champs utilisés par une fonction de conversion. */ bool mark_conv_func(conv_func *, bool, const coding_bits *, const conv_list *); -/* Déclare les variables associées à une fonction de conversion. */ -bool declare_conv_func(conv_func *, int, const coding_bits *, const conv_list *, const pre_processor *, unsigned int); +/* Imprime la désignation de la destination d'une conversion. */ +void write_conv_func(conv_func *, int, bool); -/* Indique si une conversion a déjà été définie. */ -bool is_conv_func_already_defined(const conv_func *); +/* Déclare les variables associées à une fonction de conversion. */ +bool declare_conv_func(conv_func *, int, const coding_bits *, const conv_list *, const char *); /* Définit les variables associées à une fonction de conversion. */ -bool define_conv_func(conv_func *, bool, bool, int, const char *, const coding_bits *, const conv_list *, const pre_processor *, bool *); +bool define_conv_func(conv_func *, int, const coding_bits *, const conv_list *, const char *, bool, bool *); @@ -92,12 +89,6 @@ void register_conversion(conv_list *, conv_func *); /* Recherche un résultat précis dans une liste de fonctions. */ conv_func *find_named_conv_in_list(const conv_list *, const char *); -/* Déclare l'ensemble des variables intermédiaires. */ -bool declare_used_intermediate_conversions(const conv_list *, int, const coding_bits *, const pre_processor *, unsigned int); - -/* Définit l'ensemble des variables intermédiaires. */ -bool define_used_intermediate_conversions(const conv_list *, int, const char *, const coding_bits *, const pre_processor *, bool *); - #endif /* _TOOLS_D2C_CONV_MANAGER_H */ diff --git a/tools/d2c/conv/tokens.l b/tools/d2c/conv/tokens.l index ef6b958..f1d196d 100644 --- a/tools/d2c/conv/tokens.l +++ b/tools/d2c/conv/tokens.l @@ -28,5 +28,12 @@ <raw_line>[^\n]+ { yylvalp->cstring = yytext; return RAW_LINE; } <raw_line>"\n" { yy_pop_state(); } +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c conv block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + %% diff --git a/tools/d2c/d2c.c b/tools/d2c/d2c.c new file mode 100644 index 0000000..2f10d20 --- /dev/null +++ b/tools/d2c/d2c.c @@ -0,0 +1,351 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * d2c.c - compilation d'asbtractions d'instructions + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include <assert.h> +#include <getopt.h> +#include <math.h> +#include <stdio.h> +#include <stdlib.h> +#include <string.h> + + +#include "coder.h" +#include "decl.h" + + + +/* Affiche des indications sur l'utilisation du programme. */ +static void show_usage(const char *); + + +/* Commandes générales supportées */ +typedef enum _AvailableD2cCommand +{ + ADC_NONE, /* Aucune action renseignée */ + ADC_COMPILE, /* Créations principales */ + ADC_FINI /* Finition de fichier global */ + +} AvailableD2cCommand; + + + +/****************************************************************************** +* * +* Paramètres : argv0 = nombre du programme exécuté. * +* * +* Description : Affiche des indications sur l'utilisation du programme. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +static void show_usage(const char *argv0) +{ + printf("\n"); + + printf("Usage: %s [options] <input file>\n", argv0); + + printf("\n"); + + printf("General options:\n"); + + printf("\n"); + + printf("\t-h | --help\t\t\tDisplay this messsage.\n"); + printf("\t-x | --exec <cc|fini>\t\tRun as compiler mode or complete the generation.\n"); + printf("\t-o | --outdir <string>\t\tSpecify the main output directory.\n"); + printf("\t-t | --type <raw|format>\tSet the type of the input file.\n"); + printf("\t-a | --arch <string>\t\tDefine the archicture to handle (CamelCase allowed).\n"); + printf("\t-n | --name <string>\t\tSet the name of the archicture for source code (CamelCase allowed).\n"); + printf("\t-G | --guard <string>\t\tSet the base of the header macros guards.\n"); + printf("\t-e | --encoding <none|string>\tDefine one encoding prefix for files.\n"); + + printf("\n"); + + printf("\t--id-prefix <string>\t\tDefine a common prefix for all uniq identifiers.\n"); + printf("\t--id-expected <number>\t\tProvide the expected number of instructions.\n"); + + printf("\n"); + + printf("Format specific options:\n"); + + printf("\n"); + + printf("\t--op-prefix <string>\t\tDefine a prefix to format operand type constants.\n"); + + printf("\n"); + +} + + +/****************************************************************************** +* * +* Paramètres : argc = nombre d'arguments dans la ligne de commande. * +* argv = arguments de la ligne de commande. * +* * +* Description : Point d'entrée du programme. * +* * +* Retour : EXIT_SUCCESS si le prgm s'est déroulé sans encombres. * +* * +* Remarques : - * +* * +******************************************************************************/ + +int main(int argc, char **argv) +{ + int result; /* Bilan à retourner */ + bool need_help; /* Affichage de l'aide ? */ + AvailableD2cCommand execute; /* Exécution globale attendue */ + output_info info; /* Regroupement d'infos utiles */ + pre_processor *pp; /* Pré-processeur avec macros */ + bool has_error; /* Erreur dans la ligne de cmd.*/ + int index; /* Indice d'argument à traiter */ + int ret; /* Bilan d'une lecture d'arg. */ + char *sep; /* Caratère '=' en coupure */ + unsigned long int expected; /* Nombre total de définitions */ + rented_coder *coder; /* Codeur à briffer & employer */ + bool status; /* Bilan d'une génération */ + char *temp; /* Zone de travail temporaire */ + char *base; /* Identification de fichier */ + char *underscore; /* Dernier caractère '_' */ + + static struct option long_options[] = { + + { "help", no_argument, NULL, 'h' }, + { "exec", required_argument, NULL, 'x' }, + { "outdir", required_argument, NULL, 'o' }, + { "type", required_argument, NULL, 't' }, + { "arch", required_argument, NULL, 'a' }, + { "name", required_argument, NULL, 'n' }, + { "guard", required_argument, NULL, 'G' }, + { "encoding", required_argument, NULL, 'e' }, + + { "id-prefix", required_argument, NULL, 0x100 }, + { "id-expected",required_argument, NULL, 0x101 }, + + { "op-prefix", required_argument, NULL, 0x200 }, + + { NULL, 0, NULL, 0 } + + }; + + /* Récupération des commandes */ + + need_help = false; + execute = ADC_NONE; + memset(&info, 0, sizeof(info)); + + pp = create_pre_processor(); + + has_error = false; + + while (!has_error) + { + ret = getopt_long(argc, argv, "hx:o:t:a:n:e:G:", long_options, &index); + if (ret == -1) break; + + switch (ret) + { + case 'h': + need_help = true; + break; + + case 'x': + + if (strcmp(optarg, "cc") == 0) + execute = ADC_COMPILE; + + else if (strcmp(optarg, "fini") == 0) + execute = ADC_FINI; + + else + has_error = true; + + break; + + case 'o': + info.directory = optarg; + break; + + case 't': + + if (strcmp(optarg, "raw") == 0) + info.type = IOT_RAW; + + else if (strcmp(optarg, "format") == 0) + info.type = IOT_FORMAT; + + else + has_error = true; + + break; + + case 'a': + info.arch = optarg; + break; + + case 'n': + info.arch_cn = optarg; + break; + + case 'G': + info.guard = optarg; + break; + + case 'e': + + if (strcmp(optarg, "none") == 0) + register_empty_encoding(pp); + + else + { + sep = strchr(optarg, '='); + has_error = (sep == NULL); + + if (!has_error) + { + *sep = '\0'; + register_encoding(pp, optarg, sep + 1); + } + + } + + break; + + case 0x100: + info.id_prefix = optarg; + break; + + case 0x101: + expected = strtoul(optarg, NULL, 10); + info.id_len = (int)ceil(log(expected) / log(16));; + break; + + case 0x200: + info.fmt_prefix = optarg; + break; + + default: + has_error = true; + break; + + } + + } + + /* Vérifications supplémentaires */ + + if (execute == ADC_NONE) + has_error = true; + + if (info.directory == NULL || info.arch == NULL || info.arch_cn == NULL || info.guard == NULL) + has_error = true; + + if (need_help || has_error || (optind + 1) != argc) + { + show_usage(argv[0]); + result = (need_help ? EXIT_SUCCESS : EXIT_FAILURE); + goto exit; + } + + /* Execution attendue */ + + result = EXIT_FAILURE; + + switch (execute) + { + case ADC_COMPILE: + + coder = process_definition_file(argv[optind], pp); + if (coder == NULL) goto exit; + + status = output_coder_body(coder, &info); + if (!status) goto clean_exit; + + status = output_coder_identifier(coder, &info); + if (!status) goto clean_exit; + + if (info.type == IOT_FORMAT) + { + status = output_coder_keyword(coder, &info); + if (!status) goto clean_exit; + } + + status = output_coder_description(coder, &info); + if (!status) goto clean_exit; + + break; + + case ADC_FINI: + + coder = NULL; + + temp = strdup(argv[optind]); + base = basename(temp); + + underscore = rindex(base, '_'); + + if (underscore == NULL && strcmp(base, "opcodes.h") == 0) + status = fini_coder_opcodes_file(argv[optind], &info); + + else if (underscore != NULL && strcmp(underscore, "_opcodes.h") == 0) + status = fini_coder_opcodes_file(argv[optind], &info); + + else if (strcmp(base, "identifiers.h") == 0) + status = fini_coder_identifiers_file(argv[optind], &info); + + else if (info.type == IOT_FORMAT && strcmp(base, "keywords.h") == 0) + status = fini_coder_keywords_file(argv[optind], &info); + + else if (strcmp(base, "descriptions.h") == 0) + status = fini_coder_descriptions_file(argv[optind], &info); + + else + status = false; + + free(temp); + + if (!status) goto exit; + + break; + + default: + assert(false); + break; + + } + + result = EXIT_SUCCESS; + + clean_exit: + + if (coder != NULL) + delete_coder(coder); + + exit: + + return result; + +} diff --git a/tools/d2c/d2c.mk b/tools/d2c/d2c.mk index dbc9b83..10bd226 100644 --- a/tools/d2c/d2c.mk +++ b/tools/d2c/d2c.mk @@ -5,20 +5,27 @@ d2c_verbose = $(d2c_verbose_@AM_V@) d2c_verbose_ = $(d2c_verbose_@AM_DEFAULT_V@) d2c_verbose_0 = @echo " D2C " $<; +fini_verbose = $(fini_verbose_@AM_V@) +fini_verbose_ = $(fini_verbose_@AM_DEFAULT_V@) +fini_verbose_0 = echo " FINI " `basename $$f`; + fix_verbose = $(fix_verbose_@AM_V@) fix_verbose_ = $(fix_verbose_@AM_DEFAULT_V@) fix_verbose_0 = echo " FIX " `basename $$f`; # D2C_BIN = -# D2C_TYPE = +# GEN_BIN = + # D2C_OUTDIR = +# D2C_TYPE = # D2C_ARCH = -# D2C_HEADER = +# D2C_ARCH_CN = +# D2C_GUARD = # D2C_ENCODINGS = -# D2C_MACROS = -# D2C_OPERANDS = -# D2C_PREFIX = +# D2C_ID_PREFIX = +# D2C_ID_COUNT = +# D2C_SPECIFIC = # FIXED_C_INCLUDES = # FIXED_H_INCLUDES = @@ -27,25 +34,36 @@ fix_verbose_0 = echo " FIX " `basename $$f`; SUFFIXES = .g .d.g: - $(d2c_verbose)$(D2C_BIN) -i $< -t $(D2C_TYPE) -d $(D2C_OUTDIR) -a $(D2C_ARCH) -H $(D2C_HEADER) $(D2C_ENCODINGS) $(D2C_MACROS) $(D2C_OPERANDS) -p "$(D2C_PREFIX)" + $(d2c_verbose)$(D2C_BIN) -x cc -o $(D2C_OUTDIR) -t $(D2C_TYPE) -a $(D2C_ARCH) -n $(D2C_ARCH_CN) \ + -G $(D2C_GUARD) $(D2C_ENCODINGS) --id-prefix=$(D2C_ID_PREFIX) --id-expected=$(D2C_ID_COUNT) \ + $(D2C_SPECIFIC) $< @touch $@ -d2c_final_rules: fix_includes_in_c_templates fix_includes_in_h_templates untabify_disass +d2c_final_rules: finish_headers fix_includes_in_c_templates fix_includes_in_h_templates untabify_disass + +finish_headers: + @for f in `find $(D2C_OUTDIR) -type f -name '*.h'`; do \ + grep -q '#endif' $$f && continue; \ + $(fini_verbose)$(D2C_BIN) -x fini -o $(D2C_OUTDIR) -t $(D2C_TYPE) -a $(D2C_ARCH) -n $(D2C_ARCH_CN) \ + -G $(D2C_GUARD) $(D2C_ENCODINGS) --id-prefix=$(D2C_ID_PREFIX) --id-expected=$(D2C_ID_COUNT) \ + $(D2C_SPECIFIC) $$f \ + || ( echo "Can not complete $$f" ; exit 1 ) ; \ + done fix_includes_in_c_templates: - @for f in `find .gen/ -name '*tmpl.c'`; do \ - if grep -q '##INCLUDES##' $$f; then \ - $(fix_verbose)sed -i 's@##INCLUDES##@$(FIXED_C_INCLUDES)@' $$f; \ - fi; \ + @for f in `find $(D2C_OUTDIR) -type f -name '*.c'`; do \ + if grep -q '##INCLUDES##' $$f; then \ + $(fix_verbose)sed -i 's@##INCLUDES##@$(FIXED_C_INCLUDES)@' $$f; \ + fi; \ done fix_includes_in_h_templates: - @for f in `find .gen/ -name '*tmpl.h'`; do \ - if grep -q '##INCLUDES##' $$f; then \ + @for f in `find $(D2C_OUTDIR) -type f -name '*.h'`; do \ + if grep -q '##INCLUDES##' $$f; then \ $(fix_verbose)sed -i 's@##INCLUDES##@$(FIXED_H_INCLUDES)@' $$f ; \ - fi; \ + fi; \ done # Merci http://www.commandlinefu.com/commands/view/10276/grep-tab-t untabify_disass: - @find .gen/ -name '*[ch]' -exec grep -q $$'\t' {} \; -exec sed -i 's/\t/ /g' {} \; + @find $(D2C_OUTDIR) -type f -name '*.[ch]' -exec grep -q $$'\t' {} \; -exec sed -i 's/\t/ /g' {} \; diff --git a/tools/d2c/d2c_genmakefile.sh b/tools/d2c/d2c_genmakefile.sh index be303e0..d01fa6c 100755 --- a/tools/d2c/d2c_genmakefile.sh +++ b/tools/d2c/d2c_genmakefile.sh @@ -1,17 +1,15 @@ #!/bin/sh -if [ $# -lt 4 ]; then +if [ $# -lt 2 ]; then - echo "Usage: $0 <working dir> <input dir> <global mk> <arch [arch [arch ...]]" + echo "Usage: $0 <opcodes dir> <arch [arch [arch ...]]" exit 1 fi workingdir=$1 -input=$2 -globalmk=$3 -shift 3 +shift 1 OLDPWD=$PWD @@ -23,124 +21,37 @@ cd ${workingdir} echo=`which echo` rm -f ${MAKEFILE_TMP} -$echo >> ${MAKEFILE_TMP} -$echo "include ${globalmk}" >> ${MAKEFILE_TMP} -$echo >> ${MAKEFILE_TMP} +# Génération de la liste des sources -if [ "$1" = "-" ]; then - OPCODES=`find ${input} -name '*c' -and -not -name '*.tmpl.c' -exec basename {} \; | cut -d. -f2 | sort | uniq` -else - OPCODES=`find ${input} -name '*c' -and -not -name '*.tmpl.c' -exec basename {} \; | cut -d. -f3 | sort | uniq` -fi +$echo >> ${MAKEFILE_TMP} -# Génération des en-têtes de décodage +$echo -n "GENERATED_FILES = " >> ${MAKEFILE_TMP} for arch in $*; do if [ ${arch} = "-" ]; then arch_name="" - arch_name_dotted="" else arch_name="${arch}_" - arch_name_dotted="${arch}_." fi - $echo -n "${arch_name}HEADER_FILES =" | tr [:lower:] [:upper:] >> ${MAKEFILE_TMP} - - has_header="" + SOURCES=`find . -type f -name "${arch_name}*.h" -exec basename {} \; | sort` - for op in $OPCODES; + for src in $SOURCES; do - template="${input}/*.${arch_name_dotted}${op}.c" - - sources=`ls $template 2> /dev/null` - - if [ -z "${sources}" ]; then - continue - fi - - for src in ${sources}; - do - has_header="yes" - $echo -ne " \\" >> ${MAKEFILE_TMP} - $echo -ne "\n\t" >> ${MAKEFILE_TMP} - $echo -n ${src} | sed "s/${op}.c$/opcodes.h/" >> ${MAKEFILE_TMP} - done + $echo -ne " \\" >> ${MAKEFILE_TMP} + $echo -ne "\n\t${src}" >> ${MAKEFILE_TMP} done - $echo >> ${MAKEFILE_TMP} - $echo >> ${MAKEFILE_TMP} - - $echo -n "${arch_name}opcodes.h: " >> ${MAKEFILE_TMP} - $echo "\$(${arch_name}HEADER_FILES)" | tr [:lower:] [:upper:] >> ${MAKEFILE_TMP} - - if [ -z "${has_header}" ]; then - - $echo -e "\techo > \$@" >> ${MAKEFILE_TMP} - - else - - $echo -e "\t\$(cini_verbose)cat ${input}/${arch_name_dotted}opcodes.tmpl.h > \$@" >> ${MAKEFILE_TMP} - $echo -e "\t\$(cgen_verbose)cat \$^ >> \$@" >> ${MAKEFILE_TMP} - $echo -e "\t\$(cfini_verbose)echo >> \$@" >> ${MAKEFILE_TMP} - $echo -en "\t\$(cfini_verbose)echo \"#endif\t /* " >> ${MAKEFILE_TMP} - $echo -en '`cat \$@ | grep "#define" | cut -d " " -f 2`' >> ${MAKEFILE_TMP} - $echo -e " */\" >> \$@" >> ${MAKEFILE_TMP} - - fi - - $echo >> ${MAKEFILE_TMP} - -done + SOURCES=`find . -type f -name "${arch_name}*.c" -exec basename {} \; | sort` -$echo >> ${MAKEFILE_TMP} - -# Génération des codes d'instructions - -for op in $OPCODES; -do - for arch in $*; + for src in $SOURCES; do - if [ ${arch} = "-" ]; then - arch_name="" - arch_name_dotted="" - else - arch_name="${arch}_" - arch_name_dotted="${arch}_." - fi - - template="${input}/*.${arch_name_dotted}${op}.c" - - sources=`ls $template 2> /dev/null` - - if [ -z "${sources}" ]; then - continue - fi - - $echo -n "${op}_${arch_name}FILES =" | tr [:lower:] [:upper:] >> ${MAKEFILE_TMP} - - for src in ${sources}; - do - $echo -ne " \\" >> ${MAKEFILE_TMP} - $echo -ne "\n\t${src}" >> ${MAKEFILE_TMP} - done - - $echo >> ${MAKEFILE_TMP} - $echo >> ${MAKEFILE_TMP} - - $echo -n "${arch_name}${op}.c: " >> ${MAKEFILE_TMP} - $echo -n "\$(${op}_${arch_name}FILES)" | tr [:lower:] [:upper:] >> ${MAKEFILE_TMP} - $echo " ${arch_name}opcodes.h" >> ${MAKEFILE_TMP} - - $echo -e "\t\$(cini_verbose)cat ${input}/${arch_name_dotted}${op}.tmpl.c > \$@" >> ${MAKEFILE_TMP} - $echo -ne "\t\$(cgen_verbose)cat \$(" >> ${MAKEFILE_TMP} - $echo -ne "${op}_${arch_name}FILES" | tr [:lower:] [:upper:] >> ${MAKEFILE_TMP} - $echo -e ") >> \$@" >> ${MAKEFILE_TMP} - - $echo >> ${MAKEFILE_TMP} + $echo -ne " \\" >> ${MAKEFILE_TMP} + $echo -ne "\n\t${src}" >> ${MAKEFILE_TMP} done @@ -148,48 +59,13 @@ done $echo >> ${MAKEFILE_TMP} -# Génération de la liste des sources - -$echo -n "GENERATED_FILES =" >> ${MAKEFILE_TMP} - -for arch in $*; -do - if [ ${arch} = "-" ]; then - arch_name="" - arch_name_dotted="" - else - arch_name="${arch}_" - arch_name_dotted="${arch}_." - fi - - $echo -ne " \\" >> ${MAKEFILE_TMP} - $echo -ne "\n\t${arch_name}opcodes.h" >> ${MAKEFILE_TMP} - - for op in $OPCODES; - do - template="${input}/*.${arch_name_dotted}${op}.c" - - sources=`ls $template 2> /dev/null` - - if [ ! -z "${sources}" ]; then - $echo -ne " \\" >> ${MAKEFILE_TMP} - $echo -ne "\n\t${arch_name}${op}.c" >> ${MAKEFILE_TMP} - continue - fi - - done - -done - $echo >> ${MAKEFILE_TMP} -$echo >> ${MAKEFILE_TMP} # Validation finale -if [ ! -f ]; then +if [ ! -f ${MAKEFILE_EXT} ]; then - rm -rf ${MAKEFILE_EXT} mv ${MAKEFILE_TMP} ${MAKEFILE_EXT} else diff --git a/tools/d2c/decl.h b/tools/d2c/decl.h new file mode 100644 index 0000000..c2a001d --- /dev/null +++ b/tools/d2c/decl.h @@ -0,0 +1,37 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * decl.h - déclarations de prototypes utiles + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _TOOLS_D2C_DECL_H +#define _TOOLS_D2C_DECL_H + + +#include "coder.h" + + + +/* Charge en mémoire la définition contenue dans un fichier. */ +rented_coder *process_definition_file(const char *, pre_processor *); + + + +#endif /* _TOOLS_D2C_BITS_DECL_H */ diff --git a/tools/d2c/desc/Makefile.am b/tools/d2c/desc/Makefile.am new file mode 100644 index 0000000..d680c84 --- /dev/null +++ b/tools/d2c/desc/Makefile.am @@ -0,0 +1,10 @@ + +AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) + + +noinst_LTLIBRARIES = libd2cdesc.la + +.NOTPARALLEL: $(noinst_LTLIBRARIES) + +libd2cdesc_la_SOURCES = \ + manager.h manager.c diff --git a/tools/d2c/desc/manager.c b/tools/d2c/desc/manager.c new file mode 100644 index 0000000..5e2efa7 --- /dev/null +++ b/tools/d2c/desc/manager.c @@ -0,0 +1,166 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * manager.c - enregistrement d'une description complète + * + * Copyright (C) 2016-2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "manager.h" + + +#include <assert.h> +#include <ctype.h> +#include <malloc.h> +#include <string.h> + + + +/* Mémorisation de la description d'un identifiant */ +struct _instr_desc +{ + char *text; /* Contenu humainement lisible */ + +}; + + + +/****************************************************************************** +* * +* Paramètres : - * +* * +* Description : Crée un nouveau gestionnaire de définitions d'identifiant. * +* * +* Retour : Nouvelle structure prête à emploi. * +* * +* Remarques : - * +* * +******************************************************************************/ + +instr_desc *create_instruction_description(void) +{ + instr_desc *result; /* Définition vierge à renvoyer*/ + + result = (instr_desc *)calloc(1, sizeof(instr_desc)); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : desc = gestionnaire de définition de description à libérer. * +* * +* Description : Supprime de la mémoire un gestionnaire de description. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void delete_instruction_description(instr_desc *desc) +{ + if (desc->text != NULL) + free(desc->text); + + free(desc); + +} + + +/****************************************************************************** +* * +* Paramètres : desc = gestionnaire de définition de description à traiter. * +* text = valeur du contenu à mémoriser. * +* * +* Description : Définit le contenu textuel d'une description. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void set_instruction_description(instr_desc *desc, const char *text) +{ + const char *start; /* Départ réel du contenu */ + size_t len; /* Taille maximale à parcourir */ + char *iter; /* Boucle de parcours */ + + for (start = text; *start != '\0'; start++) + if (!isspace(*start)) + break; + + desc->text = strdup(start); + + len = strlen(desc->text); + + if (len > 0) + { + for (iter = desc->text + len - 1; + iter != desc->text; + iter--) + { + if (isspace(*iter)) + *iter = '\0'; + else + break; + } + + } + +} + + +/****************************************************************************** +* * +* Paramètres : desc = gestionnaire de définition de description à traiter. * +* fd = flux ouvert en écriture. * +* * +* Description : Imprime la description associée à une instruction. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void write_instruction_description(const instr_desc *desc, int fd) +{ + const char *iter; /* Boucle de parcours */ + + for (iter = desc->text; *iter != '\0'; iter++) + switch (*iter) + { + case '\n': + dprintf(fd, "\\n"); + break; + + case '"': + dprintf(fd, "\\\""); + break; + + default: + dprintf(fd, "%c", *iter); + break; + + } + +} diff --git a/tools/d2c/desc/manager.h b/tools/d2c/desc/manager.h new file mode 100644 index 0000000..45cc262 --- /dev/null +++ b/tools/d2c/desc/manager.h @@ -0,0 +1,47 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * manager.h - prototypes pour l'enregistrement d'une description complète + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _TOOLS_D2C_DESC_MANAGER_H +#define _TOOLS_D2C_DESC_MANAGER_H + + + +/* Mémorisation de la description d'un identifiant */ +typedef struct _instr_desc instr_desc; + + +/* Crée un nouveau gestionnaire de définitions d'identifiant. */ +instr_desc *create_instruction_description(void); + +/* Supprime de la mémoire un gestionnaire de description. */ +void delete_instruction_description(instr_desc *); + +/* Définit le contenu textuel d'une description. */ +void set_instruction_description(instr_desc *, const char *); + +/* Imprime la description associée à une instruction. */ +void write_instruction_description(const instr_desc *, int); + + + +#endif /* _TOOLS_D2C_DESC_MANAGER_H */ diff --git a/tools/d2c/spec.c b/tools/d2c/encoding.c index 4bf4307..052fc04 100644 --- a/tools/d2c/spec.c +++ b/tools/d2c/encoding.c @@ -1,6 +1,6 @@ /* Chrysalide - Outil d'analyse de fichiers binaires - * spec.c - représentation complète d'un encodage + * encoding.c - représentation complète d'un encodage * * Copyright (C) 2014-2017 Cyrille Bagard * @@ -21,9 +21,10 @@ */ -#include "spec.h" +#include "encoding.h" +#include <assert.h> #include <malloc.h> #include <regex.h> #include <stdio.h> @@ -45,10 +46,10 @@ struct _encoding_spec operands_format *format; /* Définition des opérandes */ coding_bits *bits; /* Encodage des bits associés */ - asm_syntax *syntax; /* Calligraphe d'assemblage */ - conv_list *conversions; /* Conversions des données */ instr_hooks *hooks; /* Fonctions complémentaires */ - decoding_rules *rules; /* Règles supplémentaires */ + + encoding_syntax **syntaxes; /* Définitions déjà en place */ + size_t syntax_count; /* Nombre de ces définitions */ }; @@ -75,10 +76,7 @@ encoding_spec *create_encoding_spec(void) result->format = create_operands_format(); result->bits = create_coding_bits(); - result->syntax = create_asm_syntax(); - result->conversions = create_conv_list(); result->hooks = create_instr_hooks(); - result->rules = create_decoding_rules(); return result; @@ -99,13 +97,21 @@ encoding_spec *create_encoding_spec(void) void delete_encoding_spec(encoding_spec *spec) { + size_t i; /* Boucle de parcours */ + delete_operands_format(spec->format); delete_coding_bits(spec->bits); - delete_asm_syntax(spec->syntax); - delete_conv_list(spec->conversions); delete_instr_hooks(spec->hooks); - delete_decoding_rules(spec->rules); + + if (spec->syntaxes != NULL) + { + for (i = 0; i < spec->syntax_count; i++) + delete_encoding_syntax(spec->syntaxes[i]); + + free(spec->syntaxes); + + } free(spec); @@ -170,17 +176,21 @@ bool has_encoding_spec_prefix(const encoding_spec *spec, const char *prefix) * * * Paramètres : spec = spécification d'encodage à consulter. * * * -* Description : Fournit le gestionnaire des définitions d'opérandes. * +* Description : Construit la distinction propre à un encodage. * * * -* Retour : Structure assurant la définition des opérandes * +* Retour : Distinction à libérer de la mémoire après usage. * * * * Remarques : - * * * ******************************************************************************/ -operands_format *get_format_in_encoding_spec(const encoding_spec *spec) +char *build_encoding_spec_prefix(const encoding_spec *spec) { - return spec->format; + char *result; /* Chaîne à retourner */ + + asprintf(&result, "%s%u", spec->lprefix, spec->index); + + return result; } @@ -189,17 +199,17 @@ operands_format *get_format_in_encoding_spec(const encoding_spec *spec) * * * Paramètres : spec = spécification d'encodage à consulter. * * * -* Description : Fournit le gestionnaire des bits d'un encodage d'instruction.* +* Description : Fournit le gestionnaire des définitions d'opérandes. * * * -* Retour : Structure assurant le suivi des bits. * +* Retour : Structure assurant la définition des opérandes. * * * * Remarques : - * * * ******************************************************************************/ -coding_bits *get_bits_in_encoding_spec(const encoding_spec *spec) +operands_format *get_format_in_encoding_spec(const encoding_spec *spec) { - return spec->bits; + return spec->format; } @@ -208,17 +218,17 @@ coding_bits *get_bits_in_encoding_spec(const encoding_spec *spec) * * * Paramètres : spec = spécification d'encodage à consulter. * * * -* Description : Fournit l'indicateur des écritures correctes d'assembleur. * +* Description : Fournit le gestionnaire des bits d'un encodage d'instruction.* * * -* Retour : Structure assurant la gestion des éléments de syntaxe. * +* Retour : Structure assurant le suivi des bits. * * * * Remarques : - * * * ******************************************************************************/ -asm_syntax *get_syntax_in_encoding_spec(const encoding_spec *spec) +coding_bits *get_bits_in_encoding_spec(const encoding_spec *spec) { - return spec->syntax; + return spec->bits; } @@ -227,7 +237,7 @@ asm_syntax *get_syntax_in_encoding_spec(const encoding_spec *spec) * * * Paramètres : spec = spécification d'encodage à consulter. * * * -* Description : Fournit la liste des fonctions de conversion. * +* Description : Fournit la liste des fonctions à lier à une instruction. * * * * Retour : Structure assurant la gestion des fonctions de conversion. * * * @@ -235,28 +245,33 @@ asm_syntax *get_syntax_in_encoding_spec(const encoding_spec *spec) * * ******************************************************************************/ -conv_list *get_conversions_in_encoding_spec(const encoding_spec *spec) +instr_hooks *get_hooks_in_encoding_spec(const encoding_spec *spec) { - return spec->conversions; + return spec->hooks; } /****************************************************************************** * * -* Paramètres : spec = spécification d'encodage à consulter. * +* Paramètres : spec = spécification d'encodage à étendre. * * * -* Description : Fournit la liste des fonctions à lier à une instruction. * +* Description : Enregistre une définition de syntaxe supplémentaire. * * * -* Retour : Structure assurant la gestion des fonctions de conversion. * +* Retour : - * * * * Remarques : - * * * ******************************************************************************/ -instr_hooks *get_hooks_in_encoding_spec(const encoding_spec *spec) +void push_new_encoding_syntax(encoding_spec *spec) { - return spec->hooks; + encoding_syntax *syntax; /* Définition à compléter */ + + syntax = create_encoding_syntax(); + + spec->syntaxes = realloc(spec->syntaxes, ++spec->syntax_count * sizeof(encoding_syntax *)); + spec->syntaxes[spec->syntax_count - 1] = syntax; } @@ -265,31 +280,36 @@ instr_hooks *get_hooks_in_encoding_spec(const encoding_spec *spec) * * * Paramètres : spec = spécification d'encodage à consulter. * * * -* Description : Fournit un ensemble de règles supplémentaires éventuel. * +* Description : Fournit un lien vers la définition de syntaxe courante. * * * -* Retour : Structure assurant la gestion de ces règles. * +* Retour : Définition en cours d'édition. * * * * Remarques : - * * * ******************************************************************************/ -decoding_rules *get_rules_in_encoding_spec(const encoding_spec *spec) +encoding_syntax *get_current_encoding_syntax(const encoding_spec *spec) { - return spec->rules; + encoding_syntax *result; /* Définition à retourner */ + + if (spec->syntax_count == 0) + result = NULL; + + else + result = spec->syntaxes[spec->syntax_count - 1]; + + return result; } /****************************************************************************** * * -* Paramètres : spec = spécification servant de base à l'opération. * -* fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération. * -* subarch = sous-catégorie de cette même architecture. * -* ins = désignation première de l'instruction manipulée. * -* details = particularités de l'instruction. * -* wide = taille des mots manipulés (en bits). * -* pp = pré-processeur pour les échanges de chaînes. * +* Paramètres : spec = spécification servant de base à l'opération. * +* fd = descripteur d'un flux ouvert en écriture. * +* arch = architecture visée par l'opération. * +* id = identifiant unique attribué à l'instruction. * +* pp = pré-processeur pour les échanges de chaînes. * * * * Description : Traduit en code une sous-fonction de désassemblage. * * * @@ -299,96 +319,115 @@ decoding_rules *get_rules_in_encoding_spec(const encoding_spec *spec) * * ******************************************************************************/ -bool write_encoding_spec_disass(const encoding_spec *spec, int fd, const char *arch, const char *subarch, const char *ins, const char *details, unsigned int wide, const pre_processor *pp) +bool write_encoding_spec_raw_disass(const encoding_spec *spec, int fd, const char *arch, const instr_id *id, const pre_processor *pp) { bool result; /* Bilan à retourner */ - bool bad_exit; /* Ajout d'une sortie d'échec ?*/ - char *keyword; /* Mot clef appelable en code */ - bool quick_exit; /* Inclusion de sortie rapide ?*/ - const char *new_ins; /* Nouvelle définition de nom */ - char *encoding_fc; /* Spécification d'encodage */ - char *cast; /* Conversion vers le format */ + bool openbar; /* Syntaxe unique par défaut ? */ + disass_assert *dassert; /* Eventuelles conditions */ + size_t i; /* Boucle de parcours */ - result = true; - bad_exit = false; - keyword = make_callable(ins, false); - dprintf(fd, "\tGArchInstruction *%s_decode_%s%s_%s%u(uint%u_t _raw)\n", - arch, keyword, details, spec->lprefix, spec->index, wide); - dprintf(fd, "\t{\n"); - dprintf(fd, "\t\tGArchInstruction *instr;\n"); + bool op_decl; /* Suivi des déclaration #1 */ + bool imm_decl; /* Suivi des déclaration #2 */ - /* Déclaration des champs à retrouver */ + bool bad_exit; /* Ajout d'une sortie d'échec ?*/ + bool quick_exit; /* Inclusion de sortie rapide ?*/ - result &= mark_syntax_items(spec->syntax, spec->bits, spec->conversions); - result &= mark_decoding_rules(spec->rules, spec->bits, spec->conversions); - result &= declare_used_bits_fields(spec->bits, fd, wide); + char *encoding_fc; /* Spécification d'encodage */ + char *cast; /* Conversion vers le format */ - result &= declare_used_intermediate_conversions(spec->conversions, fd, spec->bits, pp, wide); - result &= declare_syntax_items(spec->syntax, fd, spec->bits, spec->conversions, wide); - dprintf(fd, "\n"); + /*************** + * + * + * REAL ONE + * + * + * + **********************/ - result &= declare_hook_functions(spec->hooks, false, fd); - /* Vérification que le décodage est possible */ - result &= check_bits_correctness(spec->bits, fd); - dprintf(fd, "\n"); + result = true; - /* Définition des champs bruts */ + /* Détermination de la forme du code */ - result &= define_used_bits_fields(spec->bits, fd); + openbar = (spec->syntax_count == 1); - result &= define_used_intermediate_conversions(spec->conversions, fd, arch, spec->bits, pp, &bad_exit); + if (openbar) + { + dassert = get_assertions_for_encoding_syntax(spec->syntaxes[0]); + openbar = is_disass_assert_empty(dassert); + } - /* Inclusion des éventuelles règles */ + else + { + for (i = 0; i < spec->syntax_count && result; i++) + { + dassert = get_assertions_for_encoding_syntax(spec->syntaxes[0]); - quick_exit = false; + if (is_disass_assert_empty(dassert)) + { + fprintf(stderr, "The syntax definition #%zu has no entry conditions!\n", i); + result = false; + } - result &= write_decoding_rules(spec->rules, false, CAT_SEE, - fd, arch, subarch, spec->bits, spec->conversions, pp, &quick_exit); + } - result &= write_decoding_rules(spec->rules, false, CAT_UNPREDICTABLE, - fd, arch, subarch, spec->bits, spec->conversions, pp, &quick_exit); + } - /* Création de l'instruction en elle-même */ + if (!result) + goto wesrd_exit; + + /* Déclarations préalables */ - new_ins = get_new_keyword_from_syntax_items(spec->syntax); + dprintf(fd, "\tGArchInstruction *result; /* Instruction créée à renvoyer*/\n"); + + for (i = 0; i < spec->syntax_count && result; i++) + result = mark_syntax_items(spec->syntaxes[i], spec->bits); - dprintf(fd, "\t\tinstr = g_%s_instruction_new(\"%s\");\n", arch, new_ins != NULL ? new_ins : ins); + if (!result) + goto wesrd_exit; + + result = declare_used_bits_fields(spec->bits, fd); + if (!result) goto wesrd_exit; + + if (openbar) + { + result = declare_encoding_syntax(spec->syntaxes[0], fd, spec->bits); + if (!result) goto wesrd_exit; + } dprintf(fd, "\n"); - /* Inscriptions des éventuelles fonctions ou propriété à lier */ + result = declare_hook_functions(spec->hooks, fd); + if (!result) goto wesrd_exit; - result &= write_hook_functions(spec->hooks, false, fd); + /* Vérification que le décodage est possible */ - result &= write_decoding_rules(spec->rules, false, CAT_CHECKED_CALL, - fd, arch, subarch, spec->bits, spec->conversions, pp, &quick_exit); + result &= check_bits_correctness(spec->bits, fd); + if (!result) goto wesrd_exit; - result &= write_decoding_rules(spec->rules, false, CAT_CALL, - fd, arch, subarch, spec->bits, spec->conversions, pp, &quick_exit); + dprintf(fd, "\n"); - /* Création des opérandes */ + /* Définition des champs bruts */ - result &= define_syntax_items(spec->syntax, fd, arch, spec->bits, spec->conversions, pp, &bad_exit); + result = define_used_bits_fields(spec->bits, fd); + if (!result) goto wesrd_exit; - /* Conclusion de la procédure */ + for (i = 0; i < spec->syntax_count && result; i++) + result = write_encoding_syntax(spec->syntaxes[i], fd, arch, spec->bits, openbar, &bad_exit); - if (quick_exit) - { - dprintf(fd, "\t quick_exit:\n"); - dprintf(fd, "\n"); - } + if (!result) + goto wesrd_exit; /* Encodage en dernier lieu */ @@ -396,43 +435,38 @@ bool write_encoding_spec_disass(const encoding_spec *spec, int fd, const char *a cast = build_cast_if_needed(encoding_fc); - dprintf(fd, "\t\t%s(%s(instr), \"%s\");\n", encoding_fc, cast, spec->prefix); + dprintf(fd, "\t%s(%s(result), \"%s\");\n", encoding_fc, cast, spec->prefix); free(cast); free(encoding_fc); - /* Conclusion globale */ - dprintf(fd, "\n"); - dprintf(fd, "\t\treturn instr;\n"); + /* Inscriptions des éventuelles fonctions ou propriété à lier */ + + result = write_hook_functions(spec->hooks, fd); + if (!result) goto wesrd_exit; + + /* Conclusion globale */ + + dprintf(fd, "\treturn result;\n"); dprintf(fd, "\n"); if (bad_exit) { - dprintf(fd, "\t bad_exit:\n"); + dprintf(fd, " bad_exit:\n"); dprintf(fd, "\n"); - dprintf(fd, "\t\tg_object_unref(G_OBJECT(instr));\n"); - dprintf(fd, "\t\treturn NULL;\n"); + dprintf(fd, "\tg_object_unref(G_OBJECT(result));\n"); + dprintf(fd, "\treturn NULL;\n"); dprintf(fd, "\n"); } - dprintf(fd, "\t}\n"); - - dprintf(fd, "\n"); - - dprintf(fd, "\tif (result == NULL)\n"); - dprintf(fd, "\t\tresult = %s_decode_%s%s_%s%u(raw);\n", - arch, keyword, details, spec->lprefix, spec->index); - - dprintf(fd, "\n"); - - free(keyword); + wesrd_exit: return result; @@ -441,15 +475,11 @@ bool write_encoding_spec_disass(const encoding_spec *spec, int fd, const char *a /****************************************************************************** * * -* Paramètres : spec = spécification servant de base à l'opération. * -* fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération. * -* subarch = sous-catégorie de cette même architecture. * -* ins = désignation première de l'instruction manipulée. * -* sep = caractère de séparation avant les détails. * -* details = particularités de l'instruction. * -* pp = pré-processeur pour les échanges de chaînes. * -* prefix = préfixe pour le type de définitions d'opérandes. * +* Paramètres : spec = spécification servant de base à l'opération. * +* fd = descripteur d'un flux ouvert en écriture. * +* arch = architecture visée par l'opération. * +* id = identifiant unique attribué à l'instruction. * +* prefix = préfixe pour le type de définitions d'opérandes. * * * * Description : Traduit en code une sous-fonction de désassemblage. * * * @@ -459,14 +489,13 @@ bool write_encoding_spec_disass(const encoding_spec *spec, int fd, const char *a * * ******************************************************************************/ -bool write_encoding_spec_format_disass(const encoding_spec *spec, int fd, const char *arch, const char *subarch, const char *ins, char sep, const char *details, const pre_processor *pp, const char *prefix) +bool write_encoding_spec_format_disass(const encoding_spec *spec, int fd, const char *arch, const instr_id *id, const char *prefix) { bool result; /* Bilan à retourner */ - bool quick_exit; /* Inclusion de sortie rapide ?*/ + unsigned int iid; /* Identifiant unique attribué */ bool bad_exit; /* Ajout d'une sortie d'échec ?*/ - const char *new_ins; /* Nouvelle définition de nom */ - - result = true; + conv_list *conversions; /* Conversions de la syntaxe */ + decoding_rules *rules; /* Règles de la syntaxe */ /* Déclarations préalables */ @@ -475,45 +504,47 @@ bool write_encoding_spec_format_disass(const encoding_spec *spec, int fd, const dprintf(fd, "\n"); - result &= declare_hook_functions(spec->hooks, true, fd); + result = declare_hook_functions(spec->hooks, fd); + if (!result) goto wesfd_exit; /* Création de l'instruction en elle-même */ - new_ins = get_new_keyword_from_syntax_items(spec->syntax); + iid = get_instruction_id_value(id); - if (new_ins != NULL) - dprintf(fd, "\tresult = g_%s_instruction_new(\"%s\");\n", arch, new_ins); - else - { - if (sep == '\0') - dprintf(fd, "\tresult = g_%s_instruction_new(\"%s\");\n", arch, ins); - else - dprintf(fd, "\tresult = g_%s_instruction_new(\"%s%c%s\");\n", arch, ins, sep, details); - } + dprintf(fd, "\tresult = g_%s_instruction_new(0x%x);\n", arch, iid); dprintf(fd, "\n"); /* Inscriptions des éventuelles fonctions ou propriété à lier */ - result &= write_hook_functions(spec->hooks, true, fd); + result = write_hook_functions(spec->hooks, fd); + if (!result) goto wesfd_exit; + + bad_exit = false; + + assert(spec->syntax_count <= 1); + + if (spec->syntax_count > 0) + { + conversions = get_conversions_in_encoding_syntax(spec->syntaxes[0]); + rules = get_rules_in_encoding_syntax(spec->syntaxes[0]); - quick_exit = false; + result = write_decoding_rules(rules, CAT_CHECKED_CALL, fd, arch, spec->bits, conversions, "", &bad_exit); + if (!result) goto wesfd_exit; - result &= write_decoding_rules(spec->rules, true, CAT_CHECKED_CALL, - fd, arch, subarch, spec->bits, spec->conversions, pp, &quick_exit); + result = write_decoding_rules(rules, CAT_CALL, fd, arch, spec->bits, conversions, "", &bad_exit); + if (!result) goto wesfd_exit; - result &= write_decoding_rules(spec->rules, true, CAT_CALL, - fd, arch, subarch, spec->bits, spec->conversions, pp, &quick_exit); + } /* Création des opérandes */ - dprintf(fd, "\tendian = g_arch_processor_get_endianness(G_ARCH_PROCESSOR(proc));\n"); + dprintf(fd, "\tendian = g_arch_processor_get_endianness(proc);\n"); dprintf(fd, "\n"); - bad_exit = false; - - result &= define_operands_loading(spec->format, fd, arch, prefix, &bad_exit); + result = define_operands_loading(spec->format, fd, arch, prefix, &bad_exit); + if (!result) goto wesfd_exit; /* Conclusion de la procédure */ @@ -521,11 +552,8 @@ bool write_encoding_spec_format_disass(const encoding_spec *spec, int fd, const dprintf(fd, "\n"); - if (quick_exit || bad_exit) + if (bad_exit) { - if (quick_exit) - dprintf(fd, " quick_exit:\n"); - if (bad_exit) dprintf(fd, " bad_exit:\n"); @@ -538,6 +566,8 @@ bool write_encoding_spec_format_disass(const encoding_spec *spec, int fd, const } + wesfd_exit: + return result; } diff --git a/tools/d2c/spec.h b/tools/d2c/encoding.h index e449587..787a3ca 100644 --- a/tools/d2c/spec.h +++ b/tools/d2c/encoding.h @@ -1,6 +1,6 @@ /* Chrysalide - Outil d'analyse de fichiers binaires - * spec.h - prototypes pour la représentation complète d'un encodage + * encoding.h - prototypes pour la représentation complète d'un encodage * * Copyright (C) 2014-2017 Cyrille Bagard * @@ -21,20 +21,19 @@ */ -#ifndef _TOOLS_D2C_SPEC_H -#define _TOOLS_D2C_SPEC_H +#ifndef _TOOLS_D2C_ENCODING_H +#define _TOOLS_D2C_ENCODING_H #include <stdbool.h> #include "pproc.h" +#include "syntax.h" #include "bits/manager.h" -#include "conv/manager.h" #include "format/manager.h" #include "hooks/manager.h" -#include "rules/manager.h" -#include "syntax/manager.h" +#include "id/manager.h" @@ -54,30 +53,30 @@ void define_encoding_spec_code_name(encoding_spec *, char *, unsigned int); /* Indique si une spécification se range dans une catégorie. */ bool has_encoding_spec_prefix(const encoding_spec *, const char *); +/* Construit la distinction propre à un encodage. */ +char *build_encoding_spec_prefix(const encoding_spec *spec); + /* Fournit le gestionnaire des définitions d'opérandes. */ operands_format *get_format_in_encoding_spec(const encoding_spec *); /* Fournit le gestionnaire des bits d'un encodage d'instruction. */ coding_bits *get_bits_in_encoding_spec(const encoding_spec *); -/* Fournit l'indicateur des écritures correctes d'assembleur. */ -asm_syntax *get_syntax_in_encoding_spec(const encoding_spec *); - -/* Fournit la liste des fonctions de conversion. */ -conv_list *get_conversions_in_encoding_spec(const encoding_spec *); - /* Fournit la liste des fonctions à lier à une instruction. */ instr_hooks *get_hooks_in_encoding_spec(const encoding_spec *); -/* Fournit un ensemble de règles supplémentaires éventuel. */ -decoding_rules *get_rules_in_encoding_spec(const encoding_spec *); +/* Enregistre une définition de syntaxe supplémentaire. */ +void push_new_encoding_syntax(encoding_spec *); + +/* Fournit un lien vers la définition de syntaxe courante. */ +encoding_syntax *get_current_encoding_syntax(const encoding_spec *); /* Traduit en code une sous-fonction de désassemblage. */ -bool write_encoding_spec_disass(const encoding_spec *, int, const char *, const char *, const char *, const char *, unsigned int, const pre_processor *); +bool write_encoding_spec_raw_disass(const encoding_spec *, int, const char *, const instr_id *, const pre_processor *); /* Traduit en code une sous-fonction de désassemblage. */ -bool write_encoding_spec_format_disass(const encoding_spec *, int, const char *, const char *, const char *, char, const char *, const pre_processor *, const char *); +bool write_encoding_spec_format_disass(const encoding_spec *, int, const char *, const instr_id *, const char *); -#endif /* _TOOLS_D2C_SPEC_H */ +#endif /* _TOOLS_D2C_ENCODING_H */ diff --git a/tools/d2c/format/Makefile.am b/tools/d2c/format/Makefile.am index c40b38e..8061804 100644 --- a/tools/d2c/format/Makefile.am +++ b/tools/d2c/format/Makefile.am @@ -26,6 +26,9 @@ libd2cformat_la_SOURCES = \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2cformat_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/format/tokens.l b/tools/d2c/format/tokens.l index 9dd9301..5db4afa 100644 --- a/tools/d2c/format/tokens.l +++ b/tools/d2c/format/tokens.l @@ -21,4 +21,12 @@ [A-Za-z0-9_]* { yylvalp->string = strdup(yytext); return OPS_TYPE; } "|" { return OR; } +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c format block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + + %% diff --git a/tools/d2c/globalgen.mk b/tools/d2c/globalgen.mk deleted file mode 100644 index ede457a..0000000 --- a/tools/d2c/globalgen.mk +++ /dev/null @@ -1,12 +0,0 @@ - -cini_verbose = $(cini_verbose_@AM_V@) -cini_verbose_ = $(cini_verbose_@AM_DEFAULT_V@) -cini_verbose_0 = @echo " INIT " `basename $@`; - -cgen_verbose = $(cgen_verbose_@AM_V@) -cgen_verbose_ = $(cgen_verbose_@AM_DEFAULT_V@) -cgen_verbose_0 = @echo " GEN " `basename $@`; - -cfini_verbose = $(cfini_verbose_@AM_V@) -cfini_verbose_ = $(cfini_verbose_@AM_DEFAULT_V@) -cfini_verbose_0 = @echo " FINI " `basename $@`; diff --git a/tools/d2c/grammar.y b/tools/d2c/grammar.y index 063d22b..0c79f04 100644 --- a/tools/d2c/grammar.y +++ b/tools/d2c/grammar.y @@ -1,13 +1,14 @@ %{ -#include <getopt.h> +#include <getopt.h>////// #include <fcntl.h> #include <stdio.h> #include <stdlib.h> #include <sys/mman.h> #include <sys/stat.h> +#include "decl.h" #include "tokens.h" @@ -27,79 +28,124 @@ static void *map_input_data(const char *, size_t *); #include "coder.h" #include "helpers.h" +#include "syntax.h" #include "args/decl.h" +#include "assert/decl.h" #include "bits/decl.h" #include "conv/decl.h" #include "format/decl.h" #include "hooks/decl.h" +#include "id/decl.h" +#include "pattern/decl.h" #include "rules/decl.h" -#include "syntax/decl.h" - - -#define handle_coder_format(c, r) \ - ({ \ - encoding_spec *__spec; \ - operands_format *__format; \ - bool __status; \ - __spec = get_current_encoding_spec(c); \ - __format = get_format_in_encoding_spec(__spec); \ - __status = load_format_from_raw_line(__format, r); \ - if (!__status) YYABORT; \ + + +#define handle_coder_id(c, r) \ + ({ \ + instr_id *__id; \ + bool __status; \ + __id = get_coder_instruction_id(c); \ + __status = load_id_from_raw_line(__id, r); \ + if (!__status) YYABORT; \ + }) + +#define handle_coder_desc(c, r) \ + ({ \ + instr_desc *__desc; \ + __desc = get_coder_instruction_desc(c); \ + set_instruction_description(__desc, r); \ + }) + +#define handle_coder_format(c, r) \ + ({ \ + encoding_spec *__spec; \ + operands_format *__format; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __format = get_format_in_encoding_spec(__spec); \ + __status = load_format_from_raw_line(__format, r); \ + if (!__status) YYABORT; \ }) -#define handle_coder_bits(c, e, r) \ - ({ \ - encoding_spec *__spec; \ - coding_bits *__bits; \ - bool __status; \ - __spec = get_current_encoding_spec(c); \ - __bits = get_bits_in_encoding_spec(__spec); \ - __status = load_bits_from_raw_line(__bits, e, r); \ - if (!__status) YYABORT; \ +#define handle_coder_bits(c, e, r) \ + ({ \ + encoding_spec *__spec; \ + coding_bits *__bits; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __bits = get_bits_in_encoding_spec(__spec); \ + __status = load_bits_from_raw_line(__bits, e, r); \ + if (!__status) YYABORT; \ }) -#define handle_coder_syntax(c, r) \ - ({ \ - encoding_spec *__spec; \ - asm_syntax *__syntax; \ - bool __status; \ - __spec = get_current_encoding_spec(c); \ - __syntax = get_syntax_in_encoding_spec(__spec); \ - __status = load_syntax_from_raw_line(__syntax, r); \ - if (!__status) YYABORT; \ +#define push_coder_new_syntax(c) \ + ({ \ + encoding_spec *__spec; \ + __spec = get_current_encoding_spec(c); \ + push_new_encoding_syntax(__spec); \ }) -#define handle_coder_conversions(c, r) \ - ({ \ - encoding_spec *__spec; \ - conv_list *__list; \ - bool __status; \ - __spec = get_current_encoding_spec(c); \ - __list = get_conversions_in_encoding_spec(__spec); \ - __status = load_convs_from_raw_block(__list, r); \ - if (!__status) YYABORT; \ +#define handle_coder_asm(c, r) \ + ({ \ + encoding_spec *__spec; \ + encoding_syntax *__syntax; \ + asm_pattern *__pattern; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __syntax = get_current_encoding_syntax(__spec); \ + __pattern = get_asm_pattern_in_encoding_syntax(__syntax); \ + __status = load_asm_pattern_from_raw_line(__pattern, r); \ + if (!__status) YYABORT; \ }) -#define handle_coder_hooks(c, r) \ - ({ \ - encoding_spec *__spec; \ - instr_hooks *__hooks;; \ - bool __status; \ - __spec = get_current_encoding_spec(c); \ - __hooks = get_hooks_in_encoding_spec(__spec); \ - __status = load_hooks_from_raw_line(__hooks, r); \ - if (!__status) YYABORT; \ +#define handle_coder_conversions(c, r) \ + ({ \ + encoding_spec *__spec; \ + encoding_syntax *__syntax; \ + conv_list *__list; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __syntax = get_current_encoding_syntax(__spec); \ + __list = get_conversions_in_encoding_syntax(__syntax); \ + __status = load_convs_from_raw_block(__list, r); \ + if (!__status) YYABORT; \ }) -#define handle_coder_rules(c, r) \ - ({ \ - encoding_spec *__spec; \ - decoding_rules *__rules; \ - bool __status; \ - __spec = get_current_encoding_spec(c); \ - __rules = get_rules_in_encoding_spec(__spec); \ - __status = load_rules_from_raw_block(__rules, r); \ - if (!__status) YYABORT; \ +#define handle_coder_assertions(c, r) \ + ({ \ + encoding_spec *__spec; \ + encoding_syntax *__syntax; \ + disass_assert *__dassert; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __syntax = get_current_encoding_syntax(__spec); \ + __dassert = get_assertions_for_encoding_syntax(__syntax); \ + __status = load_assertions_from_raw_block(__dassert, r); \ + if (!__status) YYABORT; \ + }) + +#define handle_coder_hooks(c, r) \ + ({ \ + encoding_spec *__spec; \ + instr_hooks *__hooks;; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __hooks = get_hooks_in_encoding_spec(__spec); \ + __status = load_hooks_from_raw_line(__hooks, r); \ + if (!__status) YYABORT; \ + }) + +#define handle_coder_rules(c, r) \ + ({ \ + encoding_spec *__spec; \ + encoding_syntax *__syntax; \ + decoding_rules *__rules; \ + bool __status; \ + __spec = get_current_encoding_spec(c); \ + __syntax = get_current_encoding_syntax(__spec); \ + __rules = get_rules_in_encoding_syntax(__syntax); \ + __status = load_rules_from_raw_block(__rules, r); \ + if (!__status) YYABORT; \ }) } @@ -138,16 +184,17 @@ YY_DECL; %token COPYRIGHT %token TITLE %token INS_NAME INS_SEP INS_DETAILS +%token ID %token DESC %token ENCODING %token TYPE NUMBER %token ENC_START ENC_END -%token FORMAT +%token FORMAT UNUSED %token WORD HALF %token SYNTAX -%token CONV +%token ASSERT CONV ASM %token HOOKS %token RULES @@ -167,13 +214,15 @@ YY_DECL; %% -input : name encodings { if (!dump_all_routines_using_coder(coder)) YYABORT; } - | name desc encodings { if (!dump_all_routines_using_coder(coder)) YYABORT; } +input : name id desc encodings + | name id encodings name : COPYRIGHT TITLE INS_NAME { save_notes_for_coder(coder, $1, $3, '\0', NULL); } | COPYRIGHT TITLE INS_NAME INS_SEP INS_DETAILS { save_notes_for_coder(coder, $1, $3, $4, $5); } -desc : DESC RAW_LINE +id : ID RAW_LINE { handle_coder_id(coder, $2); } + +desc : DESC RAW_BLOCK { handle_coder_desc(coder, $2); } encodings : /* empty */ | encoding encodings @@ -186,38 +235,50 @@ encoding : ENCODING TYPE NUMBER format_encoding { push_encoding_spec(coder, $2, /* Définitions à l'aide d'un format défini */ format_encoding : format format_content + | unused_format format : FORMAT RAW_LINE { handle_coder_format(coder, $2); } +unused_format : UNUSED RAW_LINE { handle_coder_format(coder, $2); mark_coder_as_useless(coder); } + format_content : /* empty */ - | hooks format_content - | rules format_content + | SYNTAX { push_coder_new_syntax(coder); } format_syntax + | hooks format_syntax + +format_syntax : /* empty */ + | rules format_syntax /* Définitions à l'aide de données brutes */ raw_encoding : bitfield raw_content +bitfield : HALF RAW_LINE { handle_coder_bits(coder, 16, $2); } + | WORD RAW_LINE { handle_coder_bits(coder, 32, $2); } + raw_content : /* empty */ - | syntax raw_content - | conversions raw_content + | SYNTAX { push_coder_new_syntax(coder); } raw_syntax raw_content | hooks raw_content - | rules raw_content -bitfield : HALF RAW_LINE { handle_coder_bits(coder, 16, $2); } - | WORD RAW_LINE { handle_coder_bits(coder, 32, $2); } +raw_syntax : /* empty */ + | assertions raw_syntax + | conversions raw_syntax + | asm raw_syntax + | rules raw_syntax -syntax : SYNTAX RAW_LINE { handle_coder_syntax(coder, $2); } +assertions : ASSERT RAW_BLOCK { handle_coder_assertions(coder, $2); } conversions : CONV RAW_BLOCK { handle_coder_conversions(coder, $2); } +asm : ASM RAW_LINE { handle_coder_asm(coder, $2); } -/* Définitions communes */ -hooks : HOOKS RAW_BLOCK { handle_coder_hooks(coder, $2); } +/* Définitions communes */ rules : RULES RAW_BLOCK { handle_coder_rules(coder, $2); } +hooks : HOOKS RAW_BLOCK { handle_coder_hooks(coder, $2); } + %% @@ -238,7 +299,7 @@ rules : RULES RAW_BLOCK { handle_coder_rules(coder, $2); } static int yyerror(rented_coder *coder, char *temp, char *msg) { - printf("yyerror line %d: %s\n", yyget_lineno(), msg); + printf("YYERROR line %d: %s\n", yyget_lineno(), msg); return 0; @@ -247,46 +308,6 @@ static int yyerror(rented_coder *coder, char *temp, char *msg) /****************************************************************************** * * -* Paramètres : argv0 = nombre du programme exécuté. * -* * -* Description : Affiche des indications sur l'utilisation du programme. * -* * -* Retour : - * -* * -* Remarques : - * -* * -******************************************************************************/ - -static void show_usage(const char *argv0) -{ - printf("\n"); - - printf("Usage: %s [options]\n", argv0); - - printf("\n"); - - printf("Options:\n"); - - printf("\n"); - - printf("\t-h | --help\t\t\tDisplay this messsage.\n"); - printf("\t-i | --input <file>\t\tProvide the input file containing the description.\n"); - printf("\t-t | --type <raw|format>\tSet the type of the input file.\n"); - printf("\t-d | --dir <string>\t\tSpecify the main output directory.\n"); - printf("\t-a | --arch <string>\t\tDefine the archicture to handle.\n"); - printf("\t-H | --header <string>\t\tSet the base of the #ifndef / #define game.\n"); - printf("\t-e | --encoding <none|string>\tDefine encoding prefixes for files.\n"); - printf("\t-M | --macro <string>\t\tRegister some conversion functions.\n"); - printf("\t-n | --operand <string>\t\tRegister a function producing final operands.\n"); - printf("\t-p | --prefix <string>\t\tDefine a prefix to format operand type constants (see -t).\n"); - - printf("\n"); - -} - - -/****************************************************************************** -* * * Paramètres : filename = chemin du fichier à charger en mémoire. * * length = taille de l'espace mémoie à mettre en place. [OUT]* * * @@ -344,155 +365,47 @@ static void *map_input_data(const char *filename, size_t *length) /****************************************************************************** * * -* Paramètres : argc = nombre d'arguments dans la ligne de commande. * -* argv = arguments de la ligne de commande. * +* Paramètres : filename = chemin d'accès à un fichier à traiter. * +* pp = préprocesseur déjà chargé à intégrer. * * * -* Description : Point d'entrée du programme. * +* Description : Charge en mémoire la définition contenue dans un fichier. * * * -* Retour : EXIT_SUCCESS si le prgm s'est déroulé sans encombres. * +* Retour : Définition chargée ou NULL en cas d'erreur. * * * * Remarques : - * * * ******************************************************************************/ -int main(int argc, char **argv) +rented_coder *process_definition_file(const char *filename, pre_processor *pp) { - int result; /* Bilan à retourner */ - rented_coder *coder; /* Codeur à briffer & employer */ - int index; /* Indice de fichier à traiter */ - bool need_help; /* Affichage de l'aide ? */ - bool has_error; /* Erreur dans la ligne de cmd.*/ - int ret; /* Bilan d'une lecture d'arg. */ - char *sep; /* Caratère '=' en coupure */ + rented_coder *result; /* Codeur à briffer et renvoyer*/ size_t length; /* Nombre d'octets à traiter */ char *content; /* Contenu brut à analyser */ char *temp; /* Zone de travail temporaire */ YY_BUFFER_STATE state; /* Contexte d'analyse */ + int status; /* Bilan d'une analyse */ - static struct option long_options[] = { - - { "help", no_argument, NULL, 'h' }, - { "input", required_argument, NULL, 'i' }, - { "type", required_argument, NULL, 't' }, - { "dir", required_argument, NULL, 'd' }, - { "arch", required_argument, NULL, 'a' }, - { "header", required_argument, NULL, 'H' }, - { "encoding", required_argument, NULL, 'e' }, - { "macro", required_argument, NULL, 'M' }, - { "operand", required_argument, NULL, 'n' }, - { "prefix", required_argument, NULL, 'p' }, - { NULL, 0, NULL, 0 } - - }; - - result = EXIT_SUCCESS; - - coder = create_coder(); - - index = 0; - - need_help = false; - has_error = false; - - while (!has_error) - { - ret = getopt_long(argc, argv, "hi:t:d:a:H:e:M:n:p:", long_options, &index); - if (ret == -1) break; - - switch (ret) - { - case 'h': - need_help = true; - break; - - case 'i': - set_coder_input_file(coder, optarg); - break; - - case 't': - if (strcmp(optarg, "raw") == 0) - set_coder_input_type(coder, IOT_RAW); - else if (strcmp(optarg, "format") == 0) - set_coder_input_type(coder, IOT_FORMAT); - break; - - case 'd': - set_coder_output_directory(coder, optarg); - break; - - case 'a': - set_coder_arch(coder, optarg); - break; - - case 'H': - set_coder_header_base(coder, optarg); - break; - - case 'e': - - if (strcmp(optarg, "none") == 0) - register_empty_encoding(get_coder_pre_proc(coder)); - - else - { - sep = strchr(optarg, '='); - has_error = (sep == NULL); - - if (!has_error) - { - *sep = '\0'; - register_encoding(get_coder_pre_proc(coder), optarg, sep + 1); - } - - } - - break; - - case 'M': - - sep = strchr(optarg, '='); - has_error = (sep == NULL); - - if (!has_error) - { - *sep = '\0'; - define_macro(get_coder_pre_proc(coder), optarg, sep + 1); - } - - break; - - case 'n': - register_as_operand_producer(get_coder_pre_proc(coder), optarg); - break; - - case 'p': - set_coder_const_prefix(coder, optarg); - break; - - } - - } - - if (need_help || has_error || !do_basic_checks_with_coder(coder) || optind != argc) - { - show_usage(argv[0]); - result = (need_help ? EXIT_SUCCESS : EXIT_FAILURE); - printf("need help ? %d - result = %d vs %d\n", need_help, result, EXIT_SUCCESS); - goto exit; - } - - content = map_input_data(get_coder_input_file(coder), &length); + content = map_input_data(filename, &length); if (content == MAP_FAILED) { - result = EXIT_FAILURE; + result = NULL; goto exit; } + result = create_coder(pp); + set_coder_input_file(result, filename); + temp = (char *)calloc(length, sizeof(char)); state = d2c__scan_bytes(content, length); - result = yyparse(coder, temp); + status = yyparse(result, temp); + + if (status == EXIT_FAILURE) + { + delete_coder(result); + result = NULL; + } yy_delete_buffer(state); @@ -502,8 +415,6 @@ int main(int argc, char **argv) exit: - delete_coder(coder); - return result; } diff --git a/tools/d2c/helpers.c b/tools/d2c/helpers.c index 8cc71cb..3f79bc1 100644 --- a/tools/d2c/helpers.c +++ b/tools/d2c/helpers.c @@ -125,7 +125,7 @@ char *make_callable(const char *raw, bool details) { max = strlen(result) + 1; result = (char *)realloc(result, max); - memmove(result + 1, result, max - 1); + memmove(result + 1, result, max); result[0] = '_'; } diff --git a/tools/d2c/hooks/Makefile.am b/tools/d2c/hooks/Makefile.am index 27d88ec..c049ac5 100644 --- a/tools/d2c/hooks/Makefile.am +++ b/tools/d2c/hooks/Makefile.am @@ -26,6 +26,9 @@ libd2chooks_la_SOURCES = \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2chooks_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/hooks/manager.c b/tools/d2c/hooks/manager.c index ff2749b..02544d0 100644 --- a/tools/d2c/hooks/manager.c +++ b/tools/d2c/hooks/manager.c @@ -134,7 +134,6 @@ void register_hook_function(instr_hooks *hooks, char *type, char *name) /****************************************************************************** * * * Paramètres : hooks = gestionnaire d'un ensemble de fonctions associées. * -* top = indique si l'écriture se réalise au plus haut niveau.* * fd = descripteur d'un flux ouvert en écriture. * * * * Description : Déclare des opérations complémentaires pour une instruction. * @@ -145,7 +144,7 @@ void register_hook_function(instr_hooks *hooks, char *type, char *name) * * ******************************************************************************/ -bool declare_hook_functions(const instr_hooks *hooks, bool top, int fd) +bool declare_hook_functions(const instr_hooks *hooks, int fd) { bool result; /* Bilan à retourner */ size_t i; /* Boucle de parcours #1 */ @@ -176,27 +175,18 @@ bool declare_hook_functions(const instr_hooks *hooks, bool top, int fd) if (hooks->func_count > 0) { - if (!top) - dprintf(fd, "\t"); - dprintf(fd, "\tstatic const instr_hook_fc hooks[IPH_COUNT] = {\n\n"); for (i = 0; i < (sizeof(hook_types) / sizeof(hook_types[0])); i++) { func = find_hook_by_name(hooks, hook_types[i]); - if (!top) - dprintf(fd, "\t"); - dprintf(fd, "\t\t[IPH_%s] = (instr_hook_fc)%s,\n", hook_types[i], func != NULL ? func->name : "NULL"); } dprintf(fd, "\n"); - if (!top) - dprintf(fd, "\t"); - dprintf(fd, "\t};\n"); dprintf(fd, "\n"); @@ -211,7 +201,6 @@ bool declare_hook_functions(const instr_hooks *hooks, bool top, int fd) /****************************************************************************** * * * Paramètres : hooks = gestionnaire d'un ensemble de fonctions associées. * -* top = indique si l'écriture se réalise au plus haut niveau.* * fd = descripteur d'un flux ouvert en écriture. * * * * Description : Associe dans le code des fonctions à une instruction. * @@ -222,7 +211,7 @@ bool declare_hook_functions(const instr_hooks *hooks, bool top, int fd) * * ******************************************************************************/ -bool write_hook_functions(const instr_hooks *hooks, bool top, int fd) +bool write_hook_functions(const instr_hooks *hooks, int fd) { bool result; /* Bilan à retourner */ @@ -230,11 +219,7 @@ bool write_hook_functions(const instr_hooks *hooks, bool top, int fd) if (hooks->func_count > 0) { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\tg_arch_instruction_set_hooks(%s, hooks);\n", - top ? "result" : "instr"); + dprintf(fd, "\tg_arch_instruction_set_hooks(result, hooks);\n"); dprintf(fd, "\n"); diff --git a/tools/d2c/hooks/manager.h b/tools/d2c/hooks/manager.h index c502ab0..3647b74 100644 --- a/tools/d2c/hooks/manager.h +++ b/tools/d2c/hooks/manager.h @@ -44,10 +44,10 @@ void delete_instr_hooks(instr_hooks *); void register_hook_function(instr_hooks *, char *, char *); /* Déclare des opérations complémentaires pour une instruction. */ -bool declare_hook_functions(const instr_hooks *, bool, int); +bool declare_hook_functions(const instr_hooks *, int); /* Associe dans le code des fonctions à une instruction. */ -bool write_hook_functions(const instr_hooks *, bool, int); +bool write_hook_functions(const instr_hooks *, int); diff --git a/tools/d2c/hooks/tokens.l b/tools/d2c/hooks/tokens.l index 6aebe87..1f72d2c 100644 --- a/tools/d2c/hooks/tokens.l +++ b/tools/d2c/hooks/tokens.l @@ -16,11 +16,17 @@ %% -" " { } +[ \t\n] { } -[ \t\n]+ { } [a-z_][a-z0-9_]* { yylvalp->string = strdup(yytext); return NAME; } "=" { return EQ; } +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c hooks block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + %% diff --git a/tools/d2c/syntax/Makefile.am b/tools/d2c/id/Makefile.am index 7529978..c3d18b8 100644 --- a/tools/d2c/syntax/Makefile.am +++ b/tools/d2c/id/Makefile.am @@ -6,26 +6,29 @@ BUILT_SOURCES = grammar.h # afin de conserver des noms de fichiers simples, ie sans le nom de la # bibliothèque de sortie en préfixe. -AM_YFLAGS = -v -d -p syntax_ +AM_YFLAGS = -v -d -p id_ -AM_LFLAGS = -P syntax_ -o lex.yy.c --header-file=tokens.h \ - -Dyyget_lineno=syntax_get_lineno \ - -Dyy_scan_string=syntax__scan_string \ - -Dyy_delete_buffer=syntax__delete_buffer +AM_LFLAGS = -P id_ -o lex.yy.c --header-file=tokens.h \ + -Dyyget_lineno=id_get_lineno \ + -Dyy_scan_string=id__scan_string \ + -Dyy_delete_buffer=id__delete_buffer AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) -noinst_LTLIBRARIES = libd2csyntax.la +noinst_LTLIBRARIES = libd2cid.la .NOTPARALLEL: $(noinst_LTLIBRARIES) -libd2csyntax_la_SOURCES = \ +libd2cid_la_SOURCES = \ decl.h \ manager.h manager.c \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2cid_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/id/decl.h b/tools/d2c/id/decl.h new file mode 100644 index 0000000..0c3b3e2 --- /dev/null +++ b/tools/d2c/id/decl.h @@ -0,0 +1,40 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * decl.h - déclarations de prototypes utiles + * + * Copyright (C) 2018 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _TOOLS_D2C_ID_DECL_H +#define _TOOLS_D2C_ID_DECL_H + + +#include <stdbool.h> + + +#include "manager.h" + + + +/* Interprête des données relatives à un identifiant. */ +bool load_id_from_raw_line(instr_id *, const char *); + + + +#endif /* _TOOLS_D2C_BITS_DECL_H */ diff --git a/tools/d2c/id/grammar.y b/tools/d2c/id/grammar.y new file mode 100644 index 0000000..4799fcc --- /dev/null +++ b/tools/d2c/id/grammar.y @@ -0,0 +1,107 @@ + +%{ + +#include "tokens.h" + + +/* Affiche un message d'erreur suite à l'analyse en échec. */ +static int yyerror(instr_id *, char *); + +%} + + +%code requires { + +#include "decl.h" + +} + + +%union { + + unsigned int value; /* Valeur numérique */ + +} + + +%define api.pure full + +%parse-param { instr_id *id } + +%code provides { + +#define YY_DECL \ + int id_lex(YYSTYPE *yylvalp) + +YY_DECL; + +} + + +%token VALUE + +%type <value> VALUE + + + +%% + + +id : VALUE { set_instruction_id_value(id, $1); } + + +%% + + +/****************************************************************************** +* * +* Paramètres : id = structure impliquée dans le processus. * +* msg = message d'erreur. * +* * +* Description : Affiche un message d'erreur suite à l'analyse en échec. * +* * +* Retour : 0 * +* * +* Remarques : - * +* * +******************************************************************************/ + +static int yyerror(instr_id *id, char *msg) +{ + printf("id yyerror line %d: %s\n", yyget_lineno(), msg); + + return 0; + +} + + +/****************************************************************************** +* * +* Paramètres : id = structure à constituer à partir de données lues. * +* raw = données brutes à analyser. * +* * +* Description : Interprête des données relatives à un identifiant. * +* * +* Retour : true si l'opération s'est bien déroulée, false sinon. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool load_id_from_raw_line(instr_id *id, const char *raw) +{ + bool result; /* Bilan à faire remonter */ + YY_BUFFER_STATE state; /* Support d'analyse */ + int status; /* Bilan de l'analyse */ + + state = yy_scan_string(raw); + + status = yyparse(id); + + result = (status == 0); + + yy_delete_buffer(state); + + return result; + +} diff --git a/tools/d2c/id/manager.c b/tools/d2c/id/manager.c new file mode 100644 index 0000000..7cfc916 --- /dev/null +++ b/tools/d2c/id/manager.c @@ -0,0 +1,126 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * manager.c - enregistrement de la définition d'un identifiant + * + * Copyright (C) 2016-2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "manager.h" + + +#include <assert.h> +#include <malloc.h> +#include <stdbool.h> + + + +/* Mémorisation de la définition d'un identifiant */ +struct _instr_id +{ + unsigned int value; /* Identifiant numérique unique*/ + bool set; /* Validité de la valeur */ + +}; + + + +/****************************************************************************** +* * +* Paramètres : - * +* * +* Description : Crée un nouveau gestionnaire de définitions d'identifiant. * +* * +* Retour : Nouvelle structure prête à emploi. * +* * +* Remarques : - * +* * +******************************************************************************/ + +instr_id *create_instruction_id(void) +{ + instr_id *result; /* Définition vierge à renvoyer*/ + + result = (instr_id *)calloc(1, sizeof(instr_id)); + + result->set = false; + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : id = gestionnaire de définition d'identifiant à libérer. * +* * +* Description : Supprime de la mémoire un gestionnaire d'identifiant. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void delete_instruction_id(instr_id *id) +{ + free(id); + +} + + +/****************************************************************************** +* * +* Paramètres : id = gestionnaire de définition d'identifiant à traiter. * +* value = valeur à attribuer à une instruction. * +* * +* Description : Associe une valeur unique à une instruction. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void set_instruction_id_value(instr_id *id, unsigned int value) +{ + id->value = value; + id->set = true; + +} + + +/****************************************************************************** +* * +* Paramètres : id = gestionnaire de définition d'identifiant à traiter. * +* * +* Description : Associe une valeur unique à une instruction. * +* * +* Retour : Valeur attribuée à une instruction. * +* * +* Remarques : - * +* * +******************************************************************************/ + +unsigned int get_instruction_id_value(const instr_id *id) +{ + assert(id->set); + + return id->value; + +} diff --git a/plugins/arm/v7/opdefs/sub_A88224.d b/tools/d2c/id/manager.h index 5ef4e4d..d24fbd7 100644 --- a/plugins/arm/v7/opdefs/sub_A88224.d +++ b/tools/d2c/id/manager.h @@ -1,8 +1,8 @@ /* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 + * manager.h - prototypes pour l'enregistrement de la définition d'un identifiant * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2018 Cyrille Bagard * * This file is part of Chrysalide. * @@ -21,32 +21,27 @@ */ -@title SUB (register-shifted register) +#ifndef _TOOLS_D2C_ID_MANAGER_H +#define _TOOLS_D2C_ID_MANAGER_H -@desc This instruction subtracts a register-shifted register value from a register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. -@encoding (A1) { - @word cond(4) 0 0 0 0 0 1 0 S(1) Rn(4) Rd(4) Rs(4) 0 type(2) 1 Rm(4) +/* Mémorisation de la définition d'un identifiant */ +typedef struct _instr_id instr_id; - @syntax <reg_D> <reg_N> <reg_M> <reg_shift> - @conv { +/* Crée un nouveau gestionnaire de définitions d'identifiant. */ +instr_id *create_instruction_id(void); - reg_shift = RegisterShift(type, Rs) - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') +/* Supprime de la mémoire un gestionnaire d'identifiant. */ +void delete_instruction_id(instr_id *); - } +/* Associe une valeur unique à une instruction. */ +void set_instruction_id_value(instr_id *, unsigned int); - @rules { +/* Associe une valeur unique à une instruction. */ +unsigned int get_instruction_id_value(const instr_id *); - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) - } - -} +#endif /* _TOOLS_D2C_ID_MANAGER_H */ diff --git a/tools/d2c/id/tokens.l b/tools/d2c/id/tokens.l new file mode 100644 index 0000000..24f18f1 --- /dev/null +++ b/tools/d2c/id/tokens.l @@ -0,0 +1,33 @@ + +%top { + +#include <stdlib.h> + +#include "grammar.h" + +} + + +%option noyywrap +%option nounput +%option noinput +%option yylineno +%option noyy_top_state + + +%% + + +" " { } + +[0-9_]* { yylvalp->value = strtoul(yytext, NULL, 10); return VALUE; } + +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c id block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + + +%% diff --git a/tools/d2c/manual.h b/tools/d2c/manual.h index e3375b8..4106702 100644 --- a/tools/d2c/manual.h +++ b/tools/d2c/manual.h @@ -25,40 +25,43 @@ #define _TOOLS_D2C_MANUAL_H -#define read_block(tmp) \ - ({ \ - unsigned int __depth; \ - bool __is_string; \ - char *__iter; \ - \ - __depth = 1; \ - __is_string = false; \ - \ - for (__iter = temp; __depth > 0; __iter += (__depth > 0 ? 1 : 0)) \ - { \ - *__iter = input(); \ - \ - switch (*__iter) \ - { \ - case '"': \ - __is_string = !__is_string; \ - break; \ - \ - case '{': \ - if (!__is_string) __depth++; \ - break; \ - \ - case '}': \ - if (!__is_string) __depth--; \ - break; \ - \ - } \ - \ - } \ - \ - *__iter = '\0'; \ - \ - printf("\n\nBLOCK\n''''\n%s\n''''\n\n", temp); \ +#define read_block(tmp) \ + ({ \ + unsigned int __depth; \ + bool __is_string; \ + char *__iter; \ + \ + __depth = 1; \ + __is_string = false; \ + \ + for (__iter = temp; __depth > 0; __iter += (__depth > 0 ? 1 : 0)) \ + { \ + *__iter = input(); \ + \ + switch (*__iter) \ + { \ + case '"': \ + __is_string = !__is_string; \ + break; \ + \ + case '{': \ + if (!__is_string) __depth++; \ + break; \ + \ + case '}': \ + if (!__is_string) \ + { \ + __depth--; \ + if (__depth == 0) unput('}'); \ + } \ + break; \ + \ + } \ + \ + } \ + \ + *__iter = '\0'; \ + \ }) diff --git a/tools/d2c/pattern/Makefile.am b/tools/d2c/pattern/Makefile.am new file mode 100644 index 0000000..458eed0 --- /dev/null +++ b/tools/d2c/pattern/Makefile.am @@ -0,0 +1,37 @@ + +BUILT_SOURCES = grammar.h + + +# On évite d'utiliser les variables personnalisées de type *_la_[YL]FLAGS +# afin de conserver des noms de fichiers simples, ie sans le nom de la +# bibliothèque de sortie en préfixe. + +AM_YFLAGS = -v -d -p pattern_ + +AM_LFLAGS = -P pattern_ -o lex.yy.c --header-file=tokens.h \ + -Dyyget_lineno=pattern_get_lineno \ + -Dyy_scan_string=pattern__scan_string \ + -Dyy_delete_buffer=pattern__delete_buffer + +AM_CFLAGS = $(DEBUG_CFLAGS) $(WARNING_FLAGS) + + +noinst_LTLIBRARIES = libd2cpattern.la + +.NOTPARALLEL: $(noinst_LTLIBRARIES) + +libd2cpattern_la_SOURCES = \ + decl.h \ + manager.h manager.c \ + tokens.l \ + grammar.y + +# _GNU_SOURCE : asprintf +libd2cpattern_la_CFLAGS = -D_GNU_SOURCE + + +# Automake fait les choses à moitié +CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h + +# Pareil : de tous les fichiers générés, seule la sortie de Flex saute pour les distributions ! +EXTRA_DIST = tokens.h diff --git a/tools/d2c/syntax/decl.h b/tools/d2c/pattern/decl.h index 300ab80..c834ced 100644 --- a/tools/d2c/syntax/decl.h +++ b/tools/d2c/pattern/decl.h @@ -21,8 +21,8 @@ */ -#ifndef _TOOLS_D2C_SYNTAX_DECL_H -#define _TOOLS_D2C_SYNTAX_DECL_H +#ifndef _TOOLS_D2C_PATTERN_DECL_H +#define _TOOLS_D2C_PATTERN_DECL_H #include "manager.h" @@ -30,8 +30,8 @@ /* Interprête des données liées à une définition de syntaxe. */ -bool load_syntax_from_raw_line(asm_syntax *, const char *); +bool load_asm_pattern_from_raw_line(asm_pattern *, const char *); -#endif /* _TOOLS_D2C_SYNTAX_DECL_H */ +#endif /* _TOOLS_D2C_PATTERN_DECL_H */ diff --git a/tools/d2c/syntax/grammar.y b/tools/d2c/pattern/grammar.y index 3952b9a..c3399cc 100644 --- a/tools/d2c/syntax/grammar.y +++ b/tools/d2c/pattern/grammar.y @@ -5,7 +5,7 @@ /* Affiche un message d'erreur suite à l'analyse en échec. */ -static int yyerror(asm_syntax *, char *); +static int yyerror(asm_pattern *, char *); %} @@ -26,30 +26,28 @@ static int yyerror(asm_syntax *, char *); %define api.pure full -%parse-param { asm_syntax *syntax } +%parse-param { asm_pattern *pattern } %code provides { #define YY_DECL \ - int syntax_lex(YYSTYPE *yylvalp) + int pattern_lex(YYSTYPE *yylvalp) YY_DECL; } -%token OPERAND_NAME OPERAND_INTERNAL OPERAND_VISIBLE +%token OPERAND -%type <string> OPERAND_NAME OPERAND_INTERNAL OPERAND_VISIBLE +%type <string> OPERAND %% operands : /* empty */ - | operands OPERAND_NAME { register_syntax_item(syntax, $2, SIT_KEYWORD); } - | operands OPERAND_INTERNAL { register_syntax_item(syntax, $2, SIT_INT_OPERAND); } - | operands OPERAND_VISIBLE { register_syntax_item(syntax, $2, SIT_EXT_OPERAND); } + | operands OPERAND { register_asm_pattern_item(pattern, $2); } %% @@ -57,8 +55,8 @@ operands : /* empty */ /****************************************************************************** * * -* Paramètres : syntax = structure impliquée dans le processus. * -* msg = message d'erreur. * +* Paramètres : pattern = structure impliquée dans le processus. * +* msg = message d'erreur. * * * * Description : Affiche un message d'erreur suite à l'analyse en échec. * * * @@ -68,7 +66,7 @@ operands : /* empty */ * * ******************************************************************************/ -static int yyerror(asm_syntax *syntax, char *msg) +static int yyerror(asm_pattern *pattern, char *msg) { printf("syntax yyerror line %d: %s\n", yyget_lineno(), msg); @@ -79,8 +77,8 @@ static int yyerror(asm_syntax *syntax, char *msg) /****************************************************************************** * * -* Paramètres : syntax = structure à constituer à partir de données lues. * -* raw = données brutes à analyser. * +* Paramètres : pattern = structure à constituer à partir de données lues. * +* raw = données brutes à analyser. * * * * Description : Interprête des données liées à une définition de syntaxe. * * * @@ -90,7 +88,7 @@ static int yyerror(asm_syntax *syntax, char *msg) * * ******************************************************************************/ -bool load_syntax_from_raw_line(asm_syntax *syntax, const char *raw) +bool load_asm_pattern_from_raw_line(asm_pattern *pattern, const char *raw) { bool result; /* Bilan à faire remonter */ YY_BUFFER_STATE state; /* Support d'analyse */ @@ -98,7 +96,7 @@ bool load_syntax_from_raw_line(asm_syntax *syntax, const char *raw) state = yy_scan_string(raw); - status = yyparse(syntax); + status = yyparse(pattern); result = (status == 0); diff --git a/tools/d2c/syntax/manager.c b/tools/d2c/pattern/manager.c index 6857e9a..a756745 100644 --- a/tools/d2c/syntax/manager.c +++ b/tools/d2c/pattern/manager.c @@ -24,6 +24,7 @@ #include "manager.h" +#include <assert.h> #include <malloc.h> #include <string.h> @@ -45,13 +46,12 @@ typedef enum _SyntaxItemFlags typedef struct _syntax_item { char *name; /* Désignation humaine */ - SyntaxItemType impact; /* Portée de l'élément */ SyntaxItemFlags flags; /* Propriétés supplémentaires */ } syntax_item; /* Syntaxe d'une ligne d'assembleur */ -struct _asm_syntax +struct _asm_pattern { syntax_item *items; /* Eléments de la syntaxe */ size_t items_count; /* Nombre de ces éléments */ @@ -72,11 +72,11 @@ struct _asm_syntax * * ******************************************************************************/ -asm_syntax *create_asm_syntax(void) +asm_pattern *create_asm_pattern(void) { - asm_syntax *result; /* Définition vierge à renvoyer*/ + asm_pattern *result; /* Définition vierge à renvoyer*/ - result = (asm_syntax *)calloc(1, sizeof(asm_syntax)); + result = (asm_pattern *)calloc(1, sizeof(asm_pattern)); return result; @@ -85,7 +85,7 @@ asm_syntax *create_asm_syntax(void) /****************************************************************************** * * -* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * +* Paramètres : pattern = gestionnaire d'un ensemble d'éléments de syntaxe. * * * * Description : Supprime de la mémoire un indicateur d'écriture ASM. * * * @@ -95,26 +95,25 @@ asm_syntax *create_asm_syntax(void) * * ******************************************************************************/ -void delete_asm_syntax(asm_syntax *syntax) +void delete_asm_pattern(asm_pattern *pattern) { size_t i; /* Boucle de parcours */ - for (i = 0; i < syntax->items_count; i++) - free(syntax->items[i].name); + for (i = 0; i < pattern->items_count; i++) + free(pattern->items[i].name); - if (syntax->items != NULL) - free(syntax->items); + if (pattern->items != NULL) + free(pattern->items); - free(syntax); + free(pattern); } /****************************************************************************** * * -* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * -* name = désignation de l'opérande dans la spécification. * -* impact = précise la portée effective de l'opérande * +* Paramètres : pattern = gestionnaire d'un ensemble d'éléments de syntaxe. * +* name = désignation de l'opérande dans la spécification. * * * * Description : Enregistre la présence d'un nouvel opérande dans la syntaxe. * * * @@ -124,14 +123,14 @@ void delete_asm_syntax(asm_syntax *syntax) * * ******************************************************************************/ -void register_syntax_item(asm_syntax *syntax, char *name, SyntaxItemType impact) +void register_asm_pattern_item(asm_pattern *pattern, char *name) { syntax_item *item; /* Nouvelle prise en compte */ size_t len; /* Taille du nom fourni */ - syntax->items = (syntax_item *)realloc(syntax->items, ++syntax->items_count * sizeof(syntax_item)); + pattern->items = (syntax_item *)realloc(pattern->items, ++pattern->items_count * sizeof(syntax_item)); - item = &syntax->items[syntax->items_count - 1]; + item = &pattern->items[pattern->items_count - 1]; /* Récupération des drapeaux */ @@ -156,21 +155,16 @@ void register_syntax_item(asm_syntax *syntax, char *name, SyntaxItemType impact) } - if (impact == SIT_KEYWORD) - item->name = name; - else - item->name = make_string_lower(name); - - item->impact = impact; + item->name = make_string_lower(name); } /****************************************************************************** * * -* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * -* bits = gestionnaire des bits d'encodage. * -* list = liste de l'ensemble des fonctions de conversion. * +* Paramètres : pattern = gestionnaire d'un ensemble d'éléments de syntaxe. * +* bits = gestionnaire des bits d'encodage. * +* list = liste de l'ensemble des fonctions de conversion. * * * * Description : Marque les champs de bits effectivement utilisés. * * * @@ -180,7 +174,7 @@ void register_syntax_item(asm_syntax *syntax, char *name, SyntaxItemType impact) * * ******************************************************************************/ -bool mark_syntax_items(const asm_syntax *syntax, const coding_bits *bits, const conv_list *list) +bool mark_asm_pattern_items(const asm_pattern *pattern, const coding_bits *bits, const conv_list *list) { bool result; /* Bilan à retourner */ size_t i; /* Boucle de parcours */ @@ -189,10 +183,9 @@ bool mark_syntax_items(const asm_syntax *syntax, const coding_bits *bits, const result = true; - for (i = 0; i < syntax->items_count && result; i++) + for (i = 1; i < pattern->items_count && result; i++) { - item = &syntax->items[i]; - if (item->impact == SIT_KEYWORD) continue; + item = &pattern->items[i]; func = find_named_conv_in_list(list, item->name); if (func == NULL) @@ -212,11 +205,12 @@ bool mark_syntax_items(const asm_syntax *syntax, const coding_bits *bits, const /****************************************************************************** * * -* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * -* fd = descripteur d'un flux ouvert en écriture. * -* bits = gestionnaire des bits d'encodage. * -* list = liste de l'ensemble des fonctions de conversion. * -* wide = taille des mots décodés. * +* Paramètres : pattern = gestionnaire d'un ensemble d'éléments de syntaxe. * +* fd = descripteur d'un flux ouvert en écriture. * +* bits = gestionnaire des bits d'encodage. * +* list = liste de l'ensemble des fonctions de conversion. * +* tab = décalage éventuel selon l'inclusion. * +* imm_decl = une déclaration d'immédiat est déjà faite ? [OUT] * * * * Description : Déclare les variables C associées aux opérandes de syntaxe. * * * @@ -226,36 +220,31 @@ bool mark_syntax_items(const asm_syntax *syntax, const coding_bits *bits, const * * ******************************************************************************/ -bool declare_syntax_items(const asm_syntax *syntax, int fd, const coding_bits *bits, const conv_list *list, unsigned int wide) +bool declare_asm_pattern(const asm_pattern *pattern, int fd, const coding_bits *bits, const conv_list *list, const char *tab, bool *imm_decl) { bool result; /* Bilan à retourner */ - bool has_operand; /* Présence d'un opérande */ - bool has_immediate; /* Présence d'une conversion */ size_t i; /* Boucle de parcours */ syntax_item *item; /* Lien vers un opérande */ + conv_func *func; /* Fonction de conversion */ result = true; - has_operand = false; - has_immediate = false; - - for (i = 0; i < syntax->items_count && result; i++) + for (i = 1; i < pattern->items_count && result; i++) { - item = &syntax->items[i]; - if (item->impact == SIT_KEYWORD) continue; - - has_operand |= (item->impact == SIT_EXT_OPERAND); + item = &pattern->items[i]; - if (has_operand) - has_immediate = (item->flags & SIF_DECIMAL); + func = find_named_conv_in_list(list, item->name); + assert(func != NULL); - } + result = declare_conv_func(func, fd, bits, list, tab); - if (has_operand) - dprintf(fd, "\t\tGArchOperand *op;\n"); + if (result && item->flags & SIF_DECIMAL && !*imm_decl) + { + dprintf(fd, "\t%sGImmOperand *imm;\n", tab); + *imm_decl = true; + } - if (has_immediate) - dprintf(fd, "\t\tGImmOperand *imm;\n"); + } return result; @@ -264,7 +253,7 @@ bool declare_syntax_items(const asm_syntax *syntax, int fd, const coding_bits *b /****************************************************************************** * * -* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * +* Paramètres : pattern = gestionnaire d'un ensemble d'éléments de syntaxe. * * * * Description : Fournit si elle existe un nom nouveau pour une instruction. * * * @@ -274,17 +263,13 @@ bool declare_syntax_items(const asm_syntax *syntax, int fd, const coding_bits *b * * ******************************************************************************/ -const char *get_new_keyword_from_syntax_items(const asm_syntax *syntax) +const char *get_keyword_from_asm_pattern(const asm_pattern *pattern) { const char *result; /* Nom éventuel à renvoyer */ - result = NULL; + assert(pattern->items_count > 0); - if (syntax->items_count > 0 - && syntax->items[0].impact == SIT_KEYWORD) - { - result = syntax->items[0].name; - } + result = pattern->items[0].name; return result; @@ -293,13 +278,13 @@ const char *get_new_keyword_from_syntax_items(const asm_syntax *syntax) /****************************************************************************** * * -* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * -* fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération globale. * -* bits = gestionnaire des bits d'encodage. * -* list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * -* exit = exprime le besoin d'une voie de sortie. [OUT] * +* Paramètres : pattern = gestionnaire d'un ensemble d'éléments de syntaxe. * +* fd = descripteur d'un flux ouvert en écriture. * +* arch = architecture visée par l'opération globale. * +* bits = gestionnaire des bits d'encodage. * +* list = liste de l'ensemble des fonctions de conversion. * +* tab = décalage éventuel selon l'inclusion. * +* exit = exprime le besoin d'une voie de sortie. [OUT] * * * * Description : Définit les variables C associées aux opérandes de syntaxe. * * * @@ -309,109 +294,105 @@ const char *get_new_keyword_from_syntax_items(const asm_syntax *syntax) * * ******************************************************************************/ -bool define_syntax_items(const asm_syntax *syntax, int fd, const char *arch, const coding_bits *bits, const conv_list *list, const pre_processor *pp, bool *exit) +bool define_asm_pattern(const asm_pattern *pattern, int fd, const char *arch, const coding_bits *bits, const conv_list *list, const char *tab, bool *exit) { bool result; /* Bilan à retourner */ size_t i; /* Boucle de parcours */ syntax_item *item; /* Lien vers un opérande */ conv_func *func; /* Fonction de conversion */ - bool internal; /* Usage interne ou non ? */ + bool optional; /* Opérande optionnelle ? */ result = true; - for (i = 0; i < syntax->items_count && result; i++) + for (i = 1; i < pattern->items_count; i++) { - item = &syntax->items[i]; + item = &pattern->items[i]; - switch (item->impact) - { - case SIT_KEYWORD: + func = find_named_conv_in_list(list, item->name); + assert(func != NULL); - /** - * TODO : à faire évoluer vers extend... - */ - //_exit(123); + optional = item->flags & SIF_OPTIONAL; - // rev_A88146 - /* - if (i > 0) - dprintf(fd, "\t\tg_arch_instruction_append_suffix(instr, \"%s\");\n", item->name); - else - continue; - */ + result = define_conv_func(func, fd, bits, list, tab, optional, exit); + if (!result) break; - break; + if (optional) + { + dprintf(fd, "\t%sif (", tab); - case SIT_INT_OPERAND: // A supprimer - case SIT_EXT_OPERAND: + write_conv_func(func, fd, false); - internal = (item->impact == SIT_INT_OPERAND); + dprintf(fd, " != NULL)"); - func = find_named_conv_in_list(list, item->name); - if (func == NULL) - { - fprintf(stderr, "Error: expected conversion for '%s'.\n", item->name); - result = false; - } + dprintf(fd, "\n"); - /* Appel proprement dit */ + if (item->flags & SIF_DECIMAL) + { + dprintf(fd, "\t%s{\n", tab); - if (is_conv_func_already_defined(func)) - { - dprintf(fd, "\t\top = val_%s;\n", item->name); + dprintf(fd, "\t%s\timm = G_IMM_OPERAND(", tab); - dprintf(fd, "\n"); + write_conv_func(func, fd, false); - if (item->flags & SIF_DECIMAL) - { - dprintf(fd, "\t\timm = G_IMM_OPERAND(op)\n"); - dprintf(fd, "\t\tg_imm_operand_set_default_display(&imm, IOD_DEC, NULL);\n"); - dprintf(fd, "\t\timm = G_IMM_OPERAND(op)\n"); - } + dprintf(fd, ");\n"); - dprintf(fd, "\t\tg_arch_instruction_attach_extra_operand(instr, op);\n"); + dprintf(fd, "\t%s\tg_imm_operand_set_default_display(imm, IOD_DEC);\n", tab); - } + dprintf(fd, "\n"); - else - { - result &= define_conv_func(func, true, internal, fd, arch, bits, list, pp, exit); - if (!result) break; + dprintf(fd, "\t%s\tg_arch_instruction_attach_extra_operand(result, ", tab); - /* Raccordement : propriété ou opérande ? */ + write_conv_func(func, fd, false); - if (internal) - { - dprintf(fd, "\t\t\tgoto bad_exit;\n"); - *exit = true; - } + dprintf(fd, ");\n"); - else - { - dprintf(fd, "\t\tif (op == NULL) goto bad_exit;\n"); - *exit = true; + dprintf(fd, "\n"); - dprintf(fd, "\n"); + dprintf(fd, "\t%s}\n", tab); - if (item->flags & SIF_DECIMAL) - { - dprintf(fd, "\t\timm = G_IMM_OPERAND(op)\n"); - dprintf(fd, "\t\tg_imm_operand_set_default_display(&imm, IOD_DEC, NULL);\n"); - dprintf(fd, "\t\timm = G_IMM_OPERAND(op)\n"); - } + dprintf(fd, "\n"); - dprintf(fd, "\t\tg_arch_instruction_attach_extra_operand(instr, op);\n"); + } - } + else + { + dprintf(fd, "\t%s\tg_arch_instruction_attach_extra_operand(result, ", tab); - } + write_conv_func(func, fd, false); - *exit = true; - break; + dprintf(fd, ");\n"); + + dprintf(fd, "\n"); + + } } - dprintf(fd, "\n"); + else + { + if (item->flags & SIF_DECIMAL) + { + dprintf(fd, "\t%simm = G_IMM_OPERAND(", tab); + + write_conv_func(func, fd, false); + + dprintf(fd, ");\n"); + + dprintf(fd, "\t%sg_imm_operand_set_default_display(imm, IOD_DEC);\n", tab); + + dprintf(fd, "\n"); + + } + + dprintf(fd, "\t%sg_arch_instruction_attach_extra_operand(result, ", tab); + + write_conv_func(func, fd, false); + + dprintf(fd, ");\n"); + + dprintf(fd, "\n"); + + } } diff --git a/tools/d2c/syntax/manager.h b/tools/d2c/pattern/manager.h index 9cdaa8b..592b169 100644 --- a/tools/d2c/syntax/manager.h +++ b/tools/d2c/pattern/manager.h @@ -28,45 +28,35 @@ #include <stdbool.h> -#include "../pproc.h" #include "../bits/manager.h" #include "../conv/manager.h" -/* Type d'éléments de syntaxe */ -typedef enum _SyntaxItemType -{ - SIT_KEYWORD, /* Elément de l'instruction */ - SIT_INT_OPERAND, /* Propriété d'architecture */ - SIT_EXT_OPERAND /* Opérande généraliste */ - -} SyntaxItemType; - /* Syntaxe d'une ligne d'assembleur */ -typedef struct _asm_syntax asm_syntax; +typedef struct _asm_pattern asm_pattern; /* Crée un nouvel indicateur pour l'écriture d'une instruction. */ -asm_syntax *create_asm_syntax(void); +asm_pattern *create_asm_pattern(void); /* Supprime de la mémoire un indicateur d'écriture ASM. */ -void delete_asm_syntax(asm_syntax *); +void delete_asm_pattern(asm_pattern *); /* Enregistre la présence d'un nouvel opérande dans la syntaxe. */ -void register_syntax_item(asm_syntax *, char *, SyntaxItemType); +void register_asm_pattern_item(asm_pattern *, char *); /* Marque les champs de bits effectivement utilisés. */ -bool mark_syntax_items(const asm_syntax *, const coding_bits *, const conv_list *); +bool mark_asm_pattern_items(const asm_pattern *, const coding_bits *, const conv_list *); /* Déclare les variables C associées aux opérandes de syntaxe. */ -bool declare_syntax_items(const asm_syntax *, int, const coding_bits *, const conv_list *, unsigned int); +bool declare_asm_pattern(const asm_pattern *, int, const coding_bits *, const conv_list *, const char *, bool *); /* Fournit si elle existe un nom nouveau pour une instruction. */ -const char *get_new_keyword_from_syntax_items(const asm_syntax *); +const char *get_keyword_from_asm_pattern(const asm_pattern *); /* Définit les variables C associées aux opérandes de syntaxe. */ -bool define_syntax_items(const asm_syntax *, int, const char *, const coding_bits *, const conv_list *, const pre_processor *, bool *); +bool define_asm_pattern(const asm_pattern *, int, const char *, const coding_bits *, const conv_list *, const char *, bool *); diff --git a/tools/d2c/pattern/tokens.l b/tools/d2c/pattern/tokens.l new file mode 100644 index 0000000..bef1e44 --- /dev/null +++ b/tools/d2c/pattern/tokens.l @@ -0,0 +1,34 @@ + +%top { + +#include "grammar.h" + +} + + +%option noyywrap +%option nounput +%option noinput +%option yylineno +%option stack +%option noyy_top_state +%option noyy_push_state +%option noyy_pop_state + + +%% + + +[ \t] { } + +[^ ]+ { yylvalp->string = strdup(yytext); return OPERAND; } + +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c pattern block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + + +%% diff --git a/tools/d2c/qckcall.c b/tools/d2c/qckcall.c index 828a379..f8f8641 100644 --- a/tools/d2c/qckcall.c +++ b/tools/d2c/qckcall.c @@ -96,13 +96,11 @@ char *build_cast_if_needed(const char *callee) /****************************************************************************** * * -* Paramètres : top = indique si l'écriture se fait au plus haut niveau. * -* callee = fonction appelée à nommer. * +* Paramètres : callee = fonction appelée à nommer. * * args = précise si la conversion est la dernière. * * fd = descripteur d'un flux ouvert en écriture. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * * * * Description : Réalise un appel à une fonction liée à une instruction. * * * @@ -112,7 +110,7 @@ char *build_cast_if_needed(const char *callee) * * ******************************************************************************/ -bool call_instr_func(bool top, const char *callee, const arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list, const pre_processor *pp) +bool call_instr_func(const char *callee, const arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list) { bool result; /* Bilan à remonter */ char *cast; /* Macro de transtypage */ @@ -120,21 +118,12 @@ bool call_instr_func(bool top, const char *callee, const arg_list_t *args, int f cast = build_cast_if_needed(callee); if (cast == NULL) - { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\t%s(%s, ", callee, top ? "result" : "instr"); + dprintf(fd, "\t%s(result, ", callee); - } else { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\t%s(%s(%s), ", callee, cast, top ? "result" : "instr"); + dprintf(fd, "\t%s(%s(result), ", callee, cast); free(cast); - } result = define_arg_list(args, fd, bits, list); @@ -148,13 +137,11 @@ bool call_instr_func(bool top, const char *callee, const arg_list_t *args, int f /****************************************************************************** * * -* Paramètres : top = indique si l'écriture se fait au plus haut niveau. * -* callee = fonction appelée à nommer. * +* Paramètres : callee = fonction appelée à nommer. * * args = précise si la conversion est la dernière. * * fd = descripteur d'un flux ouvert en écriture. * * bits = gestionnaire des bits d'encodage. * * list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * * * * Description : Réalise un appel à une fonction liée à une instruction. * * * @@ -164,7 +151,7 @@ bool call_instr_func(bool top, const char *callee, const arg_list_t *args, int f * * ******************************************************************************/ -bool checked_call_instr_func(bool top, const char *callee, const arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list, const pre_processor *pp) +bool checked_call_instr_func(const char *callee, const arg_list_t *args, int fd, const coding_bits *bits, const conv_list *list) { bool result; /* Bilan à remonter */ char *cast; /* Macro de transtypage */ @@ -172,21 +159,12 @@ bool checked_call_instr_func(bool top, const char *callee, const arg_list_t *arg cast = build_cast_if_needed(callee); if (cast == NULL) - { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\tif (!%s(%s, ", callee, top ? "result" : "instr"); + dprintf(fd, "\tif (!%s(result, ", callee); - } else { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\tif (!%s(%s(%s), ", callee, cast, top ? "result" : "instr"); + dprintf(fd, "\tif (!%s(%s(result), ", callee, cast); free(cast); - } result = define_arg_list(args, fd, bits, list); diff --git a/tools/d2c/qckcall.h b/tools/d2c/qckcall.h index 28e607c..dea4792 100644 --- a/tools/d2c/qckcall.h +++ b/tools/d2c/qckcall.h @@ -28,7 +28,6 @@ #include <stdbool.h> -#include "pproc.h" #include "args/manager.h" #include "bits/manager.h" #include "conv/manager.h" @@ -39,10 +38,10 @@ char *build_cast_if_needed(const char *); /* Réalise un appel à une fonction liée à une instruction. */ -bool call_instr_func(bool, const char *, const arg_list_t *, int, const coding_bits *, const conv_list *, const pre_processor *); +bool call_instr_func(const char *, const arg_list_t *, int, const coding_bits *, const conv_list *); /* Réalise un appel à une fonction liée à une instruction. */ -bool checked_call_instr_func(bool, const char *, const arg_list_t *, int, const coding_bits *, const conv_list *, const pre_processor *); +bool checked_call_instr_func(const char *, const arg_list_t *, int, const coding_bits *, const conv_list *); diff --git a/tools/d2c/rules/Makefile.am b/tools/d2c/rules/Makefile.am index 81bf7b8..93d3040 100644 --- a/tools/d2c/rules/Makefile.am +++ b/tools/d2c/rules/Makefile.am @@ -26,6 +26,9 @@ libd2crules_la_SOURCES = \ tokens.l \ grammar.y +# _GNU_SOURCE : asprintf +libd2crules_la_CFLAGS = -D_GNU_SOURCE + # Automake fait les choses à moitié CLEANFILES = grammar.h grammar.c grammar.output tokens.c tokens.h diff --git a/tools/d2c/rules/manager.c b/tools/d2c/rules/manager.c index 74be5fc..20f1a2b 100644 --- a/tools/d2c/rules/manager.c +++ b/tools/d2c/rules/manager.c @@ -290,9 +290,6 @@ static bool mark_cond_expr(const cond_expr *expr, const coding_bits *bits, const } - - printf("=== USE '%s' : %d\n", name, status); - if (!status) fprintf(stderr, "Error: nothing defined for the requested variable '%s'.\n", name); @@ -603,16 +600,14 @@ bool mark_decoding_rules(const decoding_rules *rules, const coding_bits *bits, c /****************************************************************************** * * -* Paramètres : rules = ensemble de règles à consulter. * -* top = indique si l'écriture se fait au plus haut niveau. * -* filter = filtre sur les règles à effectivement imprimer. * -* fd = descripteur d'un flux ouvert en écriture. * -* arch = architecture visée par l'opération. * -* subarch = sous-catégorie de cette même architecture. * -* bits = gestionnaire des bits d'encodage. * -* list = liste de l'ensemble des fonctions de conversion. * -* pp = pré-processeur pour les échanges de chaînes. * -* exit = exprime le besoin d'une voie de sortie. [OUT] * +* Paramètres : rules = ensemble de règles à consulter. * +* filter = filtre sur les règles à effectivement imprimer. * +* fd = descripteur d'un flux ouvert en écriture. * +* arch = architecture visée par l'opération. * +* bits = gestionnaire des bits d'encodage. * +* list = liste de l'ensemble des fonctions de conversion. * +* tab = décalage éventuel selon l'inclusion. * +* exit = exprime le besoin d'une voie de sortie. [OUT] * * * * Description : Traduit en code les éventuelles règles présentes. * * * @@ -622,7 +617,7 @@ bool mark_decoding_rules(const decoding_rules *rules, const coding_bits *bits, c * * ******************************************************************************/ -bool write_decoding_rules(decoding_rules *rules, bool top, CondActionType filter, int fd, const char *arch, const char *subarch, const coding_bits *bits, const conv_list *list, const pre_processor *pp, bool *exit) +bool write_decoding_rules(decoding_rules *rules, CondActionType filter, int fd, const char *arch, const coding_bits *bits, const conv_list *list, const char *tab, bool *exit) { bool result; /* Bilan à remonter */ size_t i; /* Boucle de parcours */ @@ -642,6 +637,7 @@ bool write_decoding_rules(decoding_rules *rules, bool top, CondActionType filter switch (rule->action.type) { case CAT_CALL: + case CAT_CHECKED_CALL: multi_lines = false; break; @@ -653,10 +649,7 @@ bool write_decoding_rules(decoding_rules *rules, bool top, CondActionType filter if (rule->expr != NULL) { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\tif "); + dprintf(fd, "\t%sif ", tab); result = write_cond_expr(rule->expr, fd, bits, list); if (!result) break; @@ -664,13 +657,7 @@ bool write_decoding_rules(decoding_rules *rules, bool top, CondActionType filter dprintf(fd, "\n"); if (multi_lines) - { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\t{\n"); - - } + dprintf(fd, "\t%s{\n", tab); } @@ -695,37 +682,42 @@ bool write_decoding_rules(decoding_rules *rules, bool top, CondActionType filter case CAT_CALL: + /* callable = find_macro(pp, rule->action.callee); if (callable == NULL) + */ callable = rule->action.callee; if (rule->expr != NULL) - dprintf(fd, "\t"); + dprintf(fd, "\t") +; + dprintf(fd, "%s", tab); - result = call_instr_func(top, callable, rule->action.args, fd, bits, list, pp); + result = call_instr_func(callable, rule->action.args, fd, bits, list); break; case CAT_CHECKED_CALL: + /* callable = find_macro(pp, rule->action.callee); if (callable == NULL) + */ callable = rule->action.callee; if (rule->expr != NULL) dprintf(fd, "\t"); - result = checked_call_instr_func(top, callable, rule->action.args, fd, bits, list, pp); + dprintf(fd, "%s", tab); - if (rule->expr != NULL) - dprintf(fd, "\t"); + result = checked_call_instr_func(callable, rule->action.args, fd, bits, list); - if (!top) + if (rule->expr != NULL) dprintf(fd, "\t"); - dprintf(fd, "\t\tgoto quick_exit;\n"); + dprintf(fd, "\t\t%sgoto bad_exit;\n", tab); *exit = true; break; @@ -733,13 +725,7 @@ bool write_decoding_rules(decoding_rules *rules, bool top, CondActionType filter } if (rule->expr != NULL && multi_lines) - { - if (!top) - dprintf(fd, "\t"); - - dprintf(fd, "\t}\n"); - - } + dprintf(fd, "\t%s}\n", tab); dprintf(fd, "\n"); diff --git a/tools/d2c/rules/manager.h b/tools/d2c/rules/manager.h index 7f8ef11..88d1d46 100644 --- a/tools/d2c/rules/manager.h +++ b/tools/d2c/rules/manager.h @@ -25,7 +25,6 @@ #define _TOOLS_D2C_RULES_MANAGER_H -#include "../pproc.h" #include "../args/manager.h" #include "../bits/manager.h" #include "../conv/manager.h" @@ -119,7 +118,7 @@ void register_conditional_rule(decoding_rules *, cond_expr *, const rule_action bool mark_decoding_rules(const decoding_rules *, const coding_bits *, const conv_list *); /* Traduit en code les éventuelles règles présentes. */ -bool write_decoding_rules(decoding_rules *, bool, CondActionType, int, const char *, const char *, const coding_bits *, const conv_list *, const pre_processor *, bool *); +bool write_decoding_rules(decoding_rules *, CondActionType, int, const char *, const coding_bits *, const conv_list *, const char *, bool *); diff --git a/tools/d2c/rules/tokens.l b/tools/d2c/rules/tokens.l index 36d6c4a..6b14a85 100644 --- a/tools/d2c/rules/tokens.l +++ b/tools/d2c/rules/tokens.l @@ -23,7 +23,7 @@ %% -\/\/[^\n]+ { printf("SKIP '%s'\n", yytext); } +\/\/[^\n]+ { } "if" { yy_push_state(cond); return IF; } <cond>[ ]+ { } @@ -41,17 +41,24 @@ <cond>";" { yy_pop_state(); return THEN; } -[ ] { } +[ \t\n] { } "see " { yy_push_state(raw_line); return SEE; } "unpredictable" { return UNPREDICTABLE; } "call" { yy_push_state(raw_line); return CALL; } -"chk_call" { yy_push_state(raw_line); return CHK_CALL; } +"check" { yy_push_state(raw_line); return CHK_CALL; } <raw_line>[^\n]+ { yylvalp->cstring = yytext; return RAW_LINE; } <raw_line>"\n" { yy_pop_state(); } +. { + char *msg; + asprintf(&msg, "Unhandled token in d2c rules block: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + %% diff --git a/tools/d2c/syntax.c b/tools/d2c/syntax.c new file mode 100644 index 0000000..c0842a7 --- /dev/null +++ b/tools/d2c/syntax.c @@ -0,0 +1,313 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * syntax.c - représentation complète d'une syntaxe + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#include "syntax.h" + + +#include <assert.h> +#include <malloc.h> + + + +/* Mémorisation d'une définition de syntaxe */ +struct _encoding_syntax +{ + disass_assert *assertions; /* Conditions de désassemblage */ + conv_list *conversions; /* Conversions des données */ + asm_pattern *pattern; /* Calligraphe d'assemblage */ + decoding_rules *rules; /* Règles supplémentaires */ + +}; + + + +/****************************************************************************** +* * +* Paramètres : - * +* * +* Description : Crée un nouveau suivi d'une définition de syntaxe. * +* * +* Retour : Nouvelle structure prête à emploi. * +* * +* Remarques : - * +* * +******************************************************************************/ + +encoding_syntax *create_encoding_syntax(void) +{ + encoding_syntax *result; /* Définition vierge à renvoyer*/ + + result = (encoding_syntax *)calloc(1, sizeof(encoding_syntax)); + + result->assertions = create_disass_assert(); + result->conversions = create_conv_list(); + result->pattern = create_asm_pattern(); + result->rules = create_decoding_rules(); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = définition de syntaxe à libérer de la mémoire. * +* * +* Description : Supprime de la mémoire le suivi d'une définition de syntaxe. * +* * +* Retour : - * +* * +* Remarques : - * +* * +******************************************************************************/ + +void delete_encoding_syntax(encoding_syntax *syntax) +{ + delete_disass_assert(syntax->assertions); + delete_conv_list(syntax->conversions); + delete_asm_pattern(syntax->pattern); + delete_decoding_rules(syntax->rules); + + free(syntax); + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = définition de syntaxe à consulter. * +* * +* Description : Fournit la liste de conditions préalables. * +* * +* Retour : Structure assurant la gestion de conditions de désassemblage.* +* * +* Remarques : - * +* * +******************************************************************************/ + +disass_assert *get_assertions_for_encoding_syntax(const encoding_syntax *syntax) +{ + return syntax->assertions; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = définition de syntaxe à consulter. * +* * +* Description : Fournit la liste des fonctions de conversion. * +* * +* Retour : Structure assurant la gestion des fonctions de conversion. * +* * +* Remarques : - * +* * +******************************************************************************/ + +conv_list *get_conversions_in_encoding_syntax(const encoding_syntax *syntax) +{ + return syntax->conversions; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = définition de syntaxe à consulter. * +* * +* Description : Fournit l'indicateur des écritures correctes d'assembleur. * +* * +* Retour : Structure assurant la gestion des éléments de syntaxe. * +* * +* Remarques : - * +* * +******************************************************************************/ + +asm_pattern *get_asm_pattern_in_encoding_syntax(const encoding_syntax *syntax) +{ + return syntax->pattern; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = définition de syntaxe à consulter. * +* * +* Description : Fournit un ensemble de règles supplémentaires éventuel. * +* * +* Retour : Structure assurant la gestion de ces règles. * +* * +* Remarques : - * +* * +******************************************************************************/ + +decoding_rules *get_rules_in_encoding_syntax(const encoding_syntax *syntax) +{ + return syntax->rules; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * +* bits = gestionnaire des bits d'encodage. * +* * +* Description : Marque les éléments de syntaxe effectivement utilisés. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool mark_syntax_items(const encoding_syntax *syntax, const coding_bits *bits) +{ + bool result; /* Bilan à retourner */ + + result = mark_disass_assert(syntax->assertions, bits); + + if (result) + result = mark_asm_pattern_items(syntax->pattern, bits, syntax->conversions); + + if (result) + result = mark_decoding_rules(syntax->rules, bits, syntax->conversions); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * +* fd = descripteur d'un flux ouvert en écriture. * +* bits = gestionnaire des bits d'encodage. * +* * +* Description : Déclare les éléments d'une syntaxe isolée. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool declare_encoding_syntax(const encoding_syntax *syntax, int fd, const coding_bits *bits) +{ + bool result; /* Bilan à retourner */ + bool imm_decl; /* Suivi des déclaration */ + + imm_decl = false; + + result = declare_asm_pattern(syntax->pattern, fd, bits, syntax->conversions, "", &imm_decl); + + return result; + +} + + +/****************************************************************************** +* * +* Paramètres : syntax = gestionnaire d'un ensemble d'éléments de syntaxe. * +* fd = descripteur d'un flux ouvert en écriture. * +* arch = architecture visée par l'opération globale. * +* bits = gestionnaire des bits d'encodage. * +* alone = peut-on se placer en zone principale ? * +* pp = pré-processeur pour les échanges de chaînes. * +* exit = exprime le besoin d'une voie de sortie. [OUT] * +* * +* Description : Amorce la construction des éléments d'une syntaxe. * +* * +* Retour : Bilan de l'opération. * +* * +* Remarques : - * +* * +******************************************************************************/ + +bool write_encoding_syntax(const encoding_syntax *syntax, int fd, const char *arch, const coding_bits *bits, bool alone, bool *exit) +{ + bool result; /* Bilan à retourner */ + bool conditional; /* Définition sous condition ? */ + const char *tab; /* Décallage supplémentaire ? */ + bool imm_decl; /* Suivi des déclaration */ + + conditional = !is_disass_assert_empty(syntax->assertions); + + assert((conditional && !alone) || (!conditional && alone)); + + if (conditional) + { + dprintf(fd, "\tif ("); + + result = define_disass_assert(syntax->assertions, fd, bits); + if (!result) goto wes_exit; + + dprintf(fd, ")\n"); + dprintf(fd, "\t{\n"); + + tab = "\t"; + + } + + else + tab = (alone ? "" : "\t"); + + if (!alone) + { + imm_decl = false; + + result = declare_asm_pattern(syntax->pattern, fd, bits, syntax->conversions, "\t", &imm_decl); + if (!result) goto wes_exit; + + dprintf(fd, "\n"); + + } + + dprintf(fd, "\t%sresult = g_%s_instruction_new(\"%s\");\n", + tab, arch, get_keyword_from_asm_pattern(syntax->pattern)); + + dprintf(fd, "\n"); + + result = define_asm_pattern(syntax->pattern, fd, arch, bits, syntax->conversions, tab, exit); + if (!result) goto wes_exit; + + result = write_decoding_rules(syntax->rules, CAT_CHECKED_CALL, fd, arch, bits, syntax->conversions, tab, exit); + if (!result) goto wes_exit; + + result = write_decoding_rules(syntax->rules, CAT_CALL, fd, arch, bits, syntax->conversions, tab, exit); + if (!result) goto wes_exit; + + if (conditional) + { + dprintf(fd, "\t}\n"); + + dprintf(fd, "\n"); + + } + + wes_exit: + + return result; + +} diff --git a/tools/d2c/syntax.h b/tools/d2c/syntax.h new file mode 100644 index 0000000..5aa4716 --- /dev/null +++ b/tools/d2c/syntax.h @@ -0,0 +1,70 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * syntax.h - prototypes pour la représentation complète d'une syntaxe + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +#ifndef _TOOLS_D2C_SYNTAX_H +#define _TOOLS_D2C_SYNTAX_H + + + +#include "assert/manager.h" +#include "bits/manager.h" +#include "conv/manager.h" +#include "pattern/manager.h" +#include "rules/manager.h" + + + +/* Mémorisation d'une définition de syntaxe */ +typedef struct _encoding_syntax encoding_syntax; + + +/* Crée un nouveau suivi d'une définition de syntaxe. */ +encoding_syntax *create_encoding_syntax(void); + +/* Supprime de la mémoire le suivi d'une définition de syntaxe. */ +void delete_encoding_syntax(encoding_syntax *); + +/* Fournit la liste de conditions préalables. */ +disass_assert *get_assertions_for_encoding_syntax(const encoding_syntax *); + +/* Fournit la liste des fonctions de conversion. */ +conv_list *get_conversions_in_encoding_syntax(const encoding_syntax *); + +/* Fournit l'indicateur des écritures correctes d'assembleur. */ +asm_pattern *get_asm_pattern_in_encoding_syntax(const encoding_syntax *); + +/* Fournit un ensemble de règles supplémentaires éventuel. */ +decoding_rules *get_rules_in_encoding_syntax(const encoding_syntax *); + +/* Marque les éléments de syntaxe effectivement utilisés. */ +bool mark_syntax_items(const encoding_syntax *, const coding_bits *); + +/* Déclare les éléments d'une syntaxe isolée. */ +bool declare_encoding_syntax(const encoding_syntax *, int, const coding_bits *); + +/* Amorce la construction des éléments d'une syntaxe. */ +bool write_encoding_syntax(const encoding_syntax *, int, const char *, const coding_bits *, bool, bool *); + + + +#endif /* _TOOLS_D2C_SYNTAX_H */ diff --git a/tools/d2c/syntax/tokens.l b/tools/d2c/syntax/tokens.l deleted file mode 100644 index ab1b0f3..0000000 --- a/tools/d2c/syntax/tokens.l +++ /dev/null @@ -1,39 +0,0 @@ - -%top { - -#include "grammar.h" - -} - - -%option noyywrap -%option nounput -%option noinput -%option yylineno -%option stack -%option noyy_top_state - -%x named -%x internal -%x visible - - -%% - - -" " { } - -"\"" { yy_push_state(named); } -<named>[^ \"]+ { yylvalp->string = strdup(yytext); return OPERAND_NAME; } -<named>"\"" { yy_pop_state(); } - -"{" { yy_push_state(internal); } -<internal>[^ }]+ { yylvalp->string = strdup(yytext); return OPERAND_INTERNAL; } -<internal>"}" { yy_pop_state(); } - -"<" { yy_push_state (visible); } -<visible>[^ >]+ { yylvalp->string = strdup(yytext); return OPERAND_VISIBLE; } -<visible>">" { yy_pop_state(); } - - -%% diff --git a/tools/d2c/tokens.l b/tools/d2c/tokens.l index 220e5d6..60dd257 100644 --- a/tools/d2c/tokens.l +++ b/tools/d2c/tokens.l @@ -14,7 +14,6 @@ %option noyywrap -%option nounput %option yylineno %option stack %option noyy_top_state @@ -23,11 +22,12 @@ %x comments %x ins_name try_details ins_details -%x encoding encoding_type encoding_content +%x encoding encoding_type encoding_content syntax_content %x encoding_bits encoding_bits_size -%x raw_line +%x top_brace +%x raw_line raw_block %% @@ -52,45 +52,75 @@ <ins_details>[^\n]* { yylvalp->cstring = yytext; return INS_DETAILS; } <ins_details>[\n] { BEGIN(INITIAL); } +"@id" { yy_push_state(raw_line); return ID; } -"@desc" { yy_push_state(raw_line); return DESC; } +"@desc" { yy_push_state(raw_block); return DESC; } -"@encoding" { BEGIN(encoding); return ENCODING; } +"@encoding" { yy_push_state(encoding); return ENCODING; } <encoding>[ ] { } -<encoding>"(" { BEGIN(encoding_type); } +<encoding>"(" { yy_push_state(encoding_type); } <encoding_type>[A-Za-z] { yylvalp->string = strdup(yytext); return TYPE; } <encoding_type>[0-9]+ { yylvalp->integer = atoi(yytext); return NUMBER; } -<encoding_type>")" { BEGIN(encoding); } +<encoding_type>")" { yy_pop_state(); } + +<encoding>"{" { yy_push_state(encoding_content); } -<encoding>"{" { BEGIN(encoding_content); } <encoding_content>[ \t\n]+ { } -<encoding_content>"}" { BEGIN(INITIAL); } +<encoding_content>"}" { yy_pop_state(); yy_pop_state(); } <encoding_content>"@format" { yy_push_state(raw_line); return FORMAT; } +<encoding_content>"@unused" { yy_push_state(raw_line); return UNUSED; } <encoding_content>"@half" { yy_push_state(raw_line); return HALF; } <encoding_content>"@word" { yy_push_state(raw_line); return WORD; } -<encoding_content>"@syntax" { yy_push_state(raw_line); return SYNTAX; } +<encoding_content>"@syntax" { yy_push_state(syntax_content); yy_push_state(top_brace); return SYNTAX; } + +<encoding_content>"@hooks" { yy_push_state(raw_block); return HOOKS; } + + +<syntax_content>[ \t\n]+ { } + +<syntax_content>"@assert" { yy_push_state(raw_block); return ASSERT; } + +<syntax_content>"@conv" { yy_push_state(raw_block); return CONV; } + +<syntax_content>"@asm" { yy_push_state(raw_line); return ASM; } -<encoding_content>"@conv" { return CONV; } +<syntax_content>"@rules" { yy_push_state(raw_block); return RULES; } -<encoding_content>"@hooks" { return HOOKS; } +<syntax_content>"}" { yy_pop_state(); } -<encoding_content>"@rules" { return RULES; } +<top_brace>[ \t\n]+ { } +<top_brace>"{" { yy_pop_state(); } <raw_line>[^\n]+ { yylvalp->cstring = yytext; return RAW_LINE; } <raw_line>"\n" { yy_pop_state(); } +<raw_block>[ \t\n]+ { } +<raw_block>"{" { + read_block(temp); + yylvalp->cstring = temp; return RAW_BLOCK; + } +<raw_block>"}" { yy_pop_state(); } + + <encoding_content>"{" { read_block(temp); yylvalp->cstring = temp; return RAW_BLOCK; } +<*>. { + char *msg; + asprintf(&msg, "Unhandled token in d2c definition: '%s'", yytext); + YY_FATAL_ERROR(msg); + free(msg); + } + %% |