diff options
| -rw-r--r-- | ChangeLog | 22 | ||||
| -rw-r--r-- | src/arch/arm/v7/opcodes/opcodes_tmp_arm.h | 12 | ||||
| -rw-r--r-- | src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h | 3 | ||||
| -rw-r--r-- | src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h | 11 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/Makefile.am | 13 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strbt_A88209.d | 93 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strd_A88210.d | 75 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strd_A88211.d | 54 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strex_A88212.d | 68 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strexb_A88213.d | 67 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strexd_A88214.d | 69 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strexh_A88215.d | 67 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strh_A88216.d | 81 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strh_A88217.d | 53 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strh_A88218.d | 88 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strht_A88219.d | 92 | ||||
| -rw-r--r-- | src/arch/arm/v7/opdefs/strt_A88220.d | 93 |
17 files changed, 935 insertions, 26 deletions
@@ -1,3 +1,25 @@ +16-05-27 Cyrille Bagard <nocbos@gmail.com> + + * src/arch/arm/v7/opcodes/opcodes_tmp_arm.h: + * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h: + * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h: + * src/arch/arm/v7/opdefs/Makefile.am: + Handle more ARM instructions from the storing family. + + * src/arch/arm/v7/opdefs/strbt_A88209.d: + * src/arch/arm/v7/opdefs/strd_A88210.d: + * src/arch/arm/v7/opdefs/strd_A88211.d: + * src/arch/arm/v7/opdefs/strex_A88212.d: + * src/arch/arm/v7/opdefs/strexb_A88213.d: + * src/arch/arm/v7/opdefs/strexd_A88214.d: + * src/arch/arm/v7/opdefs/strexh_A88215.d: + * src/arch/arm/v7/opdefs/strh_A88216.d: + * src/arch/arm/v7/opdefs/strh_A88217.d: + * src/arch/arm/v7/opdefs/strh_A88218.d: + * src/arch/arm/v7/opdefs/strht_A88219.d: + * src/arch/arm/v7/opdefs/strt_A88220.d: + New entries: handle more ARM instructions from the storing family. + 16-05-25 Cyrille Bagard <nocbos@gmail.com> * src/arch/arm/cond.h: diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h index dcfd635..4106cbd 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h @@ -45,18 +45,6 @@ #define armv7_read_arm_instr_stmib_stmfa(r) NULL #define armv7_read_arm_instr_stm_stmia_stmea(r) NULL #define armv7_read_arm_instr_stm_user_registers(r) NULL -#define armv7_read_arm_instr_strbt(r) NULL -#define armv7_read_arm_instr_strd_immediate(r) NULL -#define armv7_read_arm_instr_strd_register(r) NULL -#define armv7_read_arm_instr_strex(r) NULL -#define armv7_read_arm_instr_strexb(r) NULL -#define armv7_read_arm_instr_strexd(r) NULL -#define armv7_read_arm_instr_strexh(r) NULL -#define armv7_read_arm_instr_strh_immediate_arm(r) NULL -#define armv7_read_arm_instr_strh_register(r) NULL -#define armv7_read_arm_instr_strht(r) NULL -#define armv7_read_arm_instr_str_register(r) NULL -#define armv7_read_arm_instr_strt(r) NULL #define armv7_read_arm_instr_sub_register_shifted_register(r) NULL #define armv7_read_arm_instr_sxtab(r) NULL #define armv7_read_arm_instr_sxtab16(r) NULL diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h index 1a62c43..1968037 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h @@ -4,9 +4,6 @@ #define armv7_read_thumb_16_instr_it(r) NULL #define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL #define armv7_read_thumb_16_instr_stm_stmia_stmea(r) NULL -#define armv7_read_thumb_16_instr_strh_immediate_thumb(r) NULL -#define armv7_read_thumb_16_instr_strh_register(r) NULL -#define armv7_read_thumb_16_instr_str_register(r) NULL #define armv7_read_thumb_16_instr_sxtb(r) NULL #define armv7_read_thumb_16_instr_sxth(r) NULL #define armv7_read_thumb_16_instr_wfe(r) NULL diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h index c74ab49..1ed547c 100644 --- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h +++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h @@ -46,17 +46,6 @@ #define armv7_read_thumb_32_instr_stc_stc2(r) NULL #define armv7_read_thumb_32_instr_stmdb_stmfd(r) NULL #define armv7_read_thumb_32_instr_stm_stmia_stmea(r) NULL -#define armv7_read_thumb_32_instr_strbt(r) NULL -#define armv7_read_thumb_32_instr_strd_immediate(r) NULL -#define armv7_read_thumb_32_instr_strex(r) NULL -#define armv7_read_thumb_32_instr_strexb(r) NULL -#define armv7_read_thumb_32_instr_strexd(r) NULL -#define armv7_read_thumb_32_instr_strexh(r) NULL -#define armv7_read_thumb_32_instr_strh_immediate_thumb(r) NULL -#define armv7_read_thumb_32_instr_strh_register(r) NULL -#define armv7_read_thumb_32_instr_strht(r) NULL -#define armv7_read_thumb_32_instr_str_register(r) NULL -#define armv7_read_thumb_32_instr_strt(r) NULL #define armv7_read_thumb_32_instr_sub_register_thumb(r) NULL #define armv7_read_thumb_32_instr_subs_pc_lr_thumb(r) NULL #define armv7_read_thumb_32_instr_sxtab(r) NULL diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am index 578e4a5..133810b 100644 --- a/src/arch/arm/v7/opdefs/Makefile.am +++ b/src/arch/arm/v7/opdefs/Makefile.am @@ -211,9 +211,22 @@ ARMV7_DEFS = \ smull_A88189.d \ str_A88203.d \ str_A88204.d \ + str_A88205.d \ strb_A88206.d \ strb_A88207.d \ strb_A88208.d \ + strbt_A88209.d \ + strd_A88210.d \ + strd_A88211.d \ + strex_A88212.d \ + strexb_A88213.d \ + strexd_A88214.d \ + strexh_A88215.d \ + strh_A88216.d \ + strh_A88217.d \ + strh_A88218.d \ + strht_A88219.d \ + strt_A88220.d \ sub_A88221.d \ sub_A88222.d \ sub_A88223.d \ diff --git a/src/arch/arm/v7/opdefs/strbt_A88209.d b/src/arch/arm/v7/opdefs/strbt_A88209.d new file mode 100644 index 0000000..2bcb260 --- /dev/null +++ b/src/arch/arm/v7/opdefs/strbt_A88209.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRBT + +@desc Store Register Byte Unprivileged stores a byte from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRBT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 1 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strd_A88210.d b/src/arch/arm/v7/opdefs/strd_A88210.d new file mode 100644 index 0000000..437bcb3 --- /dev/null +++ b/src/arch/arm/v7/opdefs/strd_A88210.d @@ -0,0 +1,75 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRD (immediate) + +@desc Store Register Dual (immediate) calculates an address from a base register value and an immediate offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) Rt2(4) imm8(8) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 1 1 1 imm4L(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strd_A88211.d b/src/arch/arm/v7/opdefs/strd_A88211.d new file mode 100644 index 0000000..b30d4a5 --- /dev/null +++ b/src/arch/arm/v7/opdefs/strd_A88211.d @@ -0,0 +1,54 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRD (register) + +@desc Store Register Dual (register) calculates an address from a base register value and a register offset, and stores two words from two registers to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 1 1 1 Rm(4) + + @syntax <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strex_A88212.d b/src/arch/arm/v7/opdefs/strex_A88212.d new file mode 100644 index 0000000..65a7dfe --- /dev/null +++ b/src/arch/arm/v7/opdefs/strex_A88212.d @@ -0,0 +1,68 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREX + +@desc Store Register Exclusive calculates an address from a base register value and an immediate offset, and stores a word from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 0 1 0 0 Rn(4) Rt(4) Rd(4) imm8(8) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8:'00', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strexb_A88213.d b/src/arch/arm/v7/opdefs/strexb_A88213.d new file mode 100644 index 0000000..0197d6c --- /dev/null +++ b/src/arch/arm/v7/opdefs/strexb_A88213.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREXB + +@desc Store Register Exclusive Byte derives an address from a base register value, and stores a byte from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 0 Rd(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 0 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strexd_A88214.d b/src/arch/arm/v7/opdefs/strexd_A88214.d new file mode 100644 index 0000000..2867cea --- /dev/null +++ b/src/arch/arm/v7/opdefs/strexd_A88214.d @@ -0,0 +1,69 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREXD + +@desc Store Register Exclusive Doubleword derives an address from a base register value, and stores a 64-bit doubleword from two registers to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) Rt2(4) 0 1 1 1 Rd(4) + + @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = Register(Rt2) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 0 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <reg_T2> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_T2 = NextRegister(reg_T) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strexh_A88215.d b/src/arch/arm/v7/opdefs/strexh_A88215.d new file mode 100644 index 0000000..4ca0b6f --- /dev/null +++ b/src/arch/arm/v7/opdefs/strexh_A88215.d @@ -0,0 +1,67 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STREXH + +@desc Store Register Exclusive Halfword derives an address from a base register value, and stores a halfword from a register to memory if the executing processor has exclusive access to the memory addressed. For more information about support for shared memory see Synchronization and semaphores on page A3-114. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (T1) { + + @word 1 1 1 0 1 0 0 0 1 1 0 0 Rn(4) Rt(4) 1 1 1 1 0 1 0 1 Rd(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 1 1 1 0 Rn(4) Rd(4) 1 1 1 1 1 0 0 1 Rt(4) + + @syntax <reg_D> <reg_T> <mem_access> + + @conv { + + reg_D = Register(Rd) + reg_T = Register(Rt) + reg_N = Register(Rn) + mem_access = MakeMemoryAccess(reg_N, NULL, NULL, true, false, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strh_A88216.d b/src/arch/arm/v7/opdefs/strh_A88216.d new file mode 100644 index 0000000..624b483 --- /dev/null +++ b/src/arch/arm/v7/opdefs/strh_A88216.d @@ -0,0 +1,81 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRH (immediate, Thumb) + +@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 1 0 0 0 0 imm5(5) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm5:'0', 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 1 0 1 0 Rn(4) Rt(4) imm12(12) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 P(1) U(1) W(1) imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + index = (P == '1') + add = (U == '1') + wback = (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strh_A88217.d b/src/arch/arm/v7/opdefs/strh_A88217.d new file mode 100644 index 0000000..3b5f97c --- /dev/null +++ b/src/arch/arm/v7/opdefs/strh_A88217.d @@ -0,0 +1,53 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRH (immediate, ARM) + +@desc Store Register Halfword (immediate) calculates an address from a base register value and an immediate offset, and stores a halfword from a register to memory. It can use offset, post-indexed, or pre-indexed addressing. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 1 W(1) 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm4H:imm4L, 32) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strh_A88218.d b/src/arch/arm/v7/opdefs/strh_A88218.d new file mode 100644 index 0000000..1e9dc1f --- /dev/null +++ b/src/arch/arm/v7/opdefs/strh_A88218.d @@ -0,0 +1,88 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRH (register) + +@desc Store Register Halfword (register) calculates an address from a base register value and an offset register value, and stores a halfword from a register to memory. The offset register value can be shifted left by 0, 1, 2, or 3 bits. For information about memory accesses see Memory accesses on page A8-294. + +@encoding (t1) { + + @half 0 1 0 1 0 0 1 Rm(3) Rn(3) Rt(3) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, true, true, false) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 0 0 0 0 0 0 imm2(2) Rm(4) + + @syntax ".W" <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(0, imm2) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 P(1) U(1) 0 W(1) 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + index = (P == '1') + add = (U == '1') + wback = (P == '0') || (W == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, index, add, wback) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strht_A88219.d b/src/arch/arm/v7/opdefs/strht_A88219.d new file mode 100644 index 0000000..3811572 --- /dev/null +++ b/src/arch/arm/v7/opdefs/strht_A88219.d @@ -0,0 +1,92 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRHT + +@desc Store Register Halfword Unprivileged stores a halfword from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRHT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or a register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 0 1 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 0 U(1) 1 1 0 Rn(4) Rt(4) imm4H(4) 1 0 1 1 imm4L(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm4H:imm4L, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 0 0 U(1) 0 1 0 Rn(4) Rt(4) 0 0 0 0 1 0 1 1 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + mem_access = MakeMemoryAccess(reg_N, reg_M, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + diff --git a/src/arch/arm/v7/opdefs/strt_A88220.d b/src/arch/arm/v7/opdefs/strt_A88220.d new file mode 100644 index 0000000..794a0fa --- /dev/null +++ b/src/arch/arm/v7/opdefs/strt_A88220.d @@ -0,0 +1,93 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title STRT + +@desc Store Register Unprivileged stores a word from a register to memory. For information about memory accesses see Memory accesses on page A8-294. The memory access is restricted as if the processor were running in User mode. This makes no difference if the processor is actually running in User mode. STRT is UNPREDICTABLE in Hyp mode. The Thumb instruction uses an offset addressing mode, that calculates the address used for the memory access from a base register value and an immediate offset, and leaves the base register unchanged. The ARM instruction uses a post-indexed addressing mode, that uses a base register value as the address for the memory access, and calculates a new address from a base register value and an offset and writes it back to the base register. The offset can be an immediate value or an optionally-shifted register value. + +@encoding (T1) { + + @word 1 1 1 1 1 0 0 0 0 1 0 0 Rn(4) Rt(4) 1 1 1 0 imm8(8) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + imm32 = ZeroExtend(imm8, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, true, true, false) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 1 0 0 U(1) 0 1 0 Rn(4) Rt(4) imm12(12) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + add = (U == '1') + imm32 = ZeroExtend(imm12, 32) + mem_access = MakeMemoryAccess(reg_N, imm32, NULL, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 1 1 0 U(1) 0 1 0 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) + + @syntax <reg_T> <mem_access> + + @conv { + + reg_T = Register(Rt) + reg_N = Register(Rn) + reg_M = Register(Rm) + add = (U == '1') + shift = DecodeImmShift(type, imm5) + mem_access = MakeMemoryAccess(reg_N, reg_M, shift, false, add, false) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + |