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-rw-r--r--ChangeLog37
-rw-r--r--src/arch/arm/v7/helpers.h7
-rw-r--r--src/arch/arm/v7/opcodes/opcodes_tmp_arm.h1
-rw-r--r--src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h10
-rw-r--r--src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h1
-rw-r--r--src/arch/arm/v7/opdefs/Makefile.am2
-rw-r--r--src/arch/arm/v7/opdefs/adc_A882.d2
-rw-r--r--src/arch/arm/v7/opdefs/bic_A8822.d2
-rw-r--r--src/arch/arm/v7/opdefs/cmp_A8837.d2
-rw-r--r--src/arch/arm/v7/opdefs/cmp_A8838.d4
-rw-r--r--src/arch/arm/v7/opdefs/eor_A8847.d2
-rw-r--r--src/arch/arm/v7/opdefs/movt_A88106.d67
-rw-r--r--src/arch/arm/v7/opdefs/mvn_A88116.d2
-rw-r--r--src/arch/arm/v7/opdefs/rsb_A88152.d2
-rw-r--r--src/arch/arm/v7/opdefs/sub_A88223.d2
-rw-r--r--src/arch/arm/v7/opdefs/sub_A88225.d116
-rw-r--r--src/arch/arm/v7/opdefs/yield_A88426.d2
-rw-r--r--src/arch/arm/v7/thumb_32.c4
18 files changed, 241 insertions, 24 deletions
diff --git a/ChangeLog b/ChangeLog
index b02c2cb..8943ab8 100644
--- a/ChangeLog
+++ b/ChangeLog
@@ -1,3 +1,40 @@
+15-01-16 Cyrille Bagard <nocbos@gmail.com>
+
+ * src/arch/arm/v7/helpers.h:
+ Create a virtual macro helper named 'Imm16'.
+
+ * src/arch/arm/v7/opcodes/opcodes_tmp_arm.h:
+ * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h:
+ * src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h:
+ Update missing prototypes.
+
+ * src/arch/arm/v7/opdefs/adc_A882.d:
+ * src/arch/arm/v7/opdefs/bic_A8822.d:
+ * src/arch/arm/v7/opdefs/cmp_A8837.d:
+ * src/arch/arm/v7/opdefs/cmp_A8838.d:
+ * src/arch/arm/v7/opdefs/eor_A8847.d:
+ Fix mistakes between lower cases and upper cases in encodings.
+
+ * src/arch/arm/v7/opdefs/Makefile.am:
+ Add new definitions to ARMV7_DEFS.
+
+ * src/arch/arm/v7/opdefs/movt_A88106.d:
+ New entry: support a new ARMv7 instruction.
+
+ * src/arch/arm/v7/opdefs/mvn_A88116.d:
+ * src/arch/arm/v7/opdefs/rsb_A88152.d:
+ * src/arch/arm/v7/opdefs/sub_A88223.d:
+ Fix mistakes between lower cases and upper cases in encodings.
+
+ * src/arch/arm/v7/opdefs/sub_A88225.d:
+ New entry: support a new ARMv7 instruction.
+
+ * src/arch/arm/v7/opdefs/yield_A88426.d:
+ Fix mistakes between lower cases and upper cases in encodings.
+
+ * src/arch/arm/v7/thumb_32.c:
+ Fix a bug due to typo: b1111 vs b11111.
+
15-01-15 Cyrille Bagard <nocbos@gmail.com>
* src/dialogs/export.c:
diff --git a/src/arch/arm/v7/helpers.h b/src/arch/arm/v7/helpers.h
index 919611e..0a1d934 100644
--- a/src/arch/arm/v7/helpers.h
+++ b/src/arch/arm/v7/helpers.h
@@ -39,6 +39,13 @@
+#define Imm16(imm16) \
+ ({ \
+ GArchOperand *__result; \
+ __result = g_imm_operand_new_from_value(MDS_16_BITS_UNSIGNED, (uint16_t)imm16); \
+ __result; \
+ })
+
#define ARMExpandImm_C(imm12, c) \
({ \
GArchOperand *__result; \
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
index 4fbf93d..36e2193 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_arm.h
@@ -8,7 +8,6 @@
#define armv7_read_arm_instr_ldm_ldmia_ldmfd_arm(r) NULL
#define armv7_read_arm_instr_ldm_user_registers(r) NULL
#define armv7_read_arm_instr_lsr_immediate(r) NULL
-#define armv7_read_arm_instr_movt(r) NULL
#define armv7_read_arm_instr_ror_immediate(r) NULL
#define armv7_read_arm_instr_rrx(r) NULL
#define armv7_read_arm_instr_stmda_stmed(r) NULL
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
index 990d1c6..b30a543 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_16.h
@@ -1,16 +1,11 @@
#ifndef thumb_16_def_tmp_h
#define thumb_16_def_tmp_h
-#define armv7_read_thumb_16_instr_adc_register(r) NULL
#define armv7_read_thumb_16_instr_and_register(r) NULL
#define armv7_read_thumb_16_instr_asr_immediate(r) NULL
#define armv7_read_thumb_16_instr_asr_register(r) NULL
-#define armv7_read_thumb_16_instr_bic_register(r) NULL
#define armv7_read_thumb_16_instr_bkpt(r) NULL
#define armv7_read_thumb_16_instr_cmn_register(r) NULL
-#define armv7_read_thumb_16_instr_cmp_immediate(r) NULL
-#define armv7_read_thumb_16_instr_cmp_register(r) NULL
#define armv7_read_thumb_16_instr_cps_thumb(r) NULL
-#define armv7_read_thumb_16_instr_eor_register(r) NULL
#define armv7_read_thumb_16_instr_it(r) NULL
#define armv7_read_thumb_16_instr_ldm_ldmia_ldmfd_thumb(r) NULL
#define armv7_read_thumb_16_instr_ldrb_register(r) NULL
@@ -22,13 +17,11 @@
#define armv7_read_thumb_16_instr_lsr_immediate(r) NULL
#define armv7_read_thumb_16_instr_lsr_register(r) NULL
#define armv7_read_thumb_16_instr_mul(r) NULL
-#define armv7_read_thumb_16_instr_mvn_register(r) NULL
#define armv7_read_thumb_16_instr_orr_register(r) NULL
#define armv7_read_thumb_16_instr_rev(r) NULL
#define armv7_read_thumb_16_instr_rev16(r) NULL
#define armv7_read_thumb_16_instr_revsh(r) NULL
#define armv7_read_thumb_16_instr_ror_register(r) NULL
-#define armv7_read_thumb_16_instr_rsb_immediate(r) NULL
#define armv7_read_thumb_16_instr_sbc_register(r) NULL
#define armv7_read_thumb_16_instr_setend(r) NULL
#define armv7_read_thumb_16_instr_sev(r) NULL
@@ -38,8 +31,6 @@
#define armv7_read_thumb_16_instr_strh_register(r) NULL
#define armv7_read_thumb_16_instr_str_register(r) NULL
#define armv7_read_thumb_16_instr_sub_immediate_thumb(r) NULL
-#define armv7_read_thumb_16_instr_sub_register(r) NULL
-#define armv7_read_thumb_16_instr_sub_sp_minus_immediate(r) NULL
#define armv7_read_thumb_16_instr_svc_previously_swi(r) NULL
#define armv7_read_thumb_16_instr_sxtb(r) NULL
#define armv7_read_thumb_16_instr_sxth(r) NULL
@@ -49,5 +40,4 @@
#define armv7_read_thumb_16_instr_uxth(r) NULL
#define armv7_read_thumb_16_instr_wfe(r) NULL
#define armv7_read_thumb_16_instr_wfi(r) NULL
-#define armv7_read_thumb_16_instr_yield(r) NULL
#endif
diff --git a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
index 4ed909c..115b515 100644
--- a/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
+++ b/src/arch/arm/v7/opcodes/opcodes_tmp_thumb_32.h
@@ -21,7 +21,6 @@
#define armv7_read_thumb_32_instr_ldrt(r) NULL
#define armv7_read_thumb_32_instr_lsl_register(r) NULL
#define armv7_read_thumb_32_instr_lsr_register(r) NULL
-#define armv7_read_thumb_32_instr_movt(r) NULL
#define armv7_read_thumb_32_instr_mrs(r) NULL
#define armv7_read_thumb_32_instr_mrs_banked_register(r) NULL
#define armv7_read_thumb_32_instr_msr_banked_register(r) NULL
diff --git a/src/arch/arm/v7/opdefs/Makefile.am b/src/arch/arm/v7/opdefs/Makefile.am
index 223cf41..44dda82 100644
--- a/src/arch/arm/v7/opdefs/Makefile.am
+++ b/src/arch/arm/v7/opdefs/Makefile.am
@@ -57,6 +57,7 @@ ARMV7_DEFS = \
mov_A88102.d \
mov_A88103.d \
mov_A88104.d \
+ movt_A88106.d \
mul_A88114.d \
mvn_A88115.d \
mvn_A88116.d \
@@ -78,6 +79,7 @@ ARMV7_DEFS = \
strb_A88206.d \
sub_A88222.d \
sub_A88223.d \
+ sub_A88225.d \
teq_A88237.d \
teq_A88238.d \
tst_A88240.d \
diff --git a/src/arch/arm/v7/opdefs/adc_A882.d b/src/arch/arm/v7/opdefs/adc_A882.d
index 9c62b24..a43cadb 100644
--- a/src/arch/arm/v7/opdefs/adc_A882.d
+++ b/src/arch/arm/v7/opdefs/adc_A882.d
@@ -23,7 +23,7 @@
@title ADC (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 0 1 0 1 Rm(3) Rdn(3)
diff --git a/src/arch/arm/v7/opdefs/bic_A8822.d b/src/arch/arm/v7/opdefs/bic_A8822.d
index 4ad55cb..03f7948 100644
--- a/src/arch/arm/v7/opdefs/bic_A8822.d
+++ b/src/arch/arm/v7/opdefs/bic_A8822.d
@@ -23,7 +23,7 @@
@title BIC (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 1 1 0 Rm(3) Rdn(3)
diff --git a/src/arch/arm/v7/opdefs/cmp_A8837.d b/src/arch/arm/v7/opdefs/cmp_A8837.d
index 24587df..bcfe5d2 100644
--- a/src/arch/arm/v7/opdefs/cmp_A8837.d
+++ b/src/arch/arm/v7/opdefs/cmp_A8837.d
@@ -23,7 +23,7 @@
@title CMP (immediate)
-@encoding(T1) {
+@encoding(t1) {
@half 0 0 1 0 1 Rn(3) imm8(8)
diff --git a/src/arch/arm/v7/opdefs/cmp_A8838.d b/src/arch/arm/v7/opdefs/cmp_A8838.d
index a24df29..7ffe3d9 100644
--- a/src/arch/arm/v7/opdefs/cmp_A8838.d
+++ b/src/arch/arm/v7/opdefs/cmp_A8838.d
@@ -23,7 +23,7 @@
@title CMP (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 0 1 0 Rm(3) Rn(3)
@@ -38,7 +38,7 @@
}
-@encoding(T2) {
+@encoding(t2) {
@half 0 1 0 0 0 1 0 1 N(1) Rm(4) Rn(3)
diff --git a/src/arch/arm/v7/opdefs/eor_A8847.d b/src/arch/arm/v7/opdefs/eor_A8847.d
index eb651f3..3d7f5b5 100644
--- a/src/arch/arm/v7/opdefs/eor_A8847.d
+++ b/src/arch/arm/v7/opdefs/eor_A8847.d
@@ -23,7 +23,7 @@
@title EOR (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 0 0 0 1 Rm(3) Rdn(3)
diff --git a/src/arch/arm/v7/opdefs/movt_A88106.d b/src/arch/arm/v7/opdefs/movt_A88106.d
new file mode 100644
index 0000000..a5ad4f1
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/movt_A88106.d
@@ -0,0 +1,67 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Foobar. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title MOVT
+
+@encoding(T1) {
+
+ @word 1 1 1 1 0 i(1) 1 0 1 1 0 0 imm4(4) 0 imm3(3) Rd((4) imm8(8)
+
+ @syntax <Rd> <imm16>
+
+ @conv {
+
+ Rd = Register(Rd)
+ imm16 = Imm16(imm4:i:imm3:imm8)
+
+ }
+
+ @rules {
+
+ //if d IN {13,15} then UNPREDICTABLE;
+
+ }
+
+}
+
+@encoding(A1) {
+
+ @word cond(4) 0 0 1 1 0 1 0 0 imm4(4) Rd(4) imm12(12)
+
+ @syntax {c} <Rd> <imm16>
+
+ @conv {
+
+ c = Condition(cond)
+ Rd = Register(Rd)
+ imm16 = Imm16(imm4:imm12)
+
+ }
+
+ @rules {
+
+ //if d == 15 then UNPREDICTABLE;
+
+ }
+
+}
diff --git a/src/arch/arm/v7/opdefs/mvn_A88116.d b/src/arch/arm/v7/opdefs/mvn_A88116.d
index 7e9434c..3c97db4 100644
--- a/src/arch/arm/v7/opdefs/mvn_A88116.d
+++ b/src/arch/arm/v7/opdefs/mvn_A88116.d
@@ -23,7 +23,7 @@
@title MVN (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 1 1 1 Rm(3) Rd(3)
diff --git a/src/arch/arm/v7/opdefs/rsb_A88152.d b/src/arch/arm/v7/opdefs/rsb_A88152.d
index 320d62e..f7bee59 100644
--- a/src/arch/arm/v7/opdefs/rsb_A88152.d
+++ b/src/arch/arm/v7/opdefs/rsb_A88152.d
@@ -23,7 +23,7 @@
@title RSB (immediate)
-@encoding(T1) {
+@encoding(t1) {
@half 0 1 0 0 0 0 1 0 0 1 Rn(3) Rd(3)
diff --git a/src/arch/arm/v7/opdefs/sub_A88223.d b/src/arch/arm/v7/opdefs/sub_A88223.d
index 025139f..3693bc4 100644
--- a/src/arch/arm/v7/opdefs/sub_A88223.d
+++ b/src/arch/arm/v7/opdefs/sub_A88223.d
@@ -23,7 +23,7 @@
@title SUB (register)
-@encoding(T1) {
+@encoding(t1) {
@half 0 0 0 1 1 0 1 Rm(3) Rn(3) Rd(3)
diff --git a/src/arch/arm/v7/opdefs/sub_A88225.d b/src/arch/arm/v7/opdefs/sub_A88225.d
new file mode 100644
index 0000000..9c29624
--- /dev/null
+++ b/src/arch/arm/v7/opdefs/sub_A88225.d
@@ -0,0 +1,116 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2014 Cyrille Bagard
+ *
+ * This file is part of Chrysalide.
+ *
+ * Chrysalide is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * Chrysalide is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with Foobar. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SUB (SP minus immediate)
+
+@encoding(t1) {
+
+ @half 1 0 1 1 0 0 0 0 1 imm7(7)
+
+ @syntax <SP1> <SP2> <const>
+
+ @conv {
+
+ SP1 = Register(13)
+ SP2 = Register(13)
+ const = ZeroExtend(imm7:'00', 9, 32);
+
+ }
+
+ @rules {
+
+ //setflags = FALSE
+
+ }
+
+}
+
+@encoding(T2) {
+
+ @word 1 1 1 1 0 i(1) 0 1 1 0 1 S(1) 1 1 0 1 0 imm3(3) Rd(4) imm8(8)
+
+ @syntax {S} ".W" <Rd> <SP> <const>
+
+ @conv {
+
+ S = SetFlags(S)
+ Rd = Register(Rd)
+ SP = Register(13)
+ const = ThumbExpandImm(i:imm3:imm8)
+
+ }
+
+ @rules {
+
+ //if Rd == '1111' && S == '1' then SEE CMP (immediate);
+ //if d == 15 && S == '0' then UNPREDICTABLE;
+
+ }
+
+}
+
+@encoding(T3) {
+
+ @word 1 1 1 1 0 i(1) 1 0 1 0 1 0 1 1 0 1 0 imm3(3) Rd(4) imm8(8)
+
+ @syntax "subw" <Rd> <SP> <const>
+
+ @conv {
+
+ Rd = Register(Rd)
+ SP = Register(13)
+ const = ZeroExtend((i:imm3:imm8, 12, 32)
+
+ }
+
+ @rules {
+
+ //if d == 15 then UNPREDICTABLE;
+
+ }
+
+}
+
+@encoding(A1) {
+
+ @word cond(4) 0 0 1 0 0 1 0 S(1) 1 1 0 1 Rd(4) imm12(12)
+
+ @syntax {S} {c} <Rd> <SP> <const>
+
+ @conv {
+
+ S = SetFlags(S)
+ c = Condition(cond)
+ Rd = Register(Rd)
+ SP = Register(13)
+ const = ARMExpandImm(imm12)
+
+ }
+
+ @rules {
+
+ //if Rd == '1111' && S == '1' then SEE SUBS PC, LR and related instructions;
+
+ }
+
+}
diff --git a/src/arch/arm/v7/opdefs/yield_A88426.d b/src/arch/arm/v7/opdefs/yield_A88426.d
index 6de27d1..c0b4be0 100644
--- a/src/arch/arm/v7/opdefs/yield_A88426.d
+++ b/src/arch/arm/v7/opdefs/yield_A88426.d
@@ -23,7 +23,7 @@
@title YIELD
-@encoding(T1) {
+@encoding(t1) {
@half 1 0 1 1 1 1 1 1 0 0 0 1 0 0 0 0
diff --git a/src/arch/arm/v7/thumb_32.c b/src/arch/arm/v7/thumb_32.c
index 8ea6ecb..757abc4 100644
--- a/src/arch/arm/v7/thumb_32.c
+++ b/src/arch/arm/v7/thumb_32.c
@@ -263,7 +263,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
case b0010:
- if (rn == b11111)
+ if (rn == b1111)
result = armv7_read_thumb_32_instr_mov_immediate(raw);
else
result = armv7_read_thumb_32_instr_orr_immediate(raw);
@@ -272,7 +272,7 @@ static GArchInstruction *process_armv7_thumb_32_data_processing_modified_immedia
case b0011:
- if (rn == b11111)
+ if (rn == b1111)
result = armv7_read_thumb_32_instr_mvn_immediate(raw);
else
result = armv7_read_thumb_32_instr_orn_immediate(raw);
generated by cgit v0.11.2-87-g4458 at 2024-12-25 05:53:54 (GMT)