1 files changed, 149 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88180_smlald.d b/plugins/arm/v7/opdefs/A88180_smlald.d
new file mode 100644
index 0000000..39a475c
--- /dev/null
+++ b/plugins/arm/v7/opdefs/A88180_smlald.d
@@ -0,0 +1,149 @@
+
+/* Chrysalide - Outil d'analyse de fichiers binaires
+ * ##FILE## - traduction d'instructions ARMv7
+ *
+ * Copyright (C) 2017 Cyrille Bagard
+ *
+ *  This file is part of Chrysalide.
+ *
+ *  Chrysalide is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 3 of the License, or
+ *  (at your option) any later version.
+ *
+ *  Chrysalide is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with Chrysalide.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+@title SMLALD
+
+@id 173
+
+@desc {
+
+	Signed Multiply Accumulate Long Dual performs two signed 16 × 16-bit multiplications. It adds the products to a 64-bit accumulate operand. Optionally, the instruction can exchange the halfwords of the second operand before performing the arithmetic. This produces top × bottom and bottom × top multiplication. Overflow is possible during this instruction, but only as a result of the 64-bit addition. This overflow is not detected if it occurs. Instead, the result wraps around modulo 264.
+
+}
+
+@encoding (T1) {
+
+	@word 1 1 1 1 1 0 1 1 1 1 0 0 Rn(4) RdLo(4) RdHi(4) 1 1 0 M(1) Rm(4)
+
+	@syntax {
+
+		@subid 523
+
+		@assert {
+
+			M == 0
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlald reg_DLO reg_DHI reg_N reg_M
+
+	}
+
+	@syntax {
+
+		@subid 524
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlaldx reg_DLO reg_DHI reg_N reg_M
+
+	}
+
+}
+
+@encoding (A1) {
+
+	@word cond(4) 0 1 1 1 0 1 0 0 RdHi(4) RdLo(4) Rm(4) 0 0 M(1) 1 Rn(4)
+
+	@syntax {
+
+		@subid 525
+
+		@assert {
+
+			M == 0
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlald reg_DLO reg_DHI reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+	@syntax {
+
+		@subid 526
+
+		@assert {
+
+			M == 1
+
+		}
+
+		@conv {
+
+			reg_DLO = Register(RdLo)
+			reg_DHI = Register(RdHi)
+			reg_N = Register(Rn)
+			reg_M = Register(Rm)
+
+		}
+
+		@asm smlaldx reg_DLO reg_DHI reg_N reg_M
+
+		@rules {
+
+			check g_arm_instruction_set_cond(cond)
+
+		}
+
+	}
+
+}
+