diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/A88241_tst.d')
-rw-r--r-- | plugins/arm/v7/opdefs/A88241_tst.d | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/A88241_tst.d b/plugins/arm/v7/opdefs/A88241_tst.d new file mode 100644 index 0000000..98e820e --- /dev/null +++ b/plugins/arm/v7/opdefs/A88241_tst.d @@ -0,0 +1,104 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2017 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title TST (register) + +@id 233 + +@desc { + + Test (register) performs a bitwise AND operation on a register value and an optionally-shifted register value. It updates the condition flags based on the result, and discards the result. + +} + +@encoding (t1) { + + @half 0 1 0 0 0 0 1 0 0 0 Rm(3) Rn(3) + + @syntax { + + @subid 722 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + + } + + @asm tst reg_N reg_M + + } + +} + +@encoding (T2) { + + @word 1 1 1 0 1 0 1 0 0 0 0 1 Rn(4) 0 imm3(3) 1 1 1 1 imm2(2) type(2) Rm(4) + + @syntax { + + @subid 723 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm3:imm2) + + } + + @asm tst.w reg_N reg_M ?shift + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 0 1 0 0 0 1 Rn(4) 0 0 0 0 imm5(5) type(2) 0 Rm(4) + + @syntax { + + @subid 724 + + @conv { + + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm tst reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) + + } + + } + +} + |