diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/add_A887.d')
-rw-r--r-- | plugins/arm/v7/opdefs/add_A887.d | 65 |
1 files changed, 53 insertions, 12 deletions
diff --git a/plugins/arm/v7/opdefs/add_A887.d b/plugins/arm/v7/opdefs/add_A887.d index 18400a6..400e179 100644 --- a/plugins/arm/v7/opdefs/add_A887.d +++ b/plugins/arm/v7/opdefs/add_A887.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,28 +23,69 @@ @title ADD (register, ARM) -@desc This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 6 + +@desc { + + This instruction adds a register value and an optionally-shifted register value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (A1) { @word cond(4) 0 0 0 0 1 0 0 S(1) Rn(4) Rd(4) imm5(5) type(2) 0 Rm(4) - @syntax <reg_D> <reg_N> <reg_M> <?shift> + @syntax { + + @assert { + + S == 0 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm add ?reg_D reg_N reg_M ?shift - @conv { + @rules { - reg_D = Register(Rd) - reg_N = Register(Rn) - reg_M = Register(Rm) - setflags = (S == '1') - shift = DecodeImmShift(type, imm5) + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + reg_M = Register(Rm) + shift = DecodeImmShift(type, imm5) + + } + + @asm adds ?reg_D reg_N reg_M ?shift + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |