diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/eor_A8846.d')
-rw-r--r-- | plugins/arm/v7/opdefs/eor_A8846.d | 101 |
1 files changed, 82 insertions, 19 deletions
diff --git a/plugins/arm/v7/opdefs/eor_A8846.d b/plugins/arm/v7/opdefs/eor_A8846.d index 38dc858..3dc39cc 100644 --- a/plugins/arm/v7/opdefs/eor_A8846.d +++ b/plugins/arm/v7/opdefs/eor_A8846.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,26 +23,55 @@ @title EOR (immediate) -@desc Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. +@id 45 + +@desc { + + Bitwise Exclusive OR (immediate) performs a bitwise Exclusive OR of a register value and an immediate value, and writes the result to the destination register. It can optionally update the condition flags based on the result. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 1 0 0 S(1) Rn(4) 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm eor ?reg_D reg_N const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm eors ?reg_D reg_N const } @@ -52,21 +81,55 @@ @word cond(4) 0 0 1 0 0 0 1 S(1) Rn(4) Rd(4) imm12(12) - @syntax <reg_D> <reg_N> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - reg_N = Register(Rn) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eor ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + reg_N = Register(Rn) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm eors ?reg_D reg_N const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |