diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/ldr_A8866.d')
-rw-r--r-- | plugins/arm/v7/opdefs/ldr_A8866.d | 132 |
1 files changed, 0 insertions, 132 deletions
diff --git a/plugins/arm/v7/opdefs/ldr_A8866.d b/plugins/arm/v7/opdefs/ldr_A8866.d deleted file mode 100644 index e676fec..0000000 --- a/plugins/arm/v7/opdefs/ldr_A8866.d +++ /dev/null @@ -1,132 +0,0 @@ - -/* Chrysalide - Outil d'analyse de fichiers binaires - * ##FILE## - traduction d'instructions ARMv7 - * - * Copyright (C) 2017 Cyrille Bagard - * - * This file is part of Chrysalide. - * - * Chrysalide is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 3 of the License, or - * (at your option) any later version. - * - * Chrysalide is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with Chrysalide. If not, see <http://www.gnu.org/licenses/>. - */ - - -@title LDR (register, ARM) - -@id 65 - -@desc { - - Load Register (register) calculates an address from a base register value and an offset register value, loads a word from memory, and writes it to a register. The offset register value can optionally be shifted. For information about memory accesses, see Memory accesses on page A8-294. - -} - -@encoding (A1) { - - @word cond(4) 0 1 1 P(1) U(1) 0 W(1) 1 Rn(4) Rt(4) imm5(5) type(2) 0 Rm(4) - - @syntax { - - @subid 182 - - @assert { - - P == 1 - P == 1 && W == 0 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessOffsetExtended(reg_N, reg_M, shift) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 183 - - @assert { - - P == 1 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPreIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - - @syntax { - - @subid 184 - - @assert { - - P == 0 - P == 0 || W == 1 - - } - - @conv { - - reg_T = Register(Rt) - reg_N = Register(Rn) - reg_M = Register(Rm) - shift = DecodeImmShift(type, imm5) - maccess = MemAccessPostIndexedExtended(reg_N, reg_M, shift) - - } - - @asm ldr reg_T maccess - - @rules { - - check g_arm_instruction_set_cond(cond) - - } - - } - -} - |