diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/mov_A88102.d')
-rw-r--r-- | plugins/arm/v7/opdefs/mov_A88102.d | 124 |
1 files changed, 124 insertions, 0 deletions
diff --git a/plugins/arm/v7/opdefs/mov_A88102.d b/plugins/arm/v7/opdefs/mov_A88102.d new file mode 100644 index 0000000..d96baab --- /dev/null +++ b/plugins/arm/v7/opdefs/mov_A88102.d @@ -0,0 +1,124 @@ + +/* Chrysalide - Outil d'analyse de fichiers binaires + * ##FILE## - traduction d'instructions ARMv7 + * + * Copyright (C) 2015 Cyrille Bagard + * + * This file is part of Chrysalide. + * + * Chrysalide is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 3 of the License, or + * (at your option) any later version. + * + * Chrysalide is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with Foobar. If not, see <http://www.gnu.org/licenses/>. + */ + + +@title MOV (immediate) + +@desc Move (immediate) writes an immediate value to the destination register. It can optionally update the condition flags based on the value. + +@encoding (t1) { + + @half 0 0 1 0 0 Rd(3) imm8(8) + + @syntax "movs" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm8, 32) + + } + +} + +@encoding (T2) { + + @word 1 1 1 1 0 i(1) 0 0 0 1 0 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call ExtendKeyword(".w") + + } + +} + +@encoding (T3) { + + @word 1 1 1 1 0 i(1) 1 0 0 1 0 0 imm4(4) 0 imm3(3) Rd(4) imm8(8) + + @syntax "movw" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:i:imm3:imm8, 32) + + } + +} + +@encoding (A1) { + + @word cond(4) 0 0 1 1 1 0 1 S(1) 0 0 0 0 Rd(4) imm12(12) + + @syntax <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + setflags = (S == '1') + imm32 = ARMExpandImm_C(imm12, 0) + + } + + @rules { + + if (setflags); chk_call ExtendKeyword("s") + chk_call StoreCondition(cond) + + } + +} + +@encoding (A2) { + + @word cond(4) 0 0 1 1 0 0 0 0 imm4(4) Rd(4) imm12(12) + + @syntax "movw" <reg_D> <imm32> + + @conv { + + reg_D = Register(Rd) + imm32 = ZeroExtend(imm4:imm12, 32) + + } + + @rules { + + chk_call StoreCondition(cond) + + } + +} + |