diff options
Diffstat (limited to 'plugins/arm/v7/opdefs/mvn_A88115.d')
-rw-r--r-- | plugins/arm/v7/opdefs/mvn_A88115.d | 95 |
1 files changed, 78 insertions, 17 deletions
diff --git a/plugins/arm/v7/opdefs/mvn_A88115.d b/plugins/arm/v7/opdefs/mvn_A88115.d index 2955439..c27b3a5 100644 --- a/plugins/arm/v7/opdefs/mvn_A88115.d +++ b/plugins/arm/v7/opdefs/mvn_A88115.d @@ -2,7 +2,7 @@ /* Chrysalide - Outil d'analyse de fichiers binaires * ##FILE## - traduction d'instructions ARMv7 * - * Copyright (C) 2015 Cyrille Bagard + * Copyright (C) 2017 Cyrille Bagard * * This file is part of Chrysalide. * @@ -23,25 +23,53 @@ @title MVN (immediate) -@desc Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. +@id 114 + +@desc { + + Bitwise NOT (immediate) writes the bitwise inverse of an immediate value to the destination register. It can optionally update the condition flags based on the value. + +} @encoding (T1) { @word 1 1 1 1 0 i(1) 0 0 0 1 1 S(1) 1 1 1 1 0 imm3(3) Rd(4) imm8(8) - @syntax <reg_D> <imm32> + @syntax { + + @assert { + + S == 0 + + } + + @conv { - @conv { + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ThumbExpandImm_C(i:imm3:imm8, 0) + } + + @asm mvn reg_D const } - @rules { + @syntax { + + @assert { + + S == 1 + + } - if (setflags); chk_call ExtendKeyword("s") + @conv { + + reg_D = Register(Rd) + const = ThumbExpandImm_C(i:imm3:imm8, APSR_C) + + } + + @asm mvns reg_D const } @@ -51,20 +79,53 @@ @word cond(4) 0 0 1 1 1 1 1 S(1) 0 0 0 0 Rd(4) imm12(12) - @syntax <reg_D> <imm32> + @syntax { + + @assert { - @conv { + S == 0 - reg_D = Register(Rd) - setflags = (S == '1') - imm32 = ARMExpandImm_C(imm12, 0) + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvn reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) + + } } - @rules { + @syntax { + + @assert { + + S == 1 + + } + + @conv { + + reg_D = Register(Rd) + const = ARMExpandImm_C(imm12, APSR_C) + + } + + @asm mvns reg_D const + + @rules { + + check g_arm_instruction_set_cond(cond) - if (setflags); chk_call ExtendKeyword("s") - chk_call StoreCondition(cond) + } } |